58 lines
1.3 KiB
VHDL
58 lines
1.3 KiB
VHDL
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-- hu
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-- Update H using stream of weights
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use work.pkg_sbs.all;
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entity hu is
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port (
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clk, rstn : in bit;
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cfg_hu : in bit_vector(BW_HU_CFG -1 downto 0); -- Config
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ena_w : in bit; -- New weight
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is_ini : in bit; -- First vector (get w and h when ena)
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is_fst : in bit; -- Fist component in vector
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ena_ho : out bit; -- Signal a valid ho value
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wi : in real; -- stream of weights
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hi : in real; -- stream of state
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ho : out real); -- stream of states
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end entity hu;
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architecture rtlf of hu is
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signal ctr_hu : bit_vector(BW_HU_CTR-1 downto 0);
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signal loc_h : bit_vector(ADDR_H_MAX-1 downto 0);
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signal eps : real;
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begin -- architecture rtlf
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i_hu_dp: entity work.hu_dp
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port map (
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clk => clk,
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rstn => rstn,
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eps => eps,
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ctr_hu => ctr_hu,
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loc_h => loc_h,
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wi => wi,
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hi => hi,
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ho => ho);
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i_hu_ctr: entity work.hu_ctr
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port map (
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clk => clk,
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rstn => rstn,
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eps => eps,
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cfg_hu => cfg_hu,
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loc_h => loc_h,
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ena_w => ena_w,
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is_ini => is_ini,
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is_fst => is_fst,
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ena_ho => ena_ho,
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ctr_hu => ctr_hu);
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end architecture rtlf;
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