50 lines
1 KiB
VHDL
50 lines
1 KiB
VHDL
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-- Implementation of a synchronous single port memory
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library ieee;
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use ieee.numeric_bit.all;
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entity mem_sync is
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generic(
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BA : natural := 7); -- log2 addresses
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port(
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clk : in bit;
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wr, rd : in bit;
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addr : in bit_vector(BA-1 downto 0);
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dti : in real;
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dto : out real);
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end entity mem_sync;
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library ieee;
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use ieee.numeric_bit.all;
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architecture beh of mem_sync is
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signal addr_rg : unsigned(BA-1 downto 0);
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begin -- architecture beh
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mem: process (clk) is
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constant mem_size : natural := 2**(addr'length);
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type mem_ty is array (0 to mem_size-1) of real;
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variable w_mem : mem_ty;
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begin -- process mem
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if clk'event and clk = '1' then -- rising clock edge
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addr_rg <= unsigned(addr);
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if wr='1' then
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w_mem(to_integer(addr_rg)) := dti;
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end if;
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if rd='1' then
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dto <= w_mem(to_integer(addr_rg));
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end if;
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end if;
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end process mem;
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end architecture beh;
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-- Local Variables:
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-- compile-command: "ghdl -a --std=00 --workdir=../do_sim/ mem_sync.vhd"
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-- End:
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