-- Implementation of a synchronous single port memory

library ieee;
use ieee.numeric_bit.all;


entity mem_sync is
  generic(
    BA : natural := 7); -- log2 addresses
  port(
    clk : in bit;
    wr, rd : in bit;
    addr : in bit_vector(BA-1 downto 0);
    dti : in real;
    dto : out real);
end entity mem_sync;


library ieee;
use ieee.numeric_bit.all;


architecture beh of mem_sync is

  signal addr_rg : unsigned(BA-1 downto 0);

begin  -- architecture beh
  
  mem: process (clk) is
    constant mem_size : natural := 2**(addr'length);
    type mem_ty is array (0 to mem_size-1) of real;
    variable w_mem : mem_ty;
  begin  -- process mem
    if clk'event and clk = '1' then  -- rising clock edge
      addr_rg <= unsigned(addr);      
      if wr='1' then
        w_mem(to_integer(addr_rg)) := dti;
      end if;
      if rd='1' then
        dto <= w_mem(to_integer(addr_rg));
      end if;
    end if;
  end process mem;

end architecture beh;
  
 -- Local Variables:
 -- compile-command: "ghdl -a --std=00  --workdir=../do_sim/  mem_sync.vhd"
 -- End: