-- Simple multiply with adder to check speed

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;


entity mua is
  
  generic (
    B : natural := 10);                 -- bitwidth

  port (
    clk, arstn   : in std_logic;        
    dt_mv, dt_mc : in  std_logic_vector(B-1 downto 0);   -- input for multiplicatin
    dt_add       : in  std_logic_vector(2*B-1 downto 0);   -- constant to add
    dt_mua       : out std_logic_vector(2*B-1 downto 0));  -- output

end entity mua;


library ieee;
use ieee.numeric_std.all;

architecture rtl of mua is

  signal dt_mv_rg, dt_mc_rg      : unsigned(B-1 downto 0);
  signal dt_add_rg               : unsigned(2*B-1 downto 0);
  signal dt_mua_rg, dt_mua_nxt   : unsigned(2*B-1 downto 0);
  
begin  -- architecture rtl

  dt_mua_nxt <= dt_mv_rg * dt_mc_rg + dt_add_rg;

  dt_mua <= std_logic_vector(dt_mua_rg);
  
  reg: process (clk, arstn) is
  begin  -- process reg
    if arstn = '0' then                 -- asynchronous reset (active low)
        dt_mv_rg <= (others=>'0');
        dt_mc_rg <= (others=>'0');
        dt_add_rg <= (others=>'0');
        dt_mua_rg <= (others=>'0');
    elsif clk'event and clk = '1' then  -- rising clock edge
        dt_mv_rg <= unsigned(dt_mv);
        dt_mc_rg <= unsigned(dt_mc);
        dt_add_rg <= unsigned(dt_add);
        dt_mua_rg <= dt_mua_nxt;
    end if;
  end process reg;

end architecture rtl;