-- hu_ctr
-- Control path for Update H using stream of weights

use work.pkg_sbs.all;

entity hu_ctr is
  port (
    clk, rstn  : in  bit;
    cfg_hu     : in bit_vector(BW_HU_CFG -1 downto 0); -- Config
    ena_w      : in bit;         -- New weight
    is_ini     : in bit;         -- First vector (get w and h when ena)
    is_fst     : in bit;         -- Fist component in vector
    loc_h      : in bit_vector(ADDR_H_MAX-1 downto 0); -- Current location in H
    ena_ho     : out bit;        -- Signal a valid ho value
    eps        : out real; 
    ctr_hu     : out bit_vector(BW_HU_CTR-1 downto 0));   -- Control for data path

end entity hu_ctr;

library ieee;
use ieee.numeric_bit.all;

architecture beh of hu_ctr is

  signal ctr_sel_ini, ctr_sum_ini, ctr_update_sum, ctr_update_sum2 : bit;
  signal ctr_addr_rst,  ctr_addr_inc,  ctr_write_hw : bit;
  signal ctr_wr_hw, ctr_wr_hp : bit;

  -- Number of elements in H (currently fixed)
  constant MAX_LOC_H  : bit_vector(ADDR_H_MAX-1 downto 0) := bit_vector(to_unsigned(8, ADDR_H_MAX));

  --constant T : time := 10 ns;
  
begin  -- architecture beh

  eps <= 0.2;

  ctr_hu(0) <= ctr_sel_ini    ;
  ctr_hu(1) <= ctr_sum_ini    ;
  ctr_hu(2) <= ctr_update_sum ;
  ctr_hu(3) <= ctr_addr_rst   ;
  ctr_hu(4) <= ctr_addr_inc   ;
  ctr_hu(5) <= ctr_write_hw   ;
  ctr_hu(6) <= ctr_wr_hw      ;
  --ctr_hu(7) <= ctr_wr_hp      ; -- ctr_wr_hp and ctr_wr_hw are the same
  ctr_hu(7) <=  ctr_update_sum2  ;

  -- Code in first approximation
  ctr_sel_ini <= is_ini; 
  ctr_wr_hp <= ena_w; --is_ini;   
  ctr_wr_hw <= ena_w;
  ctr_sum_ini <= is_fst; 
  ctr_update_sum <= transport is_fst  after 7*T ;
  --ctr_update_sum2 <= transport ctr_update_sum after T;
  --ctr_update_sum <= '1' when (loc_h = MAX_LOC_H) else '0';
  
  ctr_addr_rst <= ctr_update_sum; 
  ctr_addr_inc <= ena_w and not ctr_addr_rst;

  ena_ho <= ena_w and not is_ini;

  rg: process (clk, rstn) is
  begin 
    if rstn = '0' then                 -- asynchronous reset (active low)
      ctr_update_sum2 <= '0';
    elsif clk'event and clk = '1' then  -- rising clock edge
      ctr_update_sum2 <= ctr_update_sum;
    end if;
  end process rg;
  
  
end architecture beh;