-- tst_hu
-- Testbench for Update H using stream of weights

use work.pkg_sbs.all;

entity tst_hu is
  
end entity tst_hu;


architecture tst of tst_hu is
  
  constant T : time := 10 ns;           -- Period
  
  signal clk, rstn : bit := '0';
  signal cfg_hu    : bit_vector(BW_HU_CFG -1 downto 0);
  signal ena_w     : bit;
  signal is_ini    : bit;
  signal is_fst    : bit;
  signal ena_ho    : bit;
  signal wi        : real := 0.0;
  signal hi        : real := 0.0;
  signal ho        : real;
  
begin  -- architecture tst

  clk <= not clk after T/2;
  rstn <= '0', '1' after T/2+T/4;
  
  i_hu: entity work.hu
    port map (
      clk    => clk,
      rstn   => rstn,
      cfg_hu => cfg_hu,
      ena_w  => ena_w,
      is_ini => is_ini,
      is_fst => is_fst,
      ena_ho => ena_ho,
      wi     => wi,
      hi     => hi,
      ho     => ho);

  process (clk) is
    type array_sol is array (natural range <>) of real;

    -- Example of solution from python
    constant h_sol : array_sol := (
      --0.1 , 0.2 , 0.3 , 0.0  , 0.01, 0.01, 0.1 , 0.28,
      0.01628 , 0.02056 , 0.03144 , 0.0      , 0.001228, 0.001588,    0.01228 , 0.039984,
      1.28343706e-04, 1.62085171e-04, 3.17669760e-04, 0.00000000e+00, 1.24077120e-05, 1.99630656e-05, 1.84671552e-04, 3.05349811e-04,
      2.17637063e-08, 2.74853687e-08, 5.38684101e-08, 0.00000000e+00, 2.10402060e-09, 3.38520923e-09, 3.13154230e-08, 5.17792718e-08
      );

    variable idx : natural;
    
  begin  -- process
    if clk'event and clk = '1' then  -- rising clock edge
      if ena_ho='1' then
        if idx<h_sol'length-1 then
          if abs(ho-h_sol(idx)) > 1.0e-09 then
             report LF & ESC &  "[31;1m  [ERROR] h_sol= " & real'image(h_sol(idx)) &  ESC & "[0m" & LF severity error;            
          end if;
          idx := idx+1;
        end if;
        report LF & "[INFO] h_exp= " & real'image(ho) & LF severity note;
      end if;
    end if;
  end process;    


  process  is
    constant h : array_as_h := (0.1, 0.2, 0.3, 0.0, 0.01, 0.01, 0.1, 0.28);
  begin  -- process    
    hi <= 0.0;
    is_ini <= '0';
    wait for T/4 + T/2 + T;

    for n in 0 to 1 loop
      for ki in h'range loop
        hi <= h(ki);
        is_ini <= '1';        
        wait for T;
      end loop;  -- ki
      is_ini <= '0';        
      hi <= 0.0;
      --wait for T*(h'length+1)*3;    -- note +1 for void cycle
      wait for T*(2+(h'length+2)*3);    -- note +2 for void cycle
    end loop;  -- n
    wait;
  end process;

  
  process  is
    constant w0 : array_as_h := (0.3, 0.0, 0.01, 0.01, 0.1, 0.28, 0.1, 0.2);
    constant w1 : array_as_h := (0.01, 0.01, 0.1, 0.28, 0.1, 0.2, 0.3, 0.0);
    constant w2 : array_as_h := (0.125, 0.125, 0.125, 0.125, 0.125, 0.125, 0.125, 0.125);

    type array_w is array (0 to 2) of array_as_h;
    constant w : array_w := (w0, w1, w2);

  begin  -- process    
    ena_w <= '0';
    wi <= 0.0;
    wait for T/4 + T/2 + T;

    for n in 0 to 1 loop
      for kj in w'range loop
        is_fst <= '1', '0' after T;
        for ki in w0'range loop
          ena_w <= '1';
          wi <= w(kj)(ki);
          wait for T;
        end loop;  -- ki
        ena_w <= '0'; -- void cycle
        wait for 2*T; -- 
      end loop; -- kj
    end loop; -- n

    ena_w <= '0';
    wait for 4*T;
    report LF & LF & ESC & "[35;1m [TST] End simulation" & ESC & "[0m" & LF severity failure;
    
  end process;

  
end architecture tst;