136 lines
4.1 KiB
VHDL
136 lines
4.1 KiB
VHDL
use work.pkg_ufp.all;
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entity tst_pkg_ufp is
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end entity tst_pkg_ufp;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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architecture tst of tst_pkg_ufp is
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begin -- architecture tst
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process
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-- Define params of ufp
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constant BW : natural := 10;
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constant BE : natural := 3;
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constant EO : natural := 1;
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constant BO : natural := BW - BE -EO;
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variable r, r2 : real;
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variable ee_mm : std_logic_vector(BW-1 downto 0);
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variable mm : std_logic_vector(BW-1-BE downto 0);
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variable ee : std_logic_vector(BE-1 downto 0);
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constant r_ini : real := 0.0125;
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constant r_inc : real := 0.0125/4.0;
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constant N : natural := 10;
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procedure print (
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ar : in real;
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aee : in std_logic_vector(BE-1 downto 0);
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amm : in std_logic_vector(BW-1-BE downto 0)) is
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begin
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report LF & "[TST] " &
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"r=" & real'image(ar) & HT & HT &
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"ufp= " & integer'image(to_integer(unsigned(amm))) &
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" *2**(-" & integer'image(BO) & "- " & integer'image(to_integer(unsigned(aee))) & " )"
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severity note;
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end procedure;
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procedure tst_conv_r (
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aee : in std_logic_vector(BE-1 downto 0);
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amm : in std_logic_vector(BW-1-BE downto 0)) is
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variable ar : real;
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variable aee_mm : std_logic_vector(BW-1 downto 0);
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begin -- procedure tst_conv_r
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aee_mm := aee & amm;
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ar := ufp_to_real(aee_mm, BW, BE, EO);
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print(ar, aee, amm);
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aee_mm := real_to_ufp(ar, BW, BE, EO);
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print(ar, aee, amm);
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report LF & "[TST] ----------------------------------" severity note;
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end procedure tst_conv_r;
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constant ee_0min : std_logic_vector(BE-1 downto 0) := (others => '0');
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constant ee_1min : std_logic_vector(BE-1 downto 0) := (0 => '1', others => '0');
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constant ee_2min : std_logic_vector(BE-1 downto 0) := (1 => '1', others => '0');
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constant ee_0max : std_logic_vector(BE-1 downto 0) := (others => '1');
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constant ee_1max : std_logic_vector(BE-1 downto 0) := (0 => '0', others => '1');
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constant ee_2max : std_logic_vector(BE-1 downto 0) := (1 => '0', others => '1');
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constant mm_0min : std_logic_vector(BW-1-BE downto 0) := (others => '0');
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constant mm_1min : std_logic_vector(BW-1-BE downto 0) := (0 => '1', others => '0');
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constant mm_2min : std_logic_vector(BW-1-BE downto 0) := (1 => '1', others => '0');
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constant mm_0max : std_logic_vector(BW-1-BE downto 0) := (others => '1');
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constant mm_1max : std_logic_vector(BW-1-BE downto 0) := (0 => '0', others => '1');
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constant mm_2max : std_logic_vector(BW-1-BE downto 0) := (1 => '0', others => '1');
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begin
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if true then
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report LF & "[TST] Test corner examples =============================" severity note;
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-- Conversion from ee_mm to real
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tst_conv_r(ee_0max, mm_0min);
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tst_conv_r(ee_0max, mm_1min);
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tst_conv_r(ee_0max, mm_2min);
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tst_conv_r(ee_0max, mm_2max);
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tst_conv_r(ee_0max, mm_1max);
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tst_conv_r(ee_0max, mm_0max);
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tst_conv_r(ee_1max, mm_0min);
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tst_conv_r(ee_1max, mm_1min);
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tst_conv_r(ee_1max, mm_2min);
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tst_conv_r(ee_1max, mm_2max);
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tst_conv_r(ee_1max, mm_1max);
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tst_conv_r(ee_1max, mm_0max);
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tst_conv_r(ee_1min, mm_0min);
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tst_conv_r(ee_1min, mm_1min);
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tst_conv_r(ee_1min, mm_2min);
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tst_conv_r(ee_1min, mm_2max);
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tst_conv_r(ee_1min, mm_1max);
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tst_conv_r(ee_1min, mm_0max);
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tst_conv_r(ee_0min, mm_0min);
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tst_conv_r(ee_0min, mm_1min);
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tst_conv_r(ee_0min, mm_2min);
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tst_conv_r(ee_0min, mm_2max);
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tst_conv_r(ee_0min, mm_1max);
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tst_conv_r(ee_0min, mm_0max);
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end if;
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if true then
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report LF & "[TST] Test ramp =============================" severity note;
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-- Conersion from real to ee_mm
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r:= r_ini;
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for ki in 0 to N-1 loop
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ee_mm := real_to_ufp(r, BW, BE, EO);
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ee := ee_mm(BW-1 downto BW-BE);
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mm := ee_mm(BW-BE-1 downto 0);
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print(r, ee, mm);
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r2 := ufp_to_real(ee_mm, BW, BE, EO);
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print(r2, ee, mm);
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report LF & "[TST] ----------------------------------" severity note;
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r := r + r_inc;
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end loop; -- ki
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end if;
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`
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wait;
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end process;
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end architecture tst;
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