135 lines
4.8 KiB
VHDL
135 lines
4.8 KiB
VHDL
-- hu_dp
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-- Data path for Update H using stream of weights
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-- Trivial fix point implementation
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library ieee;
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use ieee.std_logic_1164.all;
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use work.pkg_sbs.all;
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entity hu_dp is
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generic (
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K : natural := 3; -- additional bits for sum
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B : natural := 10); -- bitwidth of input
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port (
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clk, rstn : in std_logic;
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ctr_hu : in std_logic_vector(BW_HU_CTR-1 downto 0); -- Control for data path
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loc_h : out std_logic_vector(ADDR_H_MAX-1 downto 0); -- Current location in H
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eps : in std_logic_vector(B-1 downto 0);
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wi : in std_logic_vector(B-1 downto 0); -- stream of weights
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hi : in std_logic_vector(B-1 downto 0); -- stream of state
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ho : out std_logic_vector(B-1 downto 0)); -- stream of states
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end entity hu_dp;
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library ieee;
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use ieee.numeric_std.all;
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architecture rtl of hu_dp is
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-- Memory
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subtype word is std_logic_vector(B-1 downto 0);
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type array_as_h_w is array (N_H_MAX-1 downto 0) of word;
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signal mem_hp : array_as_h_w; -- State (internal)
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signal mem_hw : array_as_h_w; -- Copy of w*h
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signal addr_wr, addr_nxt : std_logic_vector(ADDR_H_MAX-1 downto 0); -- Address
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-- Data path for hp (i.t. h un-normalized) and hw (hp*w)
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signal hp_new, hw_nxt : unsigned(2*B-1 downto 0);
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signal hp_new_rg, hp_p, h_eff : std_logic_vector(B-1 downto 0);
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signal hw_p : std_logic_vector(B-1 downto 0);
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-- Accumulators for normalization
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signal sum_hw, sum_hw_nxt : std_logic_vector(B-1 downto 0); -- Running sum hw
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signal sum_hw_p, sum_hw_p_nxt : std_logic_vector(B-1 downto 0); -- Saved sum hw of previous
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signal sum_hp, sum_hp_nxt : std_logic_vector(B-1 downto 0); -- Running sum hp
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signal sum_hp_p, sum_hp_p_nxt : std_logic_vector(B-1 downto 0); -- Saved sum hw of previous (normalization)
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-- Control signals
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signal ctr_sel_ini, ctr_sum_ini, ctr_update_sum, ctr_update_sum2 : std_logic;
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signal ctr_addr_rst, ctr_addr_inc, ctr_write_hw : std_logic;
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signal ctr_wr_hw, ctr_wr_hp : std_logic;
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begin -- architecture rtlf
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-- Get control signals
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ctr_sel_ini <= ctr_hu(0);
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ctr_sum_ini <= ctr_hu(1);
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ctr_update_sum <= ctr_hu(2);
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ctr_addr_rst <= ctr_hu(3);
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ctr_addr_inc <= ctr_hu(4);
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ctr_write_hw <= ctr_hu(5);
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ctr_wr_hw <= ctr_hu(6);
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ctr_wr_hp <= ctr_hu(6);
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ctr_update_sum2 <= ctr_hu(7);
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-- Main calculation
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hp_new <= unsigned(hp_p) * unsigned(sum_hw_p) + unsigned(sum_hp_p) * unsigned(hw_p) ;
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-- Mux to select first h or saved one
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h_eff <= hi when ctr_sel_ini='1' else hp_new_rg;
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-- Calculate hw
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hw_nxt <= unsigned(h_eff) * unsigned(wi) ;
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-- Output h (note latency of a complete group)
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ho <= h_eff;
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-- Accumulate hw and hp
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sum_hw_nxt <= std_logic_vector(hw_nxt(2*B-1 downto B)) when ctr_sum_ini='1' else std_logic_vector(unsigned(sum_hw) + hw_nxt(2*B-1 downto B));
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sum_hw_p_nxt <= (others=>'0') when ctr_update_sum='1' else
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sum_hw when ctr_update_sum2='1' else sum_hw_p;
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sum_hp_nxt <= h_eff when ctr_sum_ini='1' else std_logic_vector(unsigned(sum_hp) + unsigned(h_eff)); -- Accumulate h
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--sum_hp_p_nxt <= sum_hp_nxt * eps when ctr_update_sum='1' else sum_hp_p;
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sum_hp_p_nxt <= eps when ctr_update_sum='1' else
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std_logic_vector(hp_new(2*B-1 downto B)) when ctr_update_sum2='1' else sum_hp_p;
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-- Read from memory
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--hw_p <= mem_hw(to_integer(unsigned(addr_nxt)));
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hw_p <= mem_hw(to_integer(unsigned(addr_nxt)))
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when ctr_update_sum2='0' else sum_hp; -- Put sum_hp in mult
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hp_p <= mem_hp(to_integer(unsigned(addr_nxt)));
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-- Address calculation
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addr_nxt <= (others => '0') when ctr_addr_rst='1' else
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std_logic_vector(unsigned(addr_wr) + 1) when ctr_addr_inc='1' else addr_wr;
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loc_h <= addr_wr; -- Output for ctrl path
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-- Registers
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rg: process (clk, rstn) is
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begin -- process pipe1
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if rstn = '0' then
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hp_new_rg <= (others=>'0');
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sum_hw <= (others=>'0');
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sum_hw_p <= (others=>'0');
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sum_hp <= (others=>'0');
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sum_hp_p <= (others=>'0');
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addr_wr <= (others => '0');
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elsif clk'event and clk = '1' then
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hp_new_rg <= std_logic_vector(hp_new(2*B-1 downto B));
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sum_hw <= sum_hw_nxt;
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sum_hw_p <= sum_hw_p_nxt;
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sum_hp <= sum_hp_nxt;
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sum_hp_p <= sum_hp_p_nxt;
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addr_wr <= addr_nxt;
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end if;
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end process rg;
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-- Memory
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mem: process (clk) is
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begin -- process mem
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if clk'event and clk = '1' then -- rising clock edge
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if ctr_wr_hw='1' then
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mem_hw(to_integer(unsigned(addr_wr))) <= std_logic_vector(hw_nxt(2*B-1 downto B));
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end if;
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if ctr_wr_hp='1' then
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mem_hp(to_integer(unsigned(addr_wr))) <= h_eff;
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end if;
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end if;
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end process mem;
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end architecture rtl;
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