Project Settings
Project Name IGLOO_TOP_syn Implementation Name synthesis
Top Module work.IGLOO_TOP Retiming 0
Resource Sharing 1 Fanout Guide 24
Disable I/O Insertion 0 FSM Compiler 1

Run Status
Job Name Status CPU Time Real Time Memory Date/Time
Compile InputComplete 145 32 0 - 0m:03s - 9/2/2014
3:34:23 PM
Pre-mappingComplete 67 3 0 0m:00s 0m:00s 113MB 9/2/2014
3:34:27 PM
Map & OptimizeComplete 15 8 0 0m:23s 0m:24s 195MB 9/2/2014
3:34:52 PM

Area Summary
Core Cells 5274 IO Cells 38
Block RAMs (v_ram) 8

Timing Summary
Clock NameReq FreqEst FreqSlack
IGLOO_TOP|Clk24.0 MHz81.3 MHz29.371
IMPLANT_TOP|Clk_inferred_clock100.0 MHz15.2 MHz-27.896
IMPLANT_TOP|Clock_4MHz_inferred_clock100.0 MHz36.0 MHz-17.743

Optimizations Summary
Combined Clock Conversion 1 / 2