Project Settings |
---|
Project Name | IGLOO_TOP_syn | Implementation Name | synthesis |
Top Module | work.IGLOO_TOP | Retiming | 0 |
Resource Sharing | 1 | Fanout Guide | 24 |
Disable I/O Insertion | 0 | FSM Compiler | 1 |
Run Status |
Job Name |
Status |
|
|
|
CPU Time |
Real Time |
Memory |
Date/Time |
Compile Input | Complete |
116 |
45 |
0 |
- |
0m:01s |
- |
9/5/2014 5:35:14 PM |
Pre-mapping | Complete |
37 |
3 |
0 |
0m:00s |
0m:00s |
114MB |
9/5/2014 5:35:15 PM |
Map & Optimize | Complete |
55 |
41 |
0 |
0m:15s |
0m:15s |
216MB |
9/5/2014 5:35:31 PM |
Area Summary |
|
Core Cells | 5973 |
IO Cells | 38 |
Block RAMs
(v_ram) | 8 |
| |
Timing Summary |
|
Clock Name | Req Freq | Est Freq | Slack |
COMMAND_RECEIVER|Clk_4MHz_inferred_clock | 100.0 MHz | 34.3 MHz | -19.175 |
IGLOO_TOP|Clk | 24.0 MHz | 81.8 MHz | 29.438 |
IMPLANT_TOP|Clk_inferred_clock | 100.0 MHz | 26.0 MHz | -28.531 |
Optimizations Summary |
Combined Clock Conversion | 1 / 3 |
| |
|