Example2 Project Status (04/10/2017 - 12:27:08) | |||
Project File: | Example2.xise | Parser Errors: | No Errors |
Module Name: | Example2 | Implementation State: | Programming File Generated |
Target Device: | xc3s1400a-5ft256 |
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No Errors |
Product Version: | ISE 14.7 |
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259 Warnings (44 new) |
Design Goal: | Balanced |
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All Signals Completely Routed |
Design Strategy: | Xilinx Default (unlocked) |
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All Constraints Met |
Environment: | System Settings |
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0 (Timing Report) |
Device Utilization Summary | [-] | ||||
Logic Utilization | Used | Available | Utilization | Note(s) | |
Number of Slice Flip Flops | 818 | 22,528 | 3% | ||
Number of 4 input LUTs | 704 | 22,528 | 3% | ||
Number of occupied Slices | 710 | 11,264 | 6% | ||
Number of Slices containing only related logic | 710 | 710 | 100% | ||
Number of Slices containing unrelated logic | 0 | 710 | 0% | ||
Total Number of 4 input LUTs | 885 | 22,528 | 3% | ||
Number used as logic | 686 | ||||
Number used as a route-thru | 181 | ||||
Number used as Shift registers | 18 | ||||
Number of bonded IOBs | 62 | 161 | 38% | ||
IOB Flip Flops | 7 | ||||
Number of ODDR2s used | 41 | ||||
Number of BUFGMUXs | 5 | 24 | 20% | ||
Number of DCMs | 3 | 8 | 37% | ||
Number of RAMB16BWEs | 19 | 32 | 59% | ||
Average Fanout of Non-Clock Nets | 3.38 |
Performance Summary | [-] | |||
Final Timing Score: | 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) | Pinout Data: | Pinout Report | |
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report | |
Timing Constraints: | All Constraints Met |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | Mon Apr 10 12:26:15 2017 | 0 | 202 Warnings (44 new) | 74 Infos (34 new) | |
Translation Report | Current | Mon Apr 10 12:26:21 2017 | 0 | 0 | 4 Infos (0 new) | |
Map Report | Current | Mon Apr 10 12:26:33 2017 | 0 | 21 Warnings (0 new) | 8 Infos (0 new) | |
Place and Route Report | Current | Mon Apr 10 12:26:54 2017 | 0 | 16 Warnings (0 new) | 0 | |
Power Report | ||||||
Post-PAR Static Timing Report | Current | Mon Apr 10 12:26:57 2017 | 0 | 0 | 5 Infos (0 new) | |
Bitgen Report | Current | Mon Apr 10 12:27:07 2017 | 0 | 20 Warnings (0 new) | 2 Infos (0 new) |
Secondary Reports | [-] | ||
Report Name | Status | Generated | |
ISIM Simulator Log | Out of Date | Mon Apr 10 12:18:28 2017 | |
WebTalk Report | Current | Mon Apr 10 12:27:08 2017 | |
WebTalk Log File | Current | Mon Apr 10 12:27:08 2017 |