Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 

 
Software Version and Target Device
Product Version: ISE:14.7 (WebPack) - P.20131013 Target Family: Spartan3A and Spartan3AN
OS Platform: LIN64 Target Device: xc3s1400a
Project ID (random number) ca8cc2ce14b547069b5111885f1219e4.D24C5DF373DB0FA863A8D90E322791B9.61 Target Package: ft256
Registration ID 177307502_0_0_353 Target Speed: -5
Date Generated 2017-04-10T12:27:08 Tool Flow ISE
 
User Environment
OS Name Scientific OS Release Scientific Linux release 7.3 (Nitrogen)
CPU Name Intel(R) Core(TM) i7 CPU 960 @ 3.20GHz CPU Speed 3207.340 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Adders/Subtractors=4
  • 16-bit adder=2
  • 16-bit addsub=1
  • 4-bit subtractor=1
Comparators=6
  • 16-bit comparator greatequal=2
  • 16-bit comparator less=3
  • 6-bit comparator not equal=1
Counters=8
  • 16-bit up counter=2
  • 17-bit up counter=1
  • 24-bit up counter=1
  • 32-bit up counter=2
  • 4-bit down counter=1
  • 4-bit up counter=1
FSMs=3 Registers=251
  • Flip-Flops=251
MiscellaneousStatistics
  • AGG_BONDED_IO=62
  • AGG_IO=62
  • AGG_SLICE=710
  • NUM_4_INPUT_LUT=885
  • NUM_BONDED_IBUF=19
  • NUM_BONDED_IOB=43
  • NUM_BUFGMUX=5
  • NUM_CYMUX=353
  • NUM_DCM=3
  • NUM_IOB_FF=7
  • NUM_LUT_RT=181
  • NUM_ODDR2_NONE=41
  • NUM_RAMB16BWE=19
  • NUM_SHIFT=18
  • NUM_SLICEL=693
  • NUM_SLICEM=17
  • NUM_SLICE_FF=818
  • NUM_XOR=232
  • Xilinx Core fifo_generator_v9_3, Xilinx CORE Generator 14.7=2
NetStatistics
  • NumNets_Active=1493
  • NumNets_Gnd=1
  • NumNets_Vcc=1
  • NumNodesOfType_Active_BRAMADDR=468
  • NumNodesOfType_Active_BRAMDUMMY=322
  • NumNodesOfType_Active_CLKPIN=650
  • NumNodesOfType_Active_CNTRLPIN=758
  • NumNodesOfType_Active_DOUBLE=4536
  • NumNodesOfType_Active_DUMMY=2348
  • NumNodesOfType_Active_DUMMYBANK=344
  • NumNodesOfType_Active_DUMMYESC=20
  • NumNodesOfType_Active_GLOBAL=240
  • NumNodesOfType_Active_HFULLHEX=70
  • NumNodesOfType_Active_HLONG=22
  • NumNodesOfType_Active_HUNIHEX=404
  • NumNodesOfType_Active_INPUT=3659
  • NumNodesOfType_Active_IOBOUTPUT=24
  • NumNodesOfType_Active_OMUX=1538
  • NumNodesOfType_Active_OUTPUT=1407
  • NumNodesOfType_Active_PREBXBY=956
  • NumNodesOfType_Active_VFULLHEX=234
  • NumNodesOfType_Active_VLONG=73
  • NumNodesOfType_Active_VUNIHEX=512
  • NumNodesOfType_Vcc_CNTRLPIN=63
  • NumNodesOfType_Vcc_DUMMY=1
  • NumNodesOfType_Vcc_INPUT=27
  • NumNodesOfType_Vcc_PREBXBY=23
  • NumNodesOfType_Vcc_VCCOUT=51
SiteStatistics
  • IBUF-DIFFMTB=8
  • IBUF-DIFFSTB=9
  • IOB-DIFFMTB=22
  • IOB-DIFFSTB=21
  • SLICEL-SLICEM=297
SiteSummary
  • BUFGMUX=5
  • BUFGMUX_GCLKMUX=5
  • BUFGMUX_GCLK_BUFFER=5
  • DCM=3
  • DCM_DCM=3
  • IBUF=19
  • IBUF_DELAY_ADJ_BBOX=19
  • IBUF_IFF1=4
  • IBUF_INBUF=19
  • IBUF_PAD=19
  • IOB=43
  • IOB_DELAY_ADJ_BBOX=16
  • IOB_INBUF=16
  • IOB_OFF1=28
  • IOB_OFF2=25
  • IOB_OFFDDRBLACKBOX=25
  • IOB_OUTBUF=43
  • IOB_PAD=43
  • IOB_TFF1=16
  • IOB_TFF2=16
  • IOB_TFFDDRBLACKBOX=16
  • RAMB16BWE=19
  • RAMB16BWE_RAMB16BWE=19
  • SLICEL=693
  • SLICEL_C1VDD=12
  • SLICEL_C2VDD=7
  • SLICEL_CYMUXF=186
  • SLICEL_CYMUXG=167
  • SLICEL_F=385
  • SLICEL_F5MUX=40
  • SLICEL_F6MUX=9
  • SLICEL_FFX=311
  • SLICEL_FFY=489
  • SLICEL_G=479
  • SLICEL_GNDF=145
  • SLICEL_GNDG=133
  • SLICEL_XORF=116
  • SLICEL_XORG=116
  • SLICEM=17
  • SLICEM_F=4
  • SLICEM_FFX=1
  • SLICEM_FFY=17
  • SLICEM_G=17
  • SLICEM_WSGEN=17
 
Configuration Data
BUFGMUX
  • S=[S_INV:5] [S:0]
BUFGMUX_GCLKMUX
  • DISABLE_ATTR=[LOW:5]
  • S=[S_INV:5] [S:0]
DCM
  • PSCLK=[PSCLK_INV:0] [PSCLK:3]
  • PSEN=[PSEN_INV:0] [PSEN:3]
  • PSINCDEC=[PSINCDEC:3] [PSINCDEC_INV:0]
  • RST=[RST:2] [RST_INV:1]
DCM_DCM
  • CLKDV_DIVIDE=[2:3]
  • CLKOUT_PHASE_SHIFT=[NONE:3]
  • CLK_FEEDBACK=[1X:3]
  • DESKEW_ADJUST=[6:3]
  • DFS_FREQUENCY_MODE=[LOW:3]
  • DLL_FREQUENCY_MODE=[LOW:3]
  • DUTY_CYCLE_CORRECTION=[TRUE:3]
  • FACTORY_JF1=[0XC0:3]
  • FACTORY_JF2=[0X80:3]
  • PSCLK=[PSCLK_INV:0] [PSCLK:3]
  • PSEN=[PSEN_INV:0] [PSEN:3]
  • PSINCDEC=[PSINCDEC:3] [PSINCDEC_INV:0]
  • RST=[RST:2] [RST_INV:1]
IBUF
  • ICLK1=[ICLK1_INV:0] [ICLK1:4]
  • SR=[SR:4] [SR_INV:0]
IBUF_DELAY_ADJ_BBOX
  • DELAY_ADJ_ATTRBOX=[FIXED:19]
  • IBUF_DELAY_VALUE=[DLY0:19]
  • IFD_DELAY_VALUE=[DLY0:15] [DLY5:4]
  • SEL_IN=[SEL_IN:19] [SEL_IN_INV:0]
IBUF_IFF1
  • CK=[CK:4] [CK_INV:0]
  • IFF1_INIT_ATTR=[INIT0:4]
  • IFF1_SR_ATTR=[SRLOW:4]
  • IFFATTRBOX=[ASYNC:4]
  • LATCH_OR_FF=[FF:4]
  • SR=[SR:4] [SR_INV:0]
IBUF_PAD
  • IOATTRBOX=[LVCMOS25:3] [LVCMOS33:16]
  • PULL=[PULLDOWN:8]
IOB
  • O1=[O1_INV:1] [O1:42]
  • O2=[O2:25] [O2_INV:0]
  • OCE=[OCE:25] [OCE_INV:0]
  • OTCLK1=[OTCLK1_INV:0] [OTCLK1:28]
  • OTCLK2=[OTCLK2_INV:25] [OTCLK2:0]
  • SR=[SR:3] [SR_INV:0]
  • T1=[T1_INV:0] [T1:16]
  • T2=[T2:16] [T2_INV:0]
  • TCE=[TCE_INV:0] [TCE:16]
IOB_DELAY_ADJ_BBOX
  • DELAY_ADJ_ATTRBOX=[FIXED:16]
  • IBUF_DELAY_VALUE=[DLY0:16]
  • IFD_DELAY_VALUE=[DLY0:16]
  • SEL_IN=[SEL_IN:16] [SEL_IN_INV:0]
IOB_OFF1
  • CE=[CE:25] [CE_INV:0]
  • CK=[CK:28] [CK_INV:0]
  • D=[D:27] [D_INV:1]
  • LATCH_OR_FF=[FF:28]
  • OFF1_INIT_ATTR=[INIT0:27] [INIT1:1]
  • OFF1_SR_ATTR=[SRLOW:2] [SRHIGH:1]
  • OFFATTRBOX=[ASYNC:3]
  • SR=[SR:3] [SR_INV:0]
IOB_OFF2
  • CE=[CE:25] [CE_INV:0]
  • CK=[CK:0] [CK_INV:25]
  • D=[D:25] [D_INV:0]
  • LATCH_OR_FF=[FF:25]
  • OFF2_INIT_ATTR=[INIT0:25]
IOB_OUTBUF
  • IN=[IN_INV:0] [IN:43]
  • SUSPEND=[3STATE:43]
  • TRI=[TRI_INV:0] [TRI:16]
IOB_PAD
  • DRIVEATTRBOX=[4:2] [6:26] [8:12] [12:3]
  • IOATTRBOX=[LVCMOS25:29] [LVCMOS33:14]
  • PULL=[PULLDOWN:1]
  • SLEW=[FAST:43]
IOB_TFF1
  • CE=[CE:16] [CE_INV:0]
  • CK=[CK:16] [CK_INV:0]
  • D=[D:16] [D_INV:0]
  • LATCH_OR_FF=[FF:16]
  • TFF1_INIT_ATTR=[INIT0:16]
IOB_TFF2
  • CE=[CE:16] [CE_INV:0]
  • CK=[CK:0] [CK_INV:16]
  • D=[D:16] [D_INV:0]
  • LATCH_OR_FF=[FF:16]
  • TFF2_INIT_ATTR=[INIT0:16]
RAMB16BWE
  • CLKA=[CLKA_INV:0] [CLKA:19]
  • CLKB=[CLKB_INV:0] [CLKB:19]
  • ENA=[ENA_INV:0] [ENA:19]
  • ENB=[ENB_INV:0] [ENB:19]
  • SSRA=[SSRA_INV:0] [SSRA:19]
  • SSRB=[SSRB_INV:0] [SSRB:19]
  • WEA0=[WEA0:19] [WEA0_INV:0]
  • WEA1=[WEA1:19] [WEA1_INV:0]
  • WEA2=[WEA2:19] [WEA2_INV:0]
  • WEA3=[WEA3_INV:0] [WEA3:19]
  • WEB0=[WEB0:19] [WEB0_INV:0]
  • WEB1=[WEB1:19] [WEB1_INV:0]
  • WEB2=[WEB2_INV:0] [WEB2:19]
  • WEB3=[WEB3:19] [WEB3_INV:0]
RAMB16BWE_RAMB16BWE
  • CLKA=[CLKA_INV:0] [CLKA:19]
  • CLKB=[CLKB_INV:0] [CLKB:19]
  • DATA_WIDTH_A=[1:7] [4:4] [9:8]
  • DATA_WIDTH_B=[1:7] [4:4] [9:8]
  • ENA=[ENA_INV:0] [ENA:19]
  • ENB=[ENB_INV:0] [ENB:19]
  • SSRA=[SSRA_INV:0] [SSRA:19]
  • SSRB=[SSRB_INV:0] [SSRB:19]
  • WEA0=[WEA0:19] [WEA0_INV:0]
  • WEA1=[WEA1:19] [WEA1_INV:0]
  • WEA2=[WEA2:19] [WEA2_INV:0]
  • WEA3=[WEA3_INV:0] [WEA3:19]
  • WEB0=[WEB0:19] [WEB0_INV:0]
  • WEB1=[WEB1:19] [WEB1_INV:0]
  • WEB2=[WEB2_INV:0] [WEB2:19]
  • WEB3=[WEB3:19] [WEB3_INV:0]
  • WRITE_MODE_A=[NO_CHANGE:19]
  • WRITE_MODE_B=[NO_CHANGE:19]
SLICEL
  • BX=[BX_INV:2] [BX:192]
  • BY=[BY:260] [BY_INV:3]
  • CE=[CE:204] [CE_INV:16]
  • CIN=[CIN_INV:0] [CIN:156]
  • CLK=[CLK:521] [CLK_INV:11]
  • SR=[SR:495] [SR_INV:1]
SLICEL_CYMUXF
  • 0=[0:186] [0_INV:0]
  • 1=[1_INV:2] [1:184]
SLICEL_CYMUXG
  • 0=[0:167] [0_INV:0]
SLICEL_F5MUX
  • S0=[S0:40] [S0_INV:0]
SLICEL_F6MUX
  • S0=[S0:9] [S0_INV:0]
SLICEL_FFX
  • CE=[CE:136] [CE_INV:16]
  • CK=[CK:306] [CK_INV:5]
  • D=[D:311] [D_INV:0]
  • FFX_INIT_ATTR=[INIT0:294] [INIT1:17]
  • FFX_SR_ATTR=[SRLOW:293] [SRHIGH:18]
  • LATCH_OR_FF=[FF:311]
  • SR=[SR:295] [SR_INV:0]
  • SYNC_ATTR=[ASYNC:300] [SYNC:11]
SLICEL_FFY
  • CE=[CE:202] [CE_INV:16]
  • CK=[CK:478] [CK_INV:11]
  • D=[D:486] [D_INV:3]
  • FFY_INIT_ATTR=[INIT0:448] [INIT1:41]
  • FFY_SR_ATTR=[SRLOW:448] [SRHIGH:41]
  • LATCH_OR_FF=[FF:489]
  • SR=[SR:452] [SR_INV:1]
  • SYNC_ATTR=[ASYNC:450] [SYNC:39]
SLICEL_XORF
  • 1=[1_INV:2] [1:114]
SLICEM
  • BX=[BX_INV:0] [BX:1]
  • BY=[BY:17] [BY_INV:0]
  • CLK=[CLK:17] [CLK_INV:0]
  • SR=[SR:17] [SR_INV:0]
SLICEM_F
  • DI=[DI:1] [DI_INV:0]
  • F_ATTR=[SHIFT_REG:1]
  • LUT_OR_MEM=[LUT:3] [RAM:1]
SLICEM_FFX
  • CK=[CK:1] [CK_INV:0]
  • D=[D:1] [D_INV:0]
  • FFX_INIT_ATTR=[INIT0:1]
  • FFX_SR_ATTR=[SRLOW:1]
  • LATCH_OR_FF=[FF:1]
  • SYNC_ATTR=[ASYNC:1]
SLICEM_FFY
  • CK=[CK:17] [CK_INV:0]
  • D=[D:17] [D_INV:0]
  • FFY_INIT_ATTR=[INIT0:17]
  • FFY_SR_ATTR=[SRLOW:17]
  • LATCH_OR_FF=[FF:17]
  • SYNC_ATTR=[ASYNC:17]
SLICEM_G
  • DI=[DI:17] [DI_INV:0]
  • G_ATTR=[SHIFT_REG:17]
  • LUT_OR_MEM=[RAM:17]
SLICEM_WSGEN
  • CK=[CK:17] [CK_INV:0]
  • SYNC_ATTR=[ASYNC:17]
  • WE=[WE_INV:0] [WE:17]
 
Pin Data
BUFGMUX
  • I0=5
  • O=5
  • S=5
BUFGMUX_GCLKMUX
  • I0=5
  • OUT=5
  • S=5
BUFGMUX_GCLK_BUFFER
  • IN=5
  • OUT=5
DCM
  • CLK0=3
  • CLKFB=3
  • CLKFX=2
  • CLKIN=3
  • LOCKED=3
  • PSCLK=3
  • PSEN=3
  • PSINCDEC=3
  • RST=3
  • STATUS2=2
DCM_DCM
  • CLK0=3
  • CLKFB=3
  • CLKFX=2
  • CLKIN=3
  • LOCKED=3
  • PSCLK=3
  • PSEN=3
  • PSINCDEC=3
  • RST=3
  • STATUS2=2
IBUF
  • I=15
  • ICLK1=4
  • IQ1=4
  • PAD=19
  • SR=4
IBUF_DELAY_ADJ_BBOX
  • IBUF_OUT=15
  • IFD_OUT=4
  • SEL_IN=19
IBUF_IFF1
  • CK=4
  • D=4
  • Q=4
  • SR=4
IBUF_INBUF
  • IN=19
  • OUT=19
IBUF_PAD
  • PAD=19
IOB
  • I=16
  • O1=43
  • O2=25
  • OCE=25
  • OTCLK1=28
  • OTCLK2=25
  • PAD=43
  • SR=3
  • T1=16
  • T2=16
  • TCE=16
IOB_DELAY_ADJ_BBOX
  • IBUF_OUT=16
  • SEL_IN=16
IOB_INBUF
  • IN=16
  • OUT=16
IOB_OFF1
  • CE=25
  • CK=28
  • D=28
  • Q=28
  • SR=3
IOB_OFF2
  • CE=25
  • CK=25
  • D=25
  • Q=25
IOB_OFFDDRBLACKBOX
  • OFF1=25
  • OFF2=25
  • OFFDDR=25
IOB_OUTBUF
  • IN=43
  • OUT=43
  • TRI=16
IOB_PAD
  • PAD=43
IOB_TFF1
  • CE=16
  • CK=16
  • D=16
  • Q=16
IOB_TFF2
  • CE=16
  • CK=16
  • D=16
  • Q=16
IOB_TFFDDRBLACKBOX
  • TFF1=16
  • TFF2=16
  • TFFDDR=16
RAMB16BWE
  • ADDRA0=7
  • ADDRA1=7
  • ADDRA10=19
  • ADDRA11=19
  • ADDRA12=19
  • ADDRA13=19
  • ADDRA2=11
  • ADDRA3=19
  • ADDRA4=19
  • ADDRA5=19
  • ADDRA6=19
  • ADDRA7=19
  • ADDRA8=19
  • ADDRA9=19
  • ADDRB0=7
  • ADDRB1=7
  • ADDRB10=19
  • ADDRB11=19
  • ADDRB12=19
  • ADDRB13=19
  • ADDRB2=11
  • ADDRB3=19
  • ADDRB4=19
  • ADDRB5=19
  • ADDRB6=19
  • ADDRB7=19
  • ADDRB8=19
  • ADDRB9=19
  • CLKA=19
  • CLKB=19
  • DIA0=19
  • DIA1=12
  • DIA2=12
  • DIA3=12
  • DIA4=8
  • DIA5=8
  • DIA6=8
  • DIA7=8
  • DIPA0=8
  • DOB0=19
  • DOB1=12
  • DOB2=12
  • DOB3=12
  • DOB4=8
  • DOB5=8
  • DOB6=8
  • DOB7=8
  • DOPB0=8
  • ENA=19
  • ENB=19
  • SSRA=19
  • SSRB=19
  • WEA0=19
  • WEA1=19
  • WEA2=19
  • WEA3=19
  • WEB0=19
  • WEB1=19
  • WEB2=19
  • WEB3=19
RAMB16BWE_RAMB16BWE
  • ADDRA0=7
  • ADDRA1=7
  • ADDRA10=19
  • ADDRA11=19
  • ADDRA12=19
  • ADDRA13=19
  • ADDRA2=11
  • ADDRA3=19
  • ADDRA4=19
  • ADDRA5=19
  • ADDRA6=19
  • ADDRA7=19
  • ADDRA8=19
  • ADDRA9=19
  • ADDRB0=7
  • ADDRB1=7
  • ADDRB10=19
  • ADDRB11=19
  • ADDRB12=19
  • ADDRB13=19
  • ADDRB2=11
  • ADDRB3=19
  • ADDRB4=19
  • ADDRB5=19
  • ADDRB6=19
  • ADDRB7=19
  • ADDRB8=19
  • ADDRB9=19
  • CLKA=19
  • CLKB=19
  • DIA0=19
  • DIA1=12
  • DIA2=12
  • DIA3=12
  • DIA4=8
  • DIA5=8
  • DIA6=8
  • DIA7=8
  • DIPA0=8
  • DOB0=19
  • DOB1=12
  • DOB2=12
  • DOB3=12
  • DOB4=8
  • DOB5=8
  • DOB6=8
  • DOB7=8
  • DOPB0=8
  • ENA=19
  • ENB=19
  • SSRA=19
  • SSRB=19
  • WEA0=19
  • WEA1=19
  • WEA2=19
  • WEA3=19
  • WEB0=19
  • WEB1=19
  • WEB2=19
  • WEB3=19
SLICEL
  • BX=194
  • BY=263
  • CE=220
  • CIN=156
  • CLK=532
  • COUT=167
  • F1=384
  • F2=286
  • F3=199
  • F4=162
  • F5=18
  • FXINA=9
  • FXINB=9
  • G1=478
  • G2=379
  • G3=235
  • G4=170
  • SR=496
  • X=114
  • XB=7
  • XQ=311
  • Y=159
  • YQ=489
SLICEL_C1VDD
  • 1=12
SLICEL_C2VDD
  • 1=7
SLICEL_CYMUXF
  • 0=186
  • 1=186
  • OUT=186
  • S0=186
SLICEL_CYMUXG
  • 0=167
  • 1=167
  • OUT=167
  • S0=167
SLICEL_F
  • A1=378
  • A2=286
  • A3=199
  • A4=162
  • D=385
SLICEL_F5MUX
  • F=40
  • G=40
  • OUT=40
  • S0=40
SLICEL_F6MUX
  • 0=9
  • 1=9
  • OUT=9
  • S0=9
SLICEL_FFX
  • CE=152
  • CK=311
  • D=311
  • Q=311
  • SR=295
SLICEL_FFY
  • CE=218
  • CK=489
  • D=489
  • Q=489
  • SR=453
SLICEL_G
  • A1=472
  • A2=379
  • A3=235
  • A4=170
  • D=479
SLICEL_GNDF
  • 0=145
SLICEL_GNDG
  • 0=133
SLICEL_XORF
  • 0=116
  • 1=116
  • O=116
SLICEL_XORG
  • 0=116
  • 1=116
  • O=116
SLICEM
  • BX=1
  • BY=17
  • CLK=17
  • F1=4
  • F2=4
  • F3=3
  • F4=1
  • G1=17
  • G2=17
  • G3=17
  • G4=17
  • SR=17
  • X=3
  • XQ=1
  • YQ=17
SLICEM_F
  • A1=4
  • A2=4
  • A3=3
  • A4=1
  • D=4
  • DI=1
  • WS=1
SLICEM_FFX
  • CK=1
  • D=1
  • Q=1
SLICEM_FFY
  • CK=17
  • D=17
  • Q=17
SLICEM_G
  • A1=17
  • A2=17
  • A3=17
  • A4=17
  • D=17
  • DI=17
  • WS=17
SLICEM_WSGEN
  • CK=17
  • WE=17
  • WSF=1
  • WSG=17
 
Tool Usage
Command Line History
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -sd <dname> -aul -aut -nt timestamp -uc <fname>.ucf -p xc3s1400a-ft256-5 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s1400a-ft256-5 -timing -logic_opt on -ol std -t 1 -register_duplication off -cm speed -ir off -ignore_keep_hierarchy -pr off -ntd -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • map -intstyle ise -p xc3s1400a-ft256-5 -timing -logic_opt on -ol std -t 1 -register_duplication off -cm speed -ir off -ignore_keep_hierarchy -pr off -ntd -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • map -intstyle ise -p xc3s1400a-ft256-5 -timing -logic_opt on -ol std -t 1 -register_duplication off -cm speed -ir off -ignore_keep_hierarchy -pr off -ntd -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -pl high -rl high -xe n -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -sd <dname> -aul -aut -nt timestamp -uc <fname>.ucf -p xc3s1400a-ft256-5 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s1400a-ft256-5 -timing -logic_opt on -ol std -t 1 -register_duplication off -cm speed -ir off -ignore_keep_hierarchy -pr off -ntd -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -pl high -rl high -xe n -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -sd <dname> -aul -aut -nt timestamp -uc <fname>.ucf -p xc3s1400a-ft256-5 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s1400a-ft256-5 -timing -logic_opt on -ol std -t 1 -register_duplication off -cm speed -ir off -ignore_keep_hierarchy -pr off -ntd -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -pl high -rl high -xe n -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -sd <dname> -aul -aut -nt timestamp -uc <fname>.ucf -p xc3s1400a-ft256-5 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s1400a-ft256-5 -timing -logic_opt on -ol std -t 1 -register_duplication off -cm speed -ir off -ignore_keep_hierarchy -pr off -ntd -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -pl high -rl high -xe n -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -sd <dname> -aul -aut -nt timestamp -uc <fname>.ucf -p xc3s1400a-ft256-5 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s1400a-ft256-5 -timing -logic_opt on -ol std -t 1 -register_duplication off -cm speed -ir off -ignore_keep_hierarchy -pr off -ntd -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -pl high -rl high -xe n -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
 
Software Quality
Run Statistics
Program NameRuns StartedRuns FinishedErrorsFatal ErrorsInternal ErrorsExceptionsCore Dumps
arwz 1 1 0 0 0 0 0
bitgen 62 62 0 0 0 0 0
map 78 62 0 0 0 0 0
ngcbuild 3 3 0 0 0 0 0
ngdbuild 69 68 0 0 0 0 0
par 62 62 0 0 0 0 0
trce 62 62 0 0 0 0 0
xawinfo 1 1 0 0 0 0 0
xst 72 72 0 0 0 0 0
 
Project Statistics
PROP_Enable_Message_Filtering=false PROP_FitterReportFormat=HTML
PROP_ISimsUseCustomWaveConfigFile_behav=true PROP_LastAppliedGoal=Balanced
PROP_LastAppliedStrategy=Xilinx Default (unlocked) PROP_ManualCompileOrderImp=false
PROP_PropSpecInProjFile=Store all values PROP_SelectedInstanceHierarchicalPath=/Testgenerator16Bit_UUT
PROP_Simulator=ISim (VHDL/Verilog) PROP_SynthOptEffort=High
PROP_SynthTopFile=changed PROP_Top_Level_Module_Type=HDL
PROP_UseSmartGuide=false PROP_UserBrowsedStrategyFiles=/glocal/Xilinx/13.1/ISE_DS/ISE/data/default.xds
PROP_UserConstraintEditorPreference=Text Editor PROP_intProjectCreationTimestamp=2010-11-16T10:58:27
PROP_intWbtProjectID=D24C5DF373DB0FA863A8D90E322791B9 PROP_intWbtProjectIteration=61
PROP_intWorkingDirLocWRTProjDir=Same PROP_intWorkingDirUsed=No
PROP_lockPinsUcfFile=changed PROP_mapIgnoreTimingConstraints=true
PROP_selectedSimRootSourceNode_behav=work.Testgenerator16Bit_UUT PROP_xilxBitgStart_Clk_DriveDone=true
PROP_xilxMapAllowLogicOpt=true PROP_xilxMapCoverMode=Speed
PROP_xilxMapTimingDrivenPacking=true PROP_xilxNgdbld_AUL=true
PROP_xilxNgdbld_AUT=true PROP_xilxPARplacerEffortLevel=High
PROP_xilxPARrouterEffortLevel=High PROP_AutoTop=false
PROP_DevFamily=Spartan3A and Spartan3AN PROP_ISimsUseCustomWaveConfigFilename_behav=changed
PROP_MapEffortLevel=Standard PROP_MapLogicOptimization=true
PROP_xilxBitgCfg_MultiBootUseNewMode=false PROP_CompxlibSimPath=changed
PROP_DevDevice=xc3s1400a PROP_DevFamilyPMName=spartan3a
PROP_xilxPARextraEffortLevel=Normal PROP_DevPackage=ft256
PROP_Synthesis_Tool=XST (VHDL/Verilog) PROP_DevSpeed=-5
PROP_PreferredLanguage=VHDL FILE_COREGEN=2
FILE_UCF=1 FILE_VHDL=7
 
Core Statistics
Core Type=fifo_generator_v9_3
c_add_ngc_constraint=0 c_application_type_axis=0 c_application_type_rach=0 c_application_type_rdch=0
c_application_type_wach=0 c_application_type_wdch=0 c_application_type_wrch=0 c_axi_addr_width=32
c_axi_aruser_width=1 c_axi_awuser_width=1 c_axi_buser_width=1 c_axi_data_width=64
c_axi_id_width=4 c_axi_ruser_width=1 c_axi_type=0 c_axi_wuser_width=1
c_axis_tdata_width=64 c_axis_tdest_width=4 c_axis_tid_width=8 c_axis_tkeep_width=4
c_axis_tstrb_width=4 c_axis_tuser_width=4 c_axis_type=0 c_common_clock=0
c_count_type=0 c_data_count_width=14 c_default_value=BlankString c_din_width=16
c_din_width_axis=1 c_din_width_rach=32 c_din_width_rdch=64 c_din_width_wach=32
c_din_width_wdch=64 c_din_width_wrch=2 c_dout_rst_val=0 c_dout_width=16
c_enable_rlocs=0 c_enable_rst_sync=1 c_error_injection_type=0 c_error_injection_type_axis=0
c_error_injection_type_rach=0 c_error_injection_type_rdch=0 c_error_injection_type_wach=0 c_error_injection_type_wdch=0
c_error_injection_type_wrch=0 c_family=spartan3 c_full_flags_rst_val=1 c_has_almost_empty=1
c_has_almost_full=1 c_has_axi_aruser=0 c_has_axi_awuser=0 c_has_axi_buser=0
c_has_axi_rd_channel=0 c_has_axi_ruser=0 c_has_axi_wr_channel=0 c_has_axi_wuser=0
c_has_axis_tdata=0 c_has_axis_tdest=0 c_has_axis_tid=0 c_has_axis_tkeep=0
c_has_axis_tlast=0 c_has_axis_tready=1 c_has_axis_tstrb=0 c_has_axis_tuser=0
c_has_backup=0 c_has_data_count=0 c_has_data_counts_axis=0 c_has_data_counts_rach=0
c_has_data_counts_rdch=0 c_has_data_counts_wach=0 c_has_data_counts_wdch=0 c_has_data_counts_wrch=0
c_has_int_clk=0 c_has_master_ce=0 c_has_meminit_file=0 c_has_overflow=0
c_has_prog_flags_axis=0 c_has_prog_flags_rach=0 c_has_prog_flags_rdch=0 c_has_prog_flags_wach=0
c_has_prog_flags_wdch=0 c_has_prog_flags_wrch=0 c_has_rd_data_count=0 c_has_rd_rst=0
c_has_rst=1 c_has_slave_ce=0 c_has_srst=0 c_has_underflow=0
c_has_valid=1 c_has_wr_ack=0 c_has_wr_data_count=0 c_has_wr_rst=0
c_implementation_type=2 c_implementation_type_axis=1 c_implementation_type_rach=1 c_implementation_type_rdch=1
c_implementation_type_wach=1 c_implementation_type_wdch=1 c_implementation_type_wrch=1 c_init_wr_pntr_val=0
c_interface_type=0 c_memory_type=1 c_mif_file_name=BlankString c_msgon_val=1
c_optimization_mode=0 c_overflow_low=0 c_preload_latency=0 c_preload_regs=1
c_prim_fifo_type=8kx4 c_prog_empty_thresh_assert_val=4 c_prog_empty_thresh_assert_val_axis=1022 c_prog_empty_thresh_assert_val_rach=1022
c_prog_empty_thresh_assert_val_rdch=1022 c_prog_empty_thresh_assert_val_wach=1022 c_prog_empty_thresh_assert_val_wdch=1022 c_prog_empty_thresh_assert_val_wrch=1022
c_prog_empty_thresh_negate_val=5 c_prog_empty_type=0 c_prog_empty_type_axis=0 c_prog_empty_type_rach=0
c_prog_empty_type_rdch=0 c_prog_empty_type_wach=0 c_prog_empty_type_wdch=0 c_prog_empty_type_wrch=0
c_prog_full_thresh_assert_val=14000 c_prog_full_thresh_assert_val_axis=1023 c_prog_full_thresh_assert_val_rach=1023 c_prog_full_thresh_assert_val_rdch=1023
c_prog_full_thresh_assert_val_wach=1023 c_prog_full_thresh_assert_val_wdch=1023 c_prog_full_thresh_assert_val_wrch=1023 c_prog_full_thresh_negate_val=13999
c_prog_full_type=1 c_prog_full_type_axis=0 c_prog_full_type_rach=0 c_prog_full_type_rdch=0
c_prog_full_type_wach=0 c_prog_full_type_wdch=0 c_prog_full_type_wrch=0 c_rach_type=0
c_rd_data_count_width=14 c_rd_depth=16384 c_rd_freq=1 c_rd_pntr_width=14
c_rdch_type=0 c_reg_slice_mode_axis=0 c_reg_slice_mode_rach=0 c_reg_slice_mode_rdch=0
c_reg_slice_mode_wach=0 c_reg_slice_mode_wdch=0 c_reg_slice_mode_wrch=0 c_synchronizer_stage=2
c_underflow_low=0 c_use_common_overflow=0 c_use_common_underflow=0 c_use_default_settings=0
c_use_dout_rst=1 c_use_ecc=0 c_use_ecc_axis=0 c_use_ecc_rach=0
c_use_ecc_rdch=0 c_use_ecc_wach=0 c_use_ecc_wdch=0 c_use_ecc_wrch=0
c_use_embedded_reg=0 c_use_fifo16_flags=0 c_use_fwft_data_count=0 c_valid_low=0
c_wach_type=0 c_wdch_type=0 c_wr_ack_low=0 c_wr_data_count_width=14
c_wr_depth=16384 c_wr_depth_axis=1024 c_wr_depth_rach=16 c_wr_depth_rdch=1024
c_wr_depth_wach=16 c_wr_depth_wdch=1024 c_wr_depth_wrch=16 c_wr_freq=1
c_wr_pntr_width=14 c_wr_pntr_width_axis=10 c_wr_pntr_width_rach=4 c_wr_pntr_width_rdch=10
c_wr_pntr_width_wach=4 c_wr_pntr_width_wdch=10 c_wr_pntr_width_wrch=4 c_wr_response_latency=1
c_wrch_type=0
Core Type=fifo_generator_v9_3
c_add_ngc_constraint=0 c_application_type_axis=0 c_application_type_rach=0 c_application_type_rdch=0
c_application_type_wach=0 c_application_type_wdch=0 c_application_type_wrch=0 c_axi_addr_width=32
c_axi_aruser_width=1 c_axi_awuser_width=1 c_axi_buser_width=1 c_axi_data_width=64
c_axi_id_width=4 c_axi_ruser_width=1 c_axi_type=0 c_axi_wuser_width=1
c_axis_tdata_width=64 c_axis_tdest_width=4 c_axis_tid_width=8 c_axis_tkeep_width=4
c_axis_tstrb_width=4 c_axis_tuser_width=4 c_axis_type=0 c_common_clock=0
c_count_type=0 c_data_count_width=12 c_default_value=BlankString c_din_width=16
c_din_width_axis=1 c_din_width_rach=32 c_din_width_rdch=64 c_din_width_wach=32
c_din_width_wdch=64 c_din_width_wrch=2 c_dout_rst_val=0 c_dout_width=16
c_enable_rlocs=0 c_enable_rst_sync=1 c_error_injection_type=0 c_error_injection_type_axis=0
c_error_injection_type_rach=0 c_error_injection_type_rdch=0 c_error_injection_type_wach=0 c_error_injection_type_wdch=0
c_error_injection_type_wrch=0 c_family=spartan3 c_full_flags_rst_val=1 c_has_almost_empty=1
c_has_almost_full=1 c_has_axi_aruser=0 c_has_axi_awuser=0 c_has_axi_buser=0
c_has_axi_rd_channel=0 c_has_axi_ruser=0 c_has_axi_wr_channel=0 c_has_axi_wuser=0
c_has_axis_tdata=0 c_has_axis_tdest=0 c_has_axis_tid=0 c_has_axis_tkeep=0
c_has_axis_tlast=0 c_has_axis_tready=1 c_has_axis_tstrb=0 c_has_axis_tuser=0
c_has_backup=0 c_has_data_count=0 c_has_data_counts_axis=0 c_has_data_counts_rach=0
c_has_data_counts_rdch=0 c_has_data_counts_wach=0 c_has_data_counts_wdch=0 c_has_data_counts_wrch=0
c_has_int_clk=0 c_has_master_ce=0 c_has_meminit_file=0 c_has_overflow=0
c_has_prog_flags_axis=0 c_has_prog_flags_rach=0 c_has_prog_flags_rdch=0 c_has_prog_flags_wach=0
c_has_prog_flags_wdch=0 c_has_prog_flags_wrch=0 c_has_rd_data_count=0 c_has_rd_rst=0
c_has_rst=1 c_has_slave_ce=0 c_has_srst=0 c_has_underflow=0
c_has_valid=1 c_has_wr_ack=0 c_has_wr_data_count=0 c_has_wr_rst=0
c_implementation_type=2 c_implementation_type_axis=1 c_implementation_type_rach=1 c_implementation_type_rdch=1
c_implementation_type_wach=1 c_implementation_type_wdch=1 c_implementation_type_wrch=1 c_init_wr_pntr_val=0
c_interface_type=0 c_memory_type=1 c_mif_file_name=BlankString c_msgon_val=0
c_optimization_mode=0 c_overflow_low=0 c_preload_latency=0 c_preload_regs=1
c_prim_fifo_type=4kx9 c_prog_empty_thresh_assert_val=4 c_prog_empty_thresh_assert_val_axis=1022 c_prog_empty_thresh_assert_val_rach=1022
c_prog_empty_thresh_assert_val_rdch=1022 c_prog_empty_thresh_assert_val_wach=1022 c_prog_empty_thresh_assert_val_wdch=1022 c_prog_empty_thresh_assert_val_wrch=1022
c_prog_empty_thresh_negate_val=5 c_prog_empty_type=0 c_prog_empty_type_axis=0 c_prog_empty_type_rach=0
c_prog_empty_type_rdch=0 c_prog_empty_type_wach=0 c_prog_empty_type_wdch=0 c_prog_empty_type_wrch=0
c_prog_full_thresh_assert_val=3000 c_prog_full_thresh_assert_val_axis=1023 c_prog_full_thresh_assert_val_rach=1023 c_prog_full_thresh_assert_val_rdch=1023
c_prog_full_thresh_assert_val_wach=1023 c_prog_full_thresh_assert_val_wdch=1023 c_prog_full_thresh_assert_val_wrch=1023 c_prog_full_thresh_negate_val=2999
c_prog_full_type=1 c_prog_full_type_axis=0 c_prog_full_type_rach=0 c_prog_full_type_rdch=0
c_prog_full_type_wach=0 c_prog_full_type_wdch=0 c_prog_full_type_wrch=0 c_rach_type=0
c_rd_data_count_width=12 c_rd_depth=4096 c_rd_freq=1 c_rd_pntr_width=12
c_rdch_type=0 c_reg_slice_mode_axis=0 c_reg_slice_mode_rach=0 c_reg_slice_mode_rdch=0
c_reg_slice_mode_wach=0 c_reg_slice_mode_wdch=0 c_reg_slice_mode_wrch=0 c_synchronizer_stage=2
c_underflow_low=0 c_use_common_overflow=0 c_use_common_underflow=0 c_use_default_settings=0
c_use_dout_rst=1 c_use_ecc=0 c_use_ecc_axis=0 c_use_ecc_rach=0
c_use_ecc_rdch=0 c_use_ecc_wach=0 c_use_ecc_wdch=0 c_use_ecc_wrch=0
c_use_embedded_reg=0 c_use_fifo16_flags=0 c_use_fwft_data_count=0 c_valid_low=0
c_wach_type=0 c_wdch_type=0 c_wr_ack_low=0 c_wr_data_count_width=12
c_wr_depth=4096 c_wr_depth_axis=1024 c_wr_depth_rach=16 c_wr_depth_rdch=1024
c_wr_depth_wach=16 c_wr_depth_wdch=1024 c_wr_depth_wrch=16 c_wr_freq=1
c_wr_pntr_width=12 c_wr_pntr_width_axis=10 c_wr_pntr_width_rach=4 c_wr_pntr_width_rdch=10
c_wr_pntr_width_wach=4 c_wr_pntr_width_wdch=10 c_wr_pntr_width_wrch=4 c_wr_response_latency=1
c_wrch_type=0
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=6 NGDBUILD_NUM_DCM_SP=3 NGDBUILD_NUM_FD=50 NGDBUILD_NUM_FDC=356
NGDBUILD_NUM_FDCE=315 NGDBUILD_NUM_FDE=3 NGDBUILD_NUM_FDP=35 NGDBUILD_NUM_FDPE=22
NGDBUILD_NUM_FDR=5 NGDBUILD_NUM_FDRE=32 NGDBUILD_NUM_FDS=13 NGDBUILD_NUM_FD_1=16
NGDBUILD_NUM_GND=3 NGDBUILD_NUM_IBUF=7 NGDBUILD_NUM_IBUFG=1 NGDBUILD_NUM_INV=29
NGDBUILD_NUM_IOBUF=16 NGDBUILD_NUM_LUT1=183 NGDBUILD_NUM_LUT2=220 NGDBUILD_NUM_LUT2_D=5
NGDBUILD_NUM_LUT2_L=6 NGDBUILD_NUM_LUT3=126 NGDBUILD_NUM_LUT3_D=5 NGDBUILD_NUM_LUT4=324
NGDBUILD_NUM_LUT4_D=12 NGDBUILD_NUM_LUT4_L=11 NGDBUILD_NUM_MUXCY=397 NGDBUILD_NUM_MUXF5=42
NGDBUILD_NUM_MUXF6=9 NGDBUILD_NUM_OBUF=27 NGDBUILD_NUM_ODDR2=41 NGDBUILD_NUM_RAMB16BWE=19
NGDBUILD_NUM_SRL16=18 NGDBUILD_NUM_VCC=3 NGDBUILD_NUM_XORCY=245
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=6 NGDBUILD_NUM_DCM_SP=3 NGDBUILD_NUM_FD=50 NGDBUILD_NUM_FDC=356
NGDBUILD_NUM_FDCE=315 NGDBUILD_NUM_FDE=3 NGDBUILD_NUM_FDP=35 NGDBUILD_NUM_FDPE=22
NGDBUILD_NUM_FDR=5 NGDBUILD_NUM_FDRE=32 NGDBUILD_NUM_FDS=13 NGDBUILD_NUM_FD_1=16
NGDBUILD_NUM_GND=3 NGDBUILD_NUM_IBUF=34 NGDBUILD_NUM_IBUFG=1 NGDBUILD_NUM_INV=29
NGDBUILD_NUM_LUT1=183 NGDBUILD_NUM_LUT2=220 NGDBUILD_NUM_LUT2_D=5 NGDBUILD_NUM_LUT2_L=6
NGDBUILD_NUM_LUT3=126 NGDBUILD_NUM_LUT3_D=5 NGDBUILD_NUM_LUT4=324 NGDBUILD_NUM_LUT4_D=12
NGDBUILD_NUM_LUT4_L=11 NGDBUILD_NUM_MUXCY=397 NGDBUILD_NUM_MUXF5=42 NGDBUILD_NUM_MUXF6=9
NGDBUILD_NUM_OBUF=27 NGDBUILD_NUM_OBUFT=16 NGDBUILD_NUM_ODDR2=41 NGDBUILD_NUM_PULLDOWN=9
NGDBUILD_NUM_RAMB16BWE=19 NGDBUILD_NUM_SRLC16E=18 NGDBUILD_NUM_TS_TIMESPEC=1 NGDBUILD_NUM_VCC=3
NGDBUILD_NUM_XORCY=245
 
XST Command Line Options
XST_OPTION_SUMMARY
-ifn=<fname>.prj -ifmt=mixed -ofn=<design_top> -ofmt=NGC
-p=xc3s1400a-5-ft256 -top=<design_top> -opt_mode=Speed -opt_level=2
-iuc=NO -keep_hierarchy=No -netlist_hierarchy=As_Optimized -rtlview=Yes
-glob_opt=AllClockNets -read_cores=YES -sd=<No customer specific name> -write_timing_constraints=NO
-cross_clock_analysis=NO -bus_delimiter=<> -slice_utilization_ratio=100 -bram_utilization_ratio=100
-verilog2001=YES -fsm_extract=YES -fsm_encoding=Auto -safe_implementation=No
-fsm_style=LUT -ram_extract=Yes -ram_style=Auto -rom_extract=Yes
-shreg_extract=YES -rom_style=Auto -auto_bram_packing=NO -resource_sharing=YES
-async_to_sync=NO -mult_style=Auto -iobuf=YES -max_fanout=500
-bufg=24 -register_duplication=YES -register_balancing=No -optimize_primitives=NO
-use_clock_enable=Yes -use_sync_set=Yes -use_sync_reset=Yes -iob=Auto
-equivalent_register_removal=YES -slice_utilization_ratio_maxmargin=5