#Build: Synplify Pro L-2016.09M-2, Build 065R, Nov 16 2016 #install: C:\Microsemi\Libero_SoC_v11.8\SynplifyPro #OS: Windows 8 6.2 #Hostname: AGPAWELZIK-PC # Fri Apr 07 12:05:03 2017 #Implementation: synthesis Synopsys HDL Compiler, version comp2016q3p1, Build 117R, built Nov 17 2016 @N: : | Running in 64-bit mode Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Synopsys VHDL Compiler, version comp2016q3p1, Build 127R, built Nov 24 2016 @N: : | Running in 64-bit mode Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. @N:CD720 : std.vhd(123) | Setting time resolution to ps @N: : IGLOO_TOP.vhd(15) | Top entity is set to IGLOO_TOP. File C:\Users\agpawelzik\Desktop\IGLOO_TestGen\smartgen\FIFO_DISASSEMBLE\FIFO_DISASSEMBLE.vhd changed - recompiling File C:\Microsemi\Libero_SoC_v11.8\SynplifyPro\lib\proasic\igloo.vhd changed - recompiling File C:\Users\agpawelzik\Desktop\IGLOO_TestGen\hdl\TestPackageGenerator.vhd changed - recompiling File C:\Users\agpawelzik\Desktop\IGLOO_TestGen\hdl\InputParser.vhd changed - recompiling File C:\Users\agpawelzik\Desktop\IGLOO_TestGen\hdl\HV2201.vhd changed - recompiling File C:\Users\agpawelzik\Desktop\IGLOO_TestGen\hdl\ShiftReg74AHC595.vhd changed - recompiling File C:\Users\agpawelzik\Desktop\IGLOO_TestGen\hdl\AD5360_Controlle.vhd changed - recompiling File C:\Users\agpawelzik\Desktop\IGLOO_TestGen\hdl\AD5360_TestProgrammer.vhd changed - recompiling File C:\Users\agpawelzik\Desktop\IGLOO_TestGen\hdl\PackageDisassembler.vhd changed - recompiling File C:\Users\agpawelzik\Desktop\IGLOO_TestGen\hdl\DACSwitchCore.vhd changed - recompiling File C:\Users\agpawelzik\Desktop\IGLOO_TestGen\hdl\SwitchControl.vhd changed - recompiling File C:\Users\agpawelzik\Desktop\IGLOO_TestGen\hdl\IGLOO_TOP.vhd changed - recompiling VHDL syntax check successful! Compiler output is up to date. No re-compile necessary @N:CD630 : IGLOO_TOP.vhd(15) | Synthesizing work.igloo_top.igloo_top_arch. @N:CD364 : IGLOO_TOP.vhd(184) | Removing redundant assignment. @N:CD630 : SwitchControl.vhd(6) | Synthesizing work.switchcontrol.behavioural. @N:CD364 : SwitchControl.vhd(84) | Removing redundant assignment. @N:CD364 : SwitchControl.vhd(85) | Removing redundant assignment. @N:CD364 : SwitchControl.vhd(86) | Removing redundant assignment. @N:CD364 : SwitchControl.vhd(87) | Removing redundant assignment. @N:CD364 : SwitchControl.vhd(88) | Removing redundant assignment. @N:CD364 : SwitchControl.vhd(132) | Removing redundant assignment. @N:CD364 : SwitchControl.vhd(133) | Removing redundant assignment. @N:CD364 : SwitchControl.vhd(277) | Removing redundant assignment. @N:CD364 : SwitchControl.vhd(278) | Removing redundant assignment. @N:CD364 : SwitchControl.vhd(279) | Removing redundant assignment. @N:CD364 : SwitchControl.vhd(280) | Removing redundant assignment. @N:CD364 : SwitchControl.vhd(281) | Removing redundant assignment. @N:CD364 : SwitchControl.vhd(282) | Removing redundant assignment. @N:CD364 : SwitchControl.vhd(283) | Removing redundant assignment. @N:CD364 : SwitchControl.vhd(284) | Removing redundant assignment. @N:CD630 : HV2201.vhd(5) | Synthesizing work.hv2201.behaviourals. @N:CD231 : HV2201.vhd(41) | Using onehot encoding for type state_type. For example, enumeration sm_reset is mapped to "10000000000000000000000". @N:CD364 : HV2201.vhd(112) | Removing redundant assignment. @N:CD364 : HV2201.vhd(113) | Removing redundant assignment. @N:CD364 : HV2201.vhd(114) | Removing redundant assignment. @N:CD364 : HV2201.vhd(115) | Removing redundant assignment. @N:CD364 : HV2201.vhd(116) | Removing redundant assignment. @N:CD364 : HV2201.vhd(117) | Removing redundant assignment. @N:CD364 : HV2201.vhd(118) | Removing redundant assignment. @N:CD364 : HV2201.vhd(119) | Removing redundant assignment. Post processing for work.hv2201.behaviourals @W:CL111 : HV2201.vhd(81) | All reachable assignments to SW_CLR(0) are '0'; removing register. To preserve a constant register, use the syn_preserve attribute. @W:CL111 : HV2201.vhd(81) | All reachable assignments to SW_CLR(1) are '0'; removing register. To preserve a constant register, use the syn_preserve attribute. @N:CD630 : ShiftReg74AHC595.vhd(5) | Synthesizing work.shiftreg74ahc595.behavioural. @N:CD231 : ShiftReg74AHC595.vhd(30) | Using onehot encoding for type state_type. For example, enumeration sm_reset is mapped to "100000000000000000000". @N:CD364 : ShiftReg74AHC595.vhd(78) | Removing redundant assignment. @N:CD364 : ShiftReg74AHC595.vhd(79) | Removing redundant assignment. Post processing for work.shiftreg74ahc595.behavioural Post processing for work.switchcontrol.behavioural @W:CL169 : SwitchControl.vhd(76) | Pruning unused register Switch_D_COPY_3(15 downto 0). Make sure that there are no unused intermediate registers. @W:CL169 : SwitchControl.vhd(76) | Pruning unused register Switch_C_COPY_3(15 downto 0). Make sure that there are no unused intermediate registers. @W:CL169 : SwitchControl.vhd(76) | Pruning unused register Switch_B_COPY_3(15 downto 0). Make sure that there are no unused intermediate registers. @W:CL169 : SwitchControl.vhd(76) | Pruning unused register Switch_A_COPY_3(15 downto 0). Make sure that there are no unused intermediate registers. @N:CD630 : InputParser.vhd(5) | Synthesizing work.inputparser.behavioral. @N:CD231 : InputParser.vhd(32) | Using onehot encoding for type state_type. For example, enumeration sm_reset is mapped to "100000000000000000". @N:CD364 : InputParser.vhd(111) | Removing redundant assignment. @N:CD364 : InputParser.vhd(112) | Removing redundant assignment. @N:CD364 : InputParser.vhd(115) | Removing redundant assignment. @N:CD364 : InputParser.vhd(116) | Removing redundant assignment. Post processing for work.inputparser.behavioral @A:CL282 : InputParser.vhd(79) | Feedback mux created for signal DATA_OUT_EXT[8:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value. @A:CL282 : InputParser.vhd(79) | Feedback mux created for signal DATA_OUT_VALID_EXT. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value. @N:CD630 : DACSwitchCore.vhd(5) | Synthesizing work.dacswitchcore.behavioral. @W:CD434 : DACSwitchCore.vhd(57) | Signal input_data_tg in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process. @W:CD434 : DACSwitchCore.vhd(57) | Signal input_data_valid_tg in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process. @W:CD434 : DACSwitchCore.vhd(59) | Signal clk in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process. @N:CD630 : AD5360_TestProgrammer.vhd(6) | Synthesizing work.ad5360programmer.behavioral. @N:CD231 : AD5360_TestProgrammer.vhd(40) | Using onehot encoding for type state_type. For example, enumeration sm_reset is mapped to "1000000". @N:CD364 : AD5360_TestProgrammer.vhd(113) | Removing redundant assignment. @N:CD630 : AD5360_Controlle.vhd(7) | Synthesizing work.ad5360_controller.behavioral. @N:CD231 : AD5360_Controlle.vhd(109) | Using onehot encoding for type state_type. For example, enumeration sm_reset is mapped to "1000000000000000000". @N:CD364 : AD5360_Controlle.vhd(190) | Removing redundant assignment. @N:CD364 : AD5360_Controlle.vhd(191) | Removing redundant assignment. @N:CD364 : AD5360_Controlle.vhd(192) | Removing redundant assignment. @N:CD364 : AD5360_Controlle.vhd(193) | Removing redundant assignment. @N:CD364 : AD5360_Controlle.vhd(194) | Removing redundant assignment. @N:CD364 : AD5360_Controlle.vhd(195) | Removing redundant assignment. @N:CD364 : AD5360_Controlle.vhd(196) | Removing redundant assignment. @N:CD364 : AD5360_Controlle.vhd(197) | Removing redundant assignment. @N:CD364 : AD5360_Controlle.vhd(198) | Removing redundant assignment. @N:CD364 : AD5360_Controlle.vhd(199) | Removing redundant assignment. @N:CD364 : AD5360_Controlle.vhd(200) | Removing redundant assignment. @N:CD364 : AD5360_Controlle.vhd(201) | Removing redundant assignment. @N:CD364 : AD5360_Controlle.vhd(202) | Removing redundant assignment. @N:CD364 : AD5360_Controlle.vhd(203) | Removing redundant assignment. @N:CD364 : AD5360_Controlle.vhd(204) | Removing redundant assignment. @N:CD364 : AD5360_Controlle.vhd(205) | Removing redundant assignment. @N:CD364 : AD5360_Controlle.vhd(206) | Removing redundant assignment. @N:CD364 : AD5360_Controlle.vhd(207) | Removing redundant assignment. @N:CD364 : AD5360_Controlle.vhd(208) | Removing redundant assignment. @N:CD364 : AD5360_Controlle.vhd(209) | Removing redundant assignment. @N:CD364 : AD5360_Controlle.vhd(210) | Removing redundant assignment. @N:CD364 : AD5360_Controlle.vhd(211) | Removing redundant assignment. @N:CD364 : AD5360_Controlle.vhd(212) | Removing redundant assignment. @N:CD364 : AD5360_Controlle.vhd(213) | Removing redundant assignment. @N:CD364 : AD5360_Controlle.vhd(214) | Removing redundant assignment. @N:CD364 : AD5360_Controlle.vhd(215) | Removing redundant assignment. @N:CD364 : AD5360_Controlle.vhd(216) | Removing redundant assignment. @N:CD364 : AD5360_Controlle.vhd(217) | Removing redundant assignment. @N:CD364 : AD5360_Controlle.vhd(218) | Removing redundant assignment. @N:CD364 : AD5360_Controlle.vhd(219) | Removing redundant assignment. @N:CD364 : AD5360_Controlle.vhd(220) | Removing redundant assignment. @N:CD364 : AD5360_Controlle.vhd(221) | Removing redundant assignment. @N:CD364 : AD5360_Controlle.vhd(405) | Removing redundant assignment. @N:CD364 : AD5360_Controlle.vhd(406) | Removing redundant assignment. @N:CD364 : AD5360_Controlle.vhd(407) | Removing redundant assignment. @N:CD364 : AD5360_Controlle.vhd(408) | Removing redundant assignment. @N:CD364 : AD5360_Controlle.vhd(409) | Removing redundant assignment. @N:CD364 : AD5360_Controlle.vhd(410) | Removing redundant assignment. @N:CD364 : AD5360_Controlle.vhd(411) | Removing redundant assignment. @N:CD364 : AD5360_Controlle.vhd(412) | Removing redundant assignment. @N:CD364 : AD5360_Controlle.vhd(413) | Removing redundant assignment. @N:CD364 : AD5360_Controlle.vhd(414) | Removing redundant assignment. @N:CD364 : AD5360_Controlle.vhd(415) | Removing redundant assignment. @N:CD364 : AD5360_Controlle.vhd(416) | Removing redundant assignment. @N:CD364 : AD5360_Controlle.vhd(417) | Removing redundant assignment. @N:CD364 : AD5360_Controlle.vhd(418) | Removing redundant assignment. @N:CD364 : AD5360_Controlle.vhd(419) | Removing redundant assignment. @N:CD364 : AD5360_Controlle.vhd(420) | Removing redundant assignment. @N:CD364 : AD5360_Controlle.vhd(421) | Removing redundant assignment. @N:CD364 : AD5360_Controlle.vhd(422) | Removing redundant assignment. @N:CD364 : AD5360_Controlle.vhd(423) | Removing redundant assignment. @N:CD364 : AD5360_Controlle.vhd(424) | Removing redundant assignment. @N:CD364 : AD5360_Controlle.vhd(425) | Removing redundant assignment. @N:CD364 : AD5360_Controlle.vhd(426) | Removing redundant assignment. @N:CD364 : AD5360_Controlle.vhd(427) | Removing redundant assignment. @N:CD364 : AD5360_Controlle.vhd(428) | Removing redundant assignment. @N:CD364 : AD5360_Controlle.vhd(429) | Removing redundant assignment. @N:CD364 : AD5360_Controlle.vhd(430) | Removing redundant assignment. @N:CD364 : AD5360_Controlle.vhd(431) | Removing redundant assignment. @N:CD364 : AD5360_Controlle.vhd(432) | Removing redundant assignment. @N:CD364 : AD5360_Controlle.vhd(433) | Removing redundant assignment. @N:CD364 : AD5360_Controlle.vhd(434) | Removing redundant assignment. @N:CD364 : AD5360_Controlle.vhd(435) | Removing redundant assignment. @N:CD364 : AD5360_Controlle.vhd(436) | Removing redundant assignment. @N:CD364 : AD5360_Controlle.vhd(439) | Removing redundant assignment. @N:CD364 : AD5360_Controlle.vhd(442) | Removing redundant assignment. @N:CD630 : AD5360_PHY.vhd(5) | Synthesizing work.ad5360_phy.behavioral. @N:CD232 : AD5360_PHY.vhd(31) | Using gray code encoding for type state_type. @N:CD364 : AD5360_PHY.vhd(100) | Removing redundant assignment. Post processing for work.ad5360_phy.behavioral Post processing for work.ad5360_controller.behavioral @W:CL190 : AD5360_Controlle.vhd(106) | Optimizing register bit Output_24BitString(21) to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL260 : AD5360_Controlle.vhd(106) | Pruning register bit 21 of Output_24BitString(23 downto 0). If this is not the intended behavior, drive the input with valid values, or an input from the top level. Post processing for work.ad5360programmer.behavioral @N:CD630 : PackageDisassembler.vhd(5) | Synthesizing work.packagedisassembler.behavioral. @N:CD232 : PackageDisassembler.vhd(69) | Using gray code encoding for type state_type. @N:CD364 : PackageDisassembler.vhd(208) | Removing redundant assignment. @N:CD364 : PackageDisassembler.vhd(261) | Removing redundant assignment. @N:CD364 : PackageDisassembler.vhd(262) | Removing redundant assignment. @N:CD364 : PackageDisassembler.vhd(264) | Removing redundant assignment. @N:CD364 : PackageDisassembler.vhd(267) | Removing redundant assignment. @N:CD364 : PackageDisassembler.vhd(268) | Removing redundant assignment. @N:CD364 : PackageDisassembler.vhd(269) | Removing redundant assignment. @N:CD364 : PackageDisassembler.vhd(270) | Removing redundant assignment. @N:CD364 : PackageDisassembler.vhd(271) | Removing redundant assignment. @N:CD364 : PackageDisassembler.vhd(272) | Removing redundant assignment. @N:CD364 : PackageDisassembler.vhd(273) | Removing redundant assignment. @N:CD364 : PackageDisassembler.vhd(274) | Removing redundant assignment. @N:CD364 : PackageDisassembler.vhd(275) | Removing redundant assignment. @N:CD364 : PackageDisassembler.vhd(276) | Removing redundant assignment. @N:CD364 : PackageDisassembler.vhd(277) | Removing redundant assignment. @N:CD364 : PackageDisassembler.vhd(278) | Removing redundant assignment. @N:CD364 : PackageDisassembler.vhd(279) | Removing redundant assignment. @N:CD364 : PackageDisassembler.vhd(280) | Removing redundant assignment. @N:CD364 : PackageDisassembler.vhd(281) | Removing redundant assignment. @N:CD364 : PackageDisassembler.vhd(282) | Removing redundant assignment. @N:CD364 : PackageDisassembler.vhd(283) | Removing redundant assignment. @N:CD364 : PackageDisassembler.vhd(284) | Removing redundant assignment. @N:CD364 : PackageDisassembler.vhd(285) | Removing redundant assignment. @N:CD364 : PackageDisassembler.vhd(286) | Removing redundant assignment. @N:CD364 : PackageDisassembler.vhd(287) | Removing redundant assignment. @N:CD364 : PackageDisassembler.vhd(288) | Removing redundant assignment. @N:CD364 : PackageDisassembler.vhd(289) | Removing redundant assignment. @N:CD630 : FIFO_DISASSEMBLE.vhd(8) | Synthesizing work.fifo_disassemble.def_arch. @N:CD630 : igloo.vhd(2722) | Synthesizing igloo.vcc.syn_black_box. Post processing for igloo.vcc.syn_black_box @N:CD630 : igloo.vhd(1787) | Synthesizing igloo.gnd.syn_black_box. Post processing for igloo.gnd.syn_black_box @N:CD630 : igloo.vhd(1934) | Synthesizing igloo.inv.syn_black_box. Post processing for igloo.inv.syn_black_box @N:CD630 : igloo.vhd(2198) | Synthesizing igloo.or2.syn_black_box. Post processing for igloo.or2.syn_black_box @N:CD630 : igloo.vhd(3039) | Synthesizing igloo.fifo4k18.syn_black_box. Post processing for igloo.fifo4k18.syn_black_box @N:CD630 : igloo.vhd(13) | Synthesizing igloo.and2.syn_black_box. Post processing for igloo.and2.syn_black_box @N:CD630 : igloo.vhd(2032) | Synthesizing igloo.nand2.syn_black_box. Post processing for igloo.nand2.syn_black_box @N:CD630 : igloo.vhd(2040) | Synthesizing igloo.nand2a.syn_black_box. Post processing for igloo.nand2a.syn_black_box Post processing for work.fifo_disassemble.def_arch Post processing for work.packagedisassembler.behavioral @N:CD630 : TestPackageGenerator.vhd(72) | Synthesizing work.testpackagegenerator.behavioral. @N:CD232 : TestPackageGenerator.vhd(86) | Using gray code encoding for type state_type. @N:CD364 : TestPackageGenerator.vhd(170) | Removing redundant assignment. Post processing for work.testpackagegenerator.behavioral Post processing for work.dacswitchcore.behavioral @W:CL168 : DACSwitchCore.vhd(73) | Removing instance TestGen because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. Post processing for work.igloo_top.igloo_top_arch @W:CL169 : IGLOO_TOP.vhd(100) | Pruning unused register SF_VALID_Buffer_1. Make sure that there are no unused intermediate registers. @W:CL169 : IGLOO_TOP.vhd(133) | Pruning unused register SF_DATA_Buffer_1(7 downto 0). Make sure that there are no unused intermediate registers. @N:CL201 : TestPackageGenerator.vhd(158) | Trying to extract state machine for register SPIMACHINE_STATE. Extracted state machine for register SPIMACHINE_STATE State machine has 51 reachable states with original encodings of: 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 101000 101001 101011 110000 110001 110010 110011 110100 110101 110110 110111 111000 111001 111010 111011 111100 111101 111110 111111 @N:CL201 : PackageDisassembler.vhd(225) | Trying to extract state machine for register SPIMACHINE_STATE. Extracted state machine for register SPIMACHINE_STATE State machine has 57 reachable states with original encodings of: 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 100100 101000 101001 101010 101011 101100 101101 101110 101111 110000 110001 110010 110011 110100 110101 110110 110111 111000 111001 111010 111011 111100 111101 111110 111111 @N:CL201 : AD5360_PHY.vhd(84) | Trying to extract state machine for register SPIMACHINE_STATE. Extracted state machine for register SPIMACHINE_STATE State machine has 29 reachable states with original encodings of: 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10010 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 @N:CL201 : AD5360_Controlle.vhd(362) | Trying to extract state machine for register SPIMACHINE_STATE. Extracted state machine for register SPIMACHINE_STATE State machine has 19 reachable states with original encodings of: 0000000000000000001 0000000000000000010 0000000000000000100 0000000000000001000 0000000000000010000 0000000000000100000 0000000000001000000 0000000000010000000 0000000000100000000 0000000001000000000 0000000010000000000 0000000100000000000 0000001000000000000 0000010000000000000 0000100000000000000 0001000000000000000 0010000000000000000 0100000000000000000 1000000000000000000 @N:CL201 : AD5360_TestProgrammer.vhd(95) | Trying to extract state machine for register SPIMACHINE_STATE. Extracted state machine for register SPIMACHINE_STATE State machine has 7 reachable states with original encodings of: 0000001 0000010 0000100 0001000 0010000 0100000 1000000 @N:CL201 : InputParser.vhd(91) | Trying to extract state machine for register SPIMACHINE_STATE. Extracted state machine for register SPIMACHINE_STATE State machine has 18 reachable states with original encodings of: 000000000000000001 000000000000000010 000000000000000100 000000000000001000 000000000000010000 000000000000100000 000000000001000000 000000000010000000 000000000100000000 000000001000000000 000000010000000000 000000100000000000 000001000000000000 000010000000000000 000100000000000000 001000000000000000 010000000000000000 100000000000000000 @N:CL159 : InputParser.vhd(15) | Input DATA_OUT_FULL is unused. @N:CL201 : ShiftReg74AHC595.vhd(58) | Trying to extract state machine for register SPIMACHINE_STATE. Extracted state machine for register SPIMACHINE_STATE State machine has 21 reachable states with original encodings of: 000000000000000000001 000000000000000000010 000000000000000000100 000000000000000001000 000000000000000010000 000000000000000100000 000000000000001000000 000000000000010000000 000000000000100000000 000000000001000000000 000000000010000000000 000000000100000000000 000000001000000000000 000000010000000000000 000000100000000000000 000001000000000000000 000010000000000000000 000100000000000000000 001000000000000000000 010000000000000000000 100000000000000000000 @W:CL260 : HV2201.vhd(81) | Pruning register bit 1 of SW_NOT_LE(1 downto 0). If this is not the intended behavior, drive the input with valid values, or an input from the top level. @W:CL260 : HV2201.vhd(81) | Pruning register bit 1 of SW_CLK(1 downto 0). If this is not the intended behavior, drive the input with valid values, or an input from the top level. @N:CL201 : HV2201.vhd(81) | Trying to extract state machine for register SPIMACHINE_STATE. Extracted state machine for register SPIMACHINE_STATE State machine has 23 reachable states with original encodings of: 00000000000000000000001 00000000000000000000010 00000000000000000000100 00000000000000000001000 00000000000000000010000 00000000000000000100000 00000000000000001000000 00000000000000010000000 00000000000000100000000 00000000000001000000000 00000000000010000000000 00000000000100000000000 00000000001000000000000 00000000010000000000000 00000000100000000000000 00000001000000000000000 00000010000000000000000 00000100000000000000000 00001000000000000000000 00010000000000000000000 00100000000000000000000 01000000000000000000000 10000000000000000000000 At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 72MB peak: 73MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Fri Apr 07 12:05:03 2017 ###########################################################] Synopsys Netlist Linker, version comp2016q3p1, Build 117R, built Nov 17 2016 @N: : | Running in 64-bit mode At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 69MB peak: 69MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Fri Apr 07 12:05:04 2017 ###########################################################] @END At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Fri Apr 07 12:05:04 2017 ###########################################################] Synopsys Netlist Linker, version comp2016q3p1, Build 117R, built Nov 17 2016 @N: : | Running in 64-bit mode File C:\Users\agpawelzik\Desktop\IGLOO_TestGen\synthesis\synwork\IGLOO_TOP_comp.srs changed - recompiling At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 69MB peak: 70MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Fri Apr 07 12:05:05 2017 ###########################################################] Pre-mapping Report # Fri Apr 07 12:05:06 2017 Synopsys Microsemi Technology Pre-mapping, Version mapact, Build 1920R, Built Nov 17 2016 09:40:34 Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Product Version L-2016.09M-2 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB) Reading constraint file: C:\Users\agpawelzik\Desktop\IGLOO_TestGen\constraint\IGLOO.sdc Linked File: IGLOO_TOP_scck.rpt Printing clock summary report in "C:\Users\agpawelzik\Desktop\IGLOO_TestGen\synthesis\IGLOO_TOP_scck.rpt" file @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 105MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 105MB) @N:BN362 : inputparser.vhd(76) | Removing sequential instance DEBUG_DATA[8:0] (in view: work.InputParser(behavioral)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : inputparser.vhd(76) | Removing sequential instance DEBUG_DATA_FSM[8:0] (in view: work.InputParser(behavioral)) of type view:PrimLib.dffr(prim) because it does not drive other instances. Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 110MB peak: 111MB) Clock Summary ***************** Start Requested Requested Clock Clock Clock Clock Frequency Period Type Group Load -------------------------------------------------------------------------------------------------------- HV2201|ClkHalf_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_0 98 IGLOO_TOP|Clk 25.0 MHz 40.000 declared default_clkgroup 1236 ======================================================================================================== @W:MT530 : hv2201.vhd(81) | Found inferred clock HV2201|ClkHalf_inferred_clock which controls 98 sequential elements including MySwitchControl.MyHV2201.SW_DIN[7:0]. This clock has no specified timing constraint which may adversely impact design performance. Finished Pre Mapping Phase. @N:BN225 : | Writing default property annotation file C:\Users\agpawelzik\Desktop\IGLOO_TestGen\synthesis\IGLOO_TOP.sap. Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 110MB peak: 111MB) Encoding state machine SPIMACHINE_STATE[0:56] (in view: work.PackageDisassembler(behavioral)) original code -> new code 000000 -> 000000 000001 -> 000001 000010 -> 000011 000011 -> 000010 000100 -> 000110 000101 -> 000111 000110 -> 000101 000111 -> 000100 001000 -> 001100 001001 -> 001101 001010 -> 001111 001011 -> 001110 001100 -> 001010 001101 -> 001011 001110 -> 001001 001111 -> 001000 010000 -> 011000 010001 -> 011001 010010 -> 011011 010011 -> 011010 010100 -> 011110 010101 -> 011111 010110 -> 011101 010111 -> 011100 011000 -> 010100 011001 -> 010101 011010 -> 010111 011011 -> 010110 011100 -> 010010 011101 -> 010011 011110 -> 010001 011111 -> 010000 100100 -> 110000 101000 -> 110001 101001 -> 110011 101010 -> 110010 101011 -> 110110 101100 -> 110111 101101 -> 110101 101110 -> 110100 101111 -> 111100 110000 -> 111101 110001 -> 111111 110010 -> 111110 110011 -> 111010 110100 -> 111011 110101 -> 111001 110110 -> 111000 110111 -> 101000 111000 -> 101001 111001 -> 101011 111010 -> 101010 111011 -> 101110 111100 -> 101111 111101 -> 101101 111110 -> 101100 111111 -> 100100 Encoding state machine SPIMACHINE_STATE[0:28] (in view: work.AD5360_PHY(behavioral)) original code -> new code 00000 -> 00000 00001 -> 00001 00010 -> 00011 00011 -> 00010 00100 -> 00110 00101 -> 00111 00110 -> 00101 00111 -> 00100 01000 -> 01100 01001 -> 01101 01010 -> 01111 01011 -> 01110 01100 -> 01010 01101 -> 01011 01110 -> 01001 01111 -> 01000 10010 -> 11000 10100 -> 11001 10101 -> 11011 10110 -> 11010 10111 -> 11110 11000 -> 11111 11001 -> 11101 11010 -> 11100 11011 -> 10100 11100 -> 10101 11101 -> 10111 11110 -> 10110 11111 -> 10010 Encoding state machine SPIMACHINE_STATE[0:18] (in view: work.AD5360_Controller(behavioral)) original code -> new code 0000000000000000001 -> 0000000000000000001 0000000000000000010 -> 0000000000000000010 0000000000000000100 -> 0000000000000000100 0000000000000001000 -> 0000000000000001000 0000000000000010000 -> 0000000000000010000 0000000000000100000 -> 0000000000000100000 0000000000001000000 -> 0000000000001000000 0000000000010000000 -> 0000000000010000000 0000000000100000000 -> 0000000000100000000 0000000001000000000 -> 0000000001000000000 0000000010000000000 -> 0000000010000000000 0000000100000000000 -> 0000000100000000000 0000001000000000000 -> 0000001000000000000 0000010000000000000 -> 0000010000000000000 0000100000000000000 -> 0000100000000000000 0001000000000000000 -> 0001000000000000000 0010000000000000000 -> 0010000000000000000 0100000000000000000 -> 0100000000000000000 1000000000000000000 -> 1000000000000000000 Encoding state machine SPIMACHINE_STATE[0:6] (in view: work.AD5360Programmer(behavioral)) original code -> new code 0000001 -> 0000001 0000010 -> 0000010 0000100 -> 0000100 0001000 -> 0001000 0010000 -> 0010000 0100000 -> 0100000 1000000 -> 1000000 Encoding state machine SPIMACHINE_STATE[0:17] (in view: work.InputParser(behavioral)) original code -> new code 000000000000000001 -> 000000000000000001 000000000000000010 -> 000000000000000010 000000000000000100 -> 000000000000000100 000000000000001000 -> 000000000000001000 000000000000010000 -> 000000000000010000 000000000000100000 -> 000000000000100000 000000000001000000 -> 000000000001000000 000000000010000000 -> 000000000010000000 000000000100000000 -> 000000000100000000 000000001000000000 -> 000000001000000000 000000010000000000 -> 000000010000000000 000000100000000000 -> 000000100000000000 000001000000000000 -> 000001000000000000 000010000000000000 -> 000010000000000000 000100000000000000 -> 000100000000000000 001000000000000000 -> 001000000000000000 010000000000000000 -> 010000000000000000 100000000000000000 -> 100000000000000000 @N:BN362 : inputparser.vhd(91) | Removing sequential instance SPIMACHINE_STATE[17] (in view: work.InputParser(behavioral)) of type view:PrimLib.dffs(prim) because it does not drive other instances. Encoding state machine SPIMACHINE_STATE[0:20] (in view: work.ShiftReg74AHC595(behavioural)) original code -> new code 000000000000000000001 -> 000000000000000000001 000000000000000000010 -> 000000000000000000010 000000000000000000100 -> 000000000000000000100 000000000000000001000 -> 000000000000000001000 000000000000000010000 -> 000000000000000010000 000000000000000100000 -> 000000000000000100000 000000000000001000000 -> 000000000000001000000 000000000000010000000 -> 000000000000010000000 000000000000100000000 -> 000000000000100000000 000000000001000000000 -> 000000000001000000000 000000000010000000000 -> 000000000010000000000 000000000100000000000 -> 000000000100000000000 000000001000000000000 -> 000000001000000000000 000000010000000000000 -> 000000010000000000000 000000100000000000000 -> 000000100000000000000 000001000000000000000 -> 000001000000000000000 000010000000000000000 -> 000010000000000000000 000100000000000000000 -> 000100000000000000000 001000000000000000000 -> 001000000000000000000 010000000000000000000 -> 010000000000000000000 100000000000000000000 -> 100000000000000000000 Encoding state machine SPIMACHINE_STATE[0:22] (in view: work.HV2201(behaviourals)) original code -> new code 00000000000000000000001 -> 00000000000000000000001 00000000000000000000010 -> 00000000000000000000010 00000000000000000000100 -> 00000000000000000000100 00000000000000000001000 -> 00000000000000000001000 00000000000000000010000 -> 00000000000000000010000 00000000000000000100000 -> 00000000000000000100000 00000000000000001000000 -> 00000000000000001000000 00000000000000010000000 -> 00000000000000010000000 00000000000000100000000 -> 00000000000000100000000 00000000000001000000000 -> 00000000000001000000000 00000000000010000000000 -> 00000000000010000000000 00000000000100000000000 -> 00000000000100000000000 00000000001000000000000 -> 00000000001000000000000 00000000010000000000000 -> 00000000010000000000000 00000000100000000000000 -> 00000000100000000000000 00000001000000000000000 -> 00000001000000000000000 00000010000000000000000 -> 00000010000000000000000 00000100000000000000000 -> 00000100000000000000000 00001000000000000000000 -> 00001000000000000000000 00010000000000000000000 -> 00010000000000000000000 00100000000000000000000 -> 00100000000000000000000 01000000000000000000000 -> 01000000000000000000000 10000000000000000000000 -> 10000000000000000000000 None None @W:MF511 : | Found issues with constraints. Please check constraint checker report "C:\Users\agpawelzik\Desktop\IGLOO_TestGen\synthesis\IGLOO_TOP_cck.rpt" . Finished constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 118MB peak: 120MB) Pre-mapping successful! At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 28MB peak: 120MB) Process took 0h:00m:02s realtime, 0h:00m:02s cputime # Fri Apr 07 12:05:08 2017 ###########################################################] Map & Optimize Report # Fri Apr 07 12:05:08 2017 Synopsys Microsemi Technology Mapper, Version mapact, Build 1920R, Built Nov 17 2016 09:40:34 Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Product Version L-2016.09M-2 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB) @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB) Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 110MB) Available hyper_sources - for debug and ip models None Found Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 110MB peak: 111MB) @N:MO231 : igloo_top.vhd(179) | Found counter in view:work.IGLOO_TOP(igloo_top_arch) instance SF_READY_COUNTER[7:0] Encoding state machine SPIMACHINE_STATE[0:56] (in view: work.PackageDisassembler(behavioral)) original code -> new code 000000 -> 000000 000001 -> 000001 000010 -> 000011 000011 -> 000010 000100 -> 000110 000101 -> 000111 000110 -> 000101 000111 -> 000100 001000 -> 001100 001001 -> 001101 001010 -> 001111 001011 -> 001110 001100 -> 001010 001101 -> 001011 001110 -> 001001 001111 -> 001000 010000 -> 011000 010001 -> 011001 010010 -> 011011 010011 -> 011010 010100 -> 011110 010101 -> 011111 010110 -> 011101 010111 -> 011100 011000 -> 010100 011001 -> 010101 011010 -> 010111 011011 -> 010110 011100 -> 010010 011101 -> 010011 011110 -> 010001 011111 -> 010000 100100 -> 110000 101000 -> 110001 101001 -> 110011 101010 -> 110010 101011 -> 110110 101100 -> 110111 101101 -> 110101 101110 -> 110100 101111 -> 111100 110000 -> 111101 110001 -> 111111 110010 -> 111110 110011 -> 111010 110100 -> 111011 110101 -> 111001 110110 -> 111000 110111 -> 101000 111000 -> 101001 111001 -> 101011 111010 -> 101010 111011 -> 101110 111100 -> 101111 111101 -> 101101 111110 -> 101100 111111 -> 100100 @N:MO231 : ad5360_testprogrammer.vhd(54) | Found counter in view:work.AD5360Programmer(behavioral) instance ResetCounter[39:0] Encoding state machine SPIMACHINE_STATE[0:6] (in view: work.AD5360Programmer(behavioral)) original code -> new code 0000001 -> 0000001 0000010 -> 0000010 0000100 -> 0000100 0001000 -> 0001000 0010000 -> 0010000 0100000 -> 0100000 1000000 -> 1000000 Encoding state machine SPIMACHINE_STATE[0:18] (in view: work.AD5360_Controller(behavioral)) original code -> new code 0000000000000000001 -> 0000000000000000001 0000000000000000010 -> 0000000000000000010 0000000000000000100 -> 0000000000000000100 0000000000000001000 -> 0000000000000001000 0000000000000010000 -> 0000000000000010000 0000000000000100000 -> 0000000000000100000 0000000000001000000 -> 0000000000001000000 0000000000010000000 -> 0000000000010000000 0000000000100000000 -> 0000000000100000000 0000000001000000000 -> 0000000001000000000 0000000010000000000 -> 0000000010000000000 0000000100000000000 -> 0000000100000000000 0000001000000000000 -> 0000001000000000000 0000010000000000000 -> 0000010000000000000 0000100000000000000 -> 0000100000000000000 0001000000000000000 -> 0001000000000000000 0010000000000000000 -> 0010000000000000000 0100000000000000000 -> 0100000000000000000 1000000000000000000 -> 1000000000000000000 Encoding state machine SPIMACHINE_STATE[0:28] (in view: work.AD5360_PHY(behavioral)) original code -> new code 00000 -> 00000 00001 -> 00001 00010 -> 00011 00011 -> 00010 00100 -> 00110 00101 -> 00111 00110 -> 00101 00111 -> 00100 01000 -> 01100 01001 -> 01101 01010 -> 01111 01011 -> 01110 01100 -> 01010 01101 -> 01011 01110 -> 01001 01111 -> 01000 10010 -> 11000 10100 -> 11001 10101 -> 11011 10110 -> 11010 10111 -> 11110 11000 -> 11111 11001 -> 11101 11010 -> 11100 11011 -> 10100 11100 -> 10101 11101 -> 10111 11110 -> 10110 11111 -> 10010 @W:MO160 : ad5360_phy.vhd(27) | Register bit DATABUFFER[21] (in view view:work.AD5360_PHY(behavioral)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. Encoding state machine SPIMACHINE_STATE[0:17] (in view: work.InputParser(behavioral)) original code -> new code 000000000000000001 -> 000000000000000001 000000000000000010 -> 000000000000000010 000000000000000100 -> 000000000000000100 000000000000001000 -> 000000000000001000 000000000000010000 -> 000000000000010000 000000000000100000 -> 000000000000100000 000000000001000000 -> 000000000001000000 000000000010000000 -> 000000000010000000 000000000100000000 -> 000000000100000000 000000001000000000 -> 000000001000000000 000000010000000000 -> 000000010000000000 000000100000000000 -> 000000100000000000 000001000000000000 -> 000001000000000000 000010000000000000 -> 000010000000000000 000100000000000000 -> 000100000000000000 001000000000000000 -> 001000000000000000 010000000000000000 -> 010000000000000000 100000000000000000 -> 100000000000000000 @N:BN362 : inputparser.vhd(91) | Removing sequential instance SPIMACHINE_STATE[17] (in view: work.InputParser(behavioral)) of type view:PrimLib.dffs(prim) because it does not drive other instances. Encoding state machine SPIMACHINE_STATE[0:20] (in view: work.ShiftReg74AHC595(behavioural)) original code -> new code 000000000000000000001 -> 000000000000000000001 000000000000000000010 -> 000000000000000000010 000000000000000000100 -> 000000000000000000100 000000000000000001000 -> 000000000000000001000 000000000000000010000 -> 000000000000000010000 000000000000000100000 -> 000000000000000100000 000000000000001000000 -> 000000000000001000000 000000000000010000000 -> 000000000000010000000 000000000000100000000 -> 000000000000100000000 000000000001000000000 -> 000000000001000000000 000000000010000000000 -> 000000000010000000000 000000000100000000000 -> 000000000100000000000 000000001000000000000 -> 000000001000000000000 000000010000000000000 -> 000000010000000000000 000000100000000000000 -> 000000100000000000000 000001000000000000000 -> 000001000000000000000 000010000000000000000 -> 000010000000000000000 000100000000000000000 -> 000100000000000000000 001000000000000000000 -> 001000000000000000000 010000000000000000000 -> 010000000000000000000 100000000000000000000 -> 100000000000000000000 @N:BN362 : shiftreg74ahc595.vhd(58) | Removing sequential instance SPIMACHINE_STATE[0] (in view: work.ShiftReg74AHC595(behavioural)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : shiftreg74ahc595.vhd(58) | Removing sequential instance SPIMACHINE_STATE[20] (in view: work.ShiftReg74AHC595(behavioural)) of type view:PrimLib.dffs(prim) because it does not drive other instances. Encoding state machine SPIMACHINE_STATE[0:22] (in view: work.HV2201(behaviourals)) original code -> new code 00000000000000000000001 -> 00000000000000000000001 00000000000000000000010 -> 00000000000000000000010 00000000000000000000100 -> 00000000000000000000100 00000000000000000001000 -> 00000000000000000001000 00000000000000000010000 -> 00000000000000000010000 00000000000000000100000 -> 00000000000000000100000 00000000000000001000000 -> 00000000000000001000000 00000000000000010000000 -> 00000000000000010000000 00000000000000100000000 -> 00000000000000100000000 00000000000001000000000 -> 00000000000001000000000 00000000000010000000000 -> 00000000000010000000000 00000000000100000000000 -> 00000000000100000000000 00000000001000000000000 -> 00000000001000000000000 00000000010000000000000 -> 00000000010000000000000 00000000100000000000000 -> 00000000100000000000000 00000001000000000000000 -> 00000001000000000000000 00000010000000000000000 -> 00000010000000000000000 00000100000000000000000 -> 00000100000000000000000 00001000000000000000000 -> 00001000000000000000000 00010000000000000000000 -> 00010000000000000000000 00100000000000000000000 -> 00100000000000000000000 01000000000000000000000 -> 01000000000000000000000 10000000000000000000000 -> 10000000000000000000000 @N:BN362 : hv2201.vhd(81) | Removing sequential instance SPIMACHINE_STATE[0] (in view: work.HV2201(behaviourals)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : hv2201.vhd(81) | Removing sequential instance SPIMACHINE_STATE[22] (in view: work.HV2201(behaviourals)) of type view:PrimLib.dffs(prim) because it does not drive other instances. Starting factoring (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 120MB peak: 121MB) Finished factoring (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 130MB peak: 136MB) @W:BN132 : ad5360_controlle.vhd(362) | Removing sequential instance MyDAC.MyAD5360.MyController.SPIMACHINE_STATE[18] because it is equivalent to instance MyDAC.MyAD5360.SPIMACHINE_STATE[6]. To keep the instance, apply constraint syn_preserve=1 on the instance. Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 126MB peak: 136MB) Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 131MB peak: 149MB) Starting Early Timing Optimization (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 133MB peak: 149MB) Finished Early Timing Optimization (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:09s; Memory used current: 132MB peak: 149MB) Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:09s; Memory used current: 132MB peak: 149MB) Finished preparing to map (Real Time elapsed 0h:00m:10s; CPU Time elapsed 0h:00m:09s; Memory used current: 131MB peak: 149MB) Finished technology mapping (Real Time elapsed 0h:00m:10s; CPU Time elapsed 0h:00m:10s; Memory used current: 147MB peak: 150MB) High Fanout Net Report ********************** Driver Instance / Pin Name Fanout, notes ------------------------------------------------------------------------------------------------ MySwitchControl.ShiftControlHV2201.data_0_prog4 / Y 65 MySwitchControl.MyHV2201.SPIMACHINE_STATE[21] / Q 66 MyDAC.MyAD5360.SPIMACHINE_STATE[4] / Q 42 MyDAC.MyAD5360.MyController.SPIMACHINE_STATE[17] / Q 291 MyDAC.MyAD5360.MyController.MyDAC.SPIMACHINE_STATE[2] / Q 26 MyDAC.MyAD5360.MyController.MyDAC.SPIMACHINE_STATE[3] / Q 32 Reset_pad / Y 1250 : 1236 asynchronous set/reset MyDAC.MyPackageDis.SPIMACHINE_STATE[0] / Q 27 MyDAC.MyPackageDis.SPIMACHINE_STATE[1] / Q 48 MyDAC.MyPackageDis.SPIMACHINE_STATE[2] / Q 31 MyDAC.MyPackageDis.SPIMACHINE_STATE[3] / Q 30 MyDAC.MyPackageDis.SPIMACHINE_STATE[4] / Q 28 MyDAC.MyPackageDis.SPIMACHINE_STATE[5] / Q 26 MyInputParser.Parser.un3_data_in_valid / Y 30 MyDAC.MyPackageDis.un1_SPIMACHINE_STATE_11_i / Y 40 MyDAC.MyAD5360.ResetCounter_n20_i_0_a3 / Y 40 MyDAC.MyPackageDis.SPIMACHINE_STATE_s9_i_o5 / Y 26 ================================================================================================ @N:FP130 : | Promoting Net Reset_c on CLKBUF Reset_pad @N:FP130 : | Promoting Net Clk_c on CLKBUF Clk_pad @N:FP130 : | Promoting Net MyDAC.MyAD5360.MyController.SPIMACHINE_STATE[17] on CLKINT I_170 @N:FP130 : | Promoting Net MySwitchControl.MyHV2201.ClkHalf on CLKINT MySwitchControl.MyHV2201.ClkHalf_inferred_clock @N:FP130 : | Promoting Net MySwitchControl.MyHV2201.SPIMACHINE_STATE[21] on CLKINT I_171 @N:FP130 : | Promoting Net MySwitchControl.ShiftControlHV2201\.data_0_prog4 on CLKINT I_172 Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:11s; Memory used current: 148MB peak: 150MB) Replicating Combinational Instance MyDAC.MyPackageDis.SPIMACHINE_STATE_s9_i_o5, fanout 26 segments 2 Replicating Combinational Instance MyDAC.MyAD5360.ResetCounter_n20_i_0_a3, fanout 40 segments 2 Replicating Combinational Instance MyDAC.MyPackageDis.un1_SPIMACHINE_STATE_11_i, fanout 40 segments 2 Replicating Combinational Instance MyInputParser.Parser.un3_data_in_valid, fanout 30 segments 2 Replicating Sequential Instance MyDAC.MyPackageDis.SPIMACHINE_STATE[5], fanout 26 segments 2 Replicating Sequential Instance MyDAC.MyPackageDis.SPIMACHINE_STATE[4], fanout 28 segments 2 Replicating Sequential Instance MyDAC.MyPackageDis.SPIMACHINE_STATE[3], fanout 31 segments 2 Replicating Sequential Instance MyDAC.MyPackageDis.SPIMACHINE_STATE[2], fanout 31 segments 2 Replicating Sequential Instance MyDAC.MyPackageDis.SPIMACHINE_STATE[1], fanout 48 segments 2 Replicating Sequential Instance MyDAC.MyPackageDis.SPIMACHINE_STATE[0], fanout 27 segments 2 Replicating Sequential Instance MyDAC.MyAD5360.MyController.MyDAC.SPIMACHINE_STATE[3], fanout 32 segments 2 Replicating Sequential Instance MyDAC.MyAD5360.MyController.MyDAC.SPIMACHINE_STATE[2], fanout 26 segments 2 Replicating Sequential Instance MyDAC.MyAD5360.SPIMACHINE_STATE[4], fanout 42 segments 2 Added 0 Buffers Added 13 Cells via replication Added 9 Sequential Cells via replication Added 4 Combinational Cells via replication Finished restoring hierarchy (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:11s; Memory used current: 149MB peak: 150MB) @S |Clock Optimization Summary #### START OF CLOCK OPTIMIZATION REPORT #####[ Clock optimization not enabled 1 non-gated/non-generated clock tree(s) driving 1165 clock pin(s) of sequential element(s) 1 gated/generated clock tree(s) driving 96 clock pin(s) of sequential element(s) 0 instances converted, 96 sequential instances remain driven by gated/generated clocks ================================ Non-Gated/Non-Generated Clocks ================================= Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance ------------------------------------------------------------------------------------------------- ClockId0002 Clk clock definition on port 1165 SF_READY_COUNTER[6] ================================================================================================= ========================================================================================== Gated/Generated Clocks =========================================================================================== Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance Explanation ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- ClockId0001 MySwitchControl.MyHV2201.ClkHalf DFN1C0 96 MySwitchControl.MyHV2201.DATA_0_COPY[0] No generated or derived clock directive on output of sequential instance ============================================================================================================================================================================================================= ##### END OF CLOCK OPTIMIZATION REPORT ######] Start Writing Netlists (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:12s; Memory used current: 145MB peak: 150MB) Writing Analyst data base C:\Users\agpawelzik\Desktop\IGLOO_TestGen\synthesis\synwork\IGLOO_TOP_m.srm Finished Writing Netlist Databases (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:12s; Memory used current: 147MB peak: 150MB) Writing EDIF Netlist and constraint files L-2016.09M-2 Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:13s; Memory used current: 148MB peak: 150MB) Start final timing analysis (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:13s; Memory used current: 147MB peak: 150MB) @N:MT615 : | Found clock IGLOO_TOP|Clk with period 40.00ns @W:MT420 : | Found inferred clock HV2201|ClkHalf_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:MySwitchControl.MyHV2201.ClkHalf" ##### START OF TIMING REPORT #####[ # Timing Report written on Fri Apr 07 12:05:22 2017 # Top view: IGLOO_TOP Library name: IGLOO_V2 Operating conditions: COMWCSTD ( T = 70.0, V = 1.14, P = 3.70, tree_type = balanced_tree ) Requested Frequency: 25.0 MHz Wire load mode: top Wire load model: igloo Paths requested: 5 Constraint File(s): C:\Users\agpawelzik\Desktop\IGLOO_TestGen\constraint\IGLOO.sdc @N:MT320 : | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. @N:MT322 : | Clock constraints include only register-to-register paths associated with each individual clock. Performance Summary ******************* Worst slack in design: -8.413 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ------------------------------------------------------------------------------------------------------------------------------------- HV2201|ClkHalf_inferred_clock 100.0 MHz 54.3 MHz 10.000 18.413 -8.413 inferred Inferred_clkgroup_0 IGLOO_TOP|Clk 25.0 MHz 28.4 MHz 40.000 35.260 4.740 declared default_clkgroup ===================================================================================================================================== Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise ----------------------------------------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ----------------------------------------------------------------------------------------------------------------------------------------------------- IGLOO_TOP|Clk IGLOO_TOP|Clk | 40.000 4.740 | No paths - | No paths - | No paths - IGLOO_TOP|Clk HV2201|ClkHalf_inferred_clock | Diff grp - | No paths - | No paths - | No paths - HV2201|ClkHalf_inferred_clock IGLOO_TOP|Clk | Diff grp - | No paths - | No paths - | No paths - HV2201|ClkHalf_inferred_clock HV2201|ClkHalf_inferred_clock | 10.000 -8.413 | No paths - | No paths - | No paths - ===================================================================================================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: HV2201|ClkHalf_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------------------------------------------- MySwitchControl.MyHV2201.SPIMACHINE_STATE[9] HV2201|ClkHalf_inferred_clock DFN1C0 Q SPIMACHINE_STATE[9] 1.771 -8.413 MySwitchControl.MyHV2201.SPIMACHINE_STATE[7] HV2201|ClkHalf_inferred_clock DFN1C0 Q SPIMACHINE_STATE[7] 1.771 -8.242 MySwitchControl.MyHV2201.SPIMACHINE_STATE[10] HV2201|ClkHalf_inferred_clock DFN1C0 Q SPIMACHINE_STATE[10] 1.771 -7.808 MySwitchControl.MyHV2201.SPIMACHINE_STATE[13] HV2201|ClkHalf_inferred_clock DFN1C0 Q SPIMACHINE_STATE[13] 1.771 -7.678 MySwitchControl.MyHV2201.SPIMACHINE_STATE[8] HV2201|ClkHalf_inferred_clock DFN1C0 Q SPIMACHINE_STATE[8] 1.771 -7.678 MySwitchControl.MyHV2201.SPIMACHINE_STATE[5] HV2201|ClkHalf_inferred_clock DFN1C0 Q SPIMACHINE_STATE[5] 1.771 -7.394 MySwitchControl.MyHV2201.SPIMACHINE_STATE[11] HV2201|ClkHalf_inferred_clock DFN1C0 Q SPIMACHINE_STATE[11] 1.771 -7.394 MySwitchControl.MyHV2201.SPIMACHINE_STATE[15] HV2201|ClkHalf_inferred_clock DFN1C0 Q SPIMACHINE_STATE[15] 1.771 -7.394 MySwitchControl.MyHV2201.SPIMACHINE_STATE[6] HV2201|ClkHalf_inferred_clock DFN1C0 Q SPIMACHINE_STATE[6] 1.771 -7.039 MySwitchControl.MyHV2201.SPIMACHINE_STATE[12] HV2201|ClkHalf_inferred_clock DFN1C0 Q SPIMACHINE_STATE[12] 1.771 -7.039 ================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------------------------------------- MySwitchControl.MyHV2201.SPIMACHINE_STATE[21] HV2201|ClkHalf_inferred_clock DFN1C0 D SPIMACHINE_STATE_ns[1] 8.705 -8.413 MySwitchControl.MyHV2201.SW_DIN[3] HV2201|ClkHalf_inferred_clock DFN1C0 D SW_DIN_10[3] 8.622 -8.284 MySwitchControl.MyHV2201.SW_DIN[4] HV2201|ClkHalf_inferred_clock DFN1C0 D SW_DIN_10[4] 8.622 -8.284 MySwitchControl.MyHV2201.SW_DIN[0] HV2201|ClkHalf_inferred_clock DFN1C0 D SW_DIN_10[0] 8.622 -8.242 MySwitchControl.MyHV2201.SW_DIN[1] HV2201|ClkHalf_inferred_clock DFN1C0 D SW_DIN_10[1] 8.622 -8.242 MySwitchControl.MyHV2201.SW_DIN[5] HV2201|ClkHalf_inferred_clock DFN1C0 D SW_DIN_10[5] 8.622 -8.242 MySwitchControl.MyHV2201.SW_DIN[6] HV2201|ClkHalf_inferred_clock DFN1C0 D SW_DIN_10[6] 8.622 -8.242 MySwitchControl.MyHV2201.SW_DIN[7] HV2201|ClkHalf_inferred_clock DFN1C0 D SW_DIN_10[7] 8.622 -8.242 MySwitchControl.MyHV2201.SW_DIN[2] HV2201|ClkHalf_inferred_clock DFN1C0 D SW_DIN_10[2] 8.622 -7.448 MySwitchControl.MyHV2201.SW_CLK_1[0] HV2201|ClkHalf_inferred_clock DFN1C0 D SW_CLK_1_RNO[0] 8.622 -4.483 ===================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 1.295 + Clock delay at ending point: 0.000 (ideal) = Required time: 8.705 - Propagation time: 17.119 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -8.413 Number of logic level(s): 4 Starting point: MySwitchControl.MyHV2201.SPIMACHINE_STATE[9] / Q Ending point: MySwitchControl.MyHV2201.SPIMACHINE_STATE[21] / D The start point is clocked by HV2201|ClkHalf_inferred_clock [rising] on pin CLK The end point is clocked by HV2201|ClkHalf_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------------------- MySwitchControl.MyHV2201.SPIMACHINE_STATE[9] DFN1C0 Q Out 1.771 1.771 - SPIMACHINE_STATE[9] Net - - 3.938 - 8 MySwitchControl.MyHV2201.SPIMACHINE_STATE_RNI8566[10] NOR2 B In - 5.709 - MySwitchControl.MyHV2201.SPIMACHINE_STATE_RNI8566[10] NOR2 Y Out 1.554 7.263 - N_241 Net - - 2.844 - 4 MySwitchControl.MyHV2201.SPIMACHINE_STATE_RNO_5[21] NOR3A A In - 10.107 - MySwitchControl.MyHV2201.SPIMACHINE_STATE_RNO_5[21] NOR3A Y Out 1.595 11.702 - SPIMACHINE_STATE_ns_a2_3[1] Net - - 0.773 - 1 MySwitchControl.MyHV2201.SPIMACHINE_STATE_RNO_2[21] NOR3B B In - 12.475 - MySwitchControl.MyHV2201.SPIMACHINE_STATE_RNO_2[21] NOR3B Y Out 1.499 13.974 - SPIMACHINE_STATE_ns_a2_9[1] Net - - 0.773 - 1 MySwitchControl.MyHV2201.SPIMACHINE_STATE_RNO[21] NOR3C C In - 14.746 - MySwitchControl.MyHV2201.SPIMACHINE_STATE_RNO[21] NOR3C Y Out 1.599 16.346 - SPIMACHINE_STATE_ns[1] Net - - 0.773 - 1 MySwitchControl.MyHV2201.SPIMACHINE_STATE[21] DFN1C0 D In - 17.119 - ====================================================================================================================== Total path delay (propagation time + setup) of 18.413 is 9.313(50.6%) logic and 9.100(49.4%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 2: Requested Period: 10.000 - Setup time: 1.378 + Clock delay at ending point: 0.000 (ideal) = Required time: 8.622 - Propagation time: 16.906 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -8.284 Number of logic level(s): 4 Starting point: MySwitchControl.MyHV2201.SPIMACHINE_STATE[9] / Q Ending point: MySwitchControl.MyHV2201.SW_DIN[4] / D The start point is clocked by HV2201|ClkHalf_inferred_clock [rising] on pin CLK The end point is clocked by HV2201|ClkHalf_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------------------------------- MySwitchControl.MyHV2201.SPIMACHINE_STATE[9] DFN1C0 Q Out 1.771 1.771 - SPIMACHINE_STATE[9] Net - - 3.938 - 8 MySwitchControl.MyHV2201.SPIMACHINE_STATE_RNI8566[10] NOR2 B In - 5.709 - MySwitchControl.MyHV2201.SPIMACHINE_STATE_RNI8566[10] NOR2 Y Out 1.554 7.263 - N_241 Net - - 2.844 - 4 MySwitchControl.MyHV2201.MyShiftFSM\.SW_DIN_10_iv_1[4] AO1A A In - 10.107 - MySwitchControl.MyHV2201.MyShiftFSM\.SW_DIN_10_iv_1[4] AO1A Y Out 0.873 10.980 - SW_DIN_10_iv_1[4] Net - - 0.773 - 1 MySwitchControl.MyHV2201.MyShiftFSM\.SW_DIN_10_iv_4[4] OR3 C In - 11.752 - MySwitchControl.MyHV2201.MyShiftFSM\.SW_DIN_10_iv_4[4] OR3 Y Out 1.804 13.556 - SW_DIN_10_iv_4[4] Net - - 0.773 - 1 MySwitchControl.MyHV2201.MyShiftFSM\.SW_DIN_10_iv[4] OR3 C In - 14.329 - MySwitchControl.MyHV2201.MyShiftFSM\.SW_DIN_10_iv[4] OR3 Y Out 1.804 16.133 - SW_DIN_10[4] Net - - 0.773 - 1 MySwitchControl.MyHV2201.SW_DIN[4] DFN1C0 D In - 16.906 - ======================================================================================================================= Total path delay (propagation time + setup) of 18.284 is 9.183(50.2%) logic and 9.100(49.8%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 3: Requested Period: 10.000 - Setup time: 1.378 + Clock delay at ending point: 0.000 (ideal) = Required time: 8.622 - Propagation time: 16.906 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -8.284 Number of logic level(s): 4 Starting point: MySwitchControl.MyHV2201.SPIMACHINE_STATE[9] / Q Ending point: MySwitchControl.MyHV2201.SW_DIN[3] / D The start point is clocked by HV2201|ClkHalf_inferred_clock [rising] on pin CLK The end point is clocked by HV2201|ClkHalf_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------------------------------- MySwitchControl.MyHV2201.SPIMACHINE_STATE[9] DFN1C0 Q Out 1.771 1.771 - SPIMACHINE_STATE[9] Net - - 3.938 - 8 MySwitchControl.MyHV2201.SPIMACHINE_STATE_RNI8566[10] NOR2 B In - 5.709 - MySwitchControl.MyHV2201.SPIMACHINE_STATE_RNI8566[10] NOR2 Y Out 1.554 7.263 - N_241 Net - - 2.844 - 4 MySwitchControl.MyHV2201.MyShiftFSM\.SW_DIN_10_iv_1[3] AO1A A In - 10.107 - MySwitchControl.MyHV2201.MyShiftFSM\.SW_DIN_10_iv_1[3] AO1A Y Out 0.873 10.980 - SW_DIN_10_iv_1[3] Net - - 0.773 - 1 MySwitchControl.MyHV2201.MyShiftFSM\.SW_DIN_10_iv_4[3] OR3 C In - 11.752 - MySwitchControl.MyHV2201.MyShiftFSM\.SW_DIN_10_iv_4[3] OR3 Y Out 1.804 13.556 - SW_DIN_10_iv_4[3] Net - - 0.773 - 1 MySwitchControl.MyHV2201.MyShiftFSM\.SW_DIN_10_iv[3] OR3 C In - 14.329 - MySwitchControl.MyHV2201.MyShiftFSM\.SW_DIN_10_iv[3] OR3 Y Out 1.804 16.133 - SW_DIN_10[3] Net - - 0.773 - 1 MySwitchControl.MyHV2201.SW_DIN[3] DFN1C0 D In - 16.906 - ======================================================================================================================= Total path delay (propagation time + setup) of 18.284 is 9.183(50.2%) logic and 9.100(49.8%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 4: Requested Period: 10.000 - Setup time: 1.378 + Clock delay at ending point: 0.000 (ideal) = Required time: 8.622 - Propagation time: 16.864 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -8.242 Number of logic level(s): 4 Starting point: MySwitchControl.MyHV2201.SPIMACHINE_STATE[7] / Q Ending point: MySwitchControl.MyHV2201.SW_DIN[0] / D The start point is clocked by HV2201|ClkHalf_inferred_clock [rising] on pin CLK The end point is clocked by HV2201|ClkHalf_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------------------------------- MySwitchControl.MyHV2201.SPIMACHINE_STATE[7] DFN1C0 Q Out 1.771 1.771 - SPIMACHINE_STATE[7] Net - - 3.074 - 5 MySwitchControl.MyHV2201.SPIMACHINE_STATE_RNITDNA[8] NOR2 B In - 4.845 - MySwitchControl.MyHV2201.SPIMACHINE_STATE_RNITDNA[8] NOR2 Y Out 1.554 6.398 - N_242 Net - - 3.667 - 7 MySwitchControl.MyHV2201.MyShiftFSM\.SW_DIN_10_iv_0[0] AO1A A In - 10.065 - MySwitchControl.MyHV2201.MyShiftFSM\.SW_DIN_10_iv_0[0] AO1A Y Out 0.873 10.938 - SW_DIN_10_iv_0[0] Net - - 0.773 - 1 MySwitchControl.MyHV2201.MyShiftFSM\.SW_DIN_10_iv_4[0] OR3 C In - 11.710 - MySwitchControl.MyHV2201.MyShiftFSM\.SW_DIN_10_iv_4[0] OR3 Y Out 1.804 13.514 - SW_DIN_10_iv_4[0] Net - - 0.773 - 1 MySwitchControl.MyHV2201.MyShiftFSM\.SW_DIN_10_iv[0] OR3 C In - 14.287 - MySwitchControl.MyHV2201.MyShiftFSM\.SW_DIN_10_iv[0] OR3 Y Out 1.804 16.091 - SW_DIN_10[0] Net - - 0.773 - 1 MySwitchControl.MyHV2201.SW_DIN[0] DFN1C0 D In - 16.864 - ======================================================================================================================= Total path delay (propagation time + setup) of 18.242 is 9.183(50.3%) logic and 9.058(49.7%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 5: Requested Period: 10.000 - Setup time: 1.378 + Clock delay at ending point: 0.000 (ideal) = Required time: 8.622 - Propagation time: 16.864 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -8.242 Number of logic level(s): 4 Starting point: MySwitchControl.MyHV2201.SPIMACHINE_STATE[7] / Q Ending point: MySwitchControl.MyHV2201.SW_DIN[1] / D The start point is clocked by HV2201|ClkHalf_inferred_clock [rising] on pin CLK The end point is clocked by HV2201|ClkHalf_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------------------------------- MySwitchControl.MyHV2201.SPIMACHINE_STATE[7] DFN1C0 Q Out 1.771 1.771 - SPIMACHINE_STATE[7] Net - - 3.074 - 5 MySwitchControl.MyHV2201.SPIMACHINE_STATE_RNITDNA[8] NOR2 B In - 4.845 - MySwitchControl.MyHV2201.SPIMACHINE_STATE_RNITDNA[8] NOR2 Y Out 1.554 6.398 - N_242 Net - - 3.667 - 7 MySwitchControl.MyHV2201.MyShiftFSM\.SW_DIN_10_iv_0[1] AO1A A In - 10.065 - MySwitchControl.MyHV2201.MyShiftFSM\.SW_DIN_10_iv_0[1] AO1A Y Out 0.873 10.938 - SW_DIN_10_iv_0[1] Net - - 0.773 - 1 MySwitchControl.MyHV2201.MyShiftFSM\.SW_DIN_10_iv_4[1] OR3 C In - 11.710 - MySwitchControl.MyHV2201.MyShiftFSM\.SW_DIN_10_iv_4[1] OR3 Y Out 1.804 13.514 - SW_DIN_10_iv_4[1] Net - - 0.773 - 1 MySwitchControl.MyHV2201.MyShiftFSM\.SW_DIN_10_iv[1] OR3 C In - 14.287 - MySwitchControl.MyHV2201.MyShiftFSM\.SW_DIN_10_iv[1] OR3 Y Out 1.804 16.091 - SW_DIN_10[1] Net - - 0.773 - 1 MySwitchControl.MyHV2201.SW_DIN[1] DFN1C0 D In - 16.864 - ======================================================================================================================= Total path delay (propagation time + setup) of 18.242 is 9.183(50.3%) logic and 9.058(49.7%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: IGLOO_TOP|Clk ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------ MyDAC.MyAD5360.ResetCounter[2] IGLOO_TOP|Clk DFN1C0 Q ResetCounter[2] 1.771 4.740 MyDAC.MyAD5360.ResetCounter[6] IGLOO_TOP|Clk DFN1C0 Q ResetCounter[6] 1.771 4.802 MyDAC.MyAD5360.ResetCounter[3] IGLOO_TOP|Clk DFN1C0 Q ResetCounter[3] 1.771 5.375 MyDAC.MyAD5360.ResetCounter[5] IGLOO_TOP|Clk DFN1C0 Q ResetCounter[5] 1.771 5.420 MyDAC.MyAD5360.ResetCounter[4] IGLOO_TOP|Clk DFN1C0 Q ResetCounter[4] 1.771 5.646 MyDAC.MyAD5360.ResetCounter[0] IGLOO_TOP|Clk DFN1C0 Q ResetCounter[0] 1.771 5.684 MyDAC.MyAD5360.ResetCounter[1] IGLOO_TOP|Clk DFN1C0 Q ResetCounter[1] 1.771 5.688 MyDAC.MyPackageDis.INPUT_READEN_INTERNAL IGLOO_TOP|Clk DFN1C0 Q INPUT_READEN_INTERNAL 1.771 6.811 MyInputParser.DATA_IN_READENABLE_INTERNAL IGLOO_TOP|Clk DFN1C0 Q DATA_IN_READENABLE_INTERNAL 1.771 7.128 MyDAC.MyPackageDis.SPIMACHINE_STATE[2] IGLOO_TOP|Clk DFN1C0 Q SPIMACHINE_STATE[2] 1.771 7.183 ==================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------------------------------------------- MyDAC.MyAD5360.ResetCounter[39] IGLOO_TOP|Clk DFN1C0 D N_99 38.622 4.740 MyDAC.MyAD5360.ResetCounter[36] IGLOO_TOP|Clk DFN1C0 D N_92 38.622 5.045 MyDAC.MyAD5360.ResetCounter[38] IGLOO_TOP|Clk DFN1C0 D N_96 38.622 6.753 MyDAC.MyPackageDis.SPIMACHINE_STATE[0] IGLOO_TOP|Clk DFN1C0 D SPIMACHINE_STATE_0_RNI0AS8U[1] 38.705 6.811 MyDAC.MyPackageDis.SPIMACHINE_STATE_0[0] IGLOO_TOP|Clk DFN1C0 D SPIMACHINE_STATE_0_RNI0AS8U[1] 38.705 6.811 MyDAC.MyAD5360.ResetCounter[21] IGLOO_TOP|Clk DFN1C0 D N_20 38.622 6.827 MyDAC.MyAD5360.ResetCounter[37] IGLOO_TOP|Clk DFN1C0 D N_94 38.622 6.907 MyDAC.MyAD5360.ResetCounter[35] IGLOO_TOP|Clk DFN1C0 D N_90 38.622 7.053 MyInputParser.COUNTER[7] IGLOO_TOP|Clk DFN1C0 D COUNTER_6[7] 38.705 7.128 MyDAC.MyAD5360.ResetCounter[29] IGLOO_TOP|Clk DFN1C0 D N_54 38.622 7.128 ======================================================================================================================================= Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 40.000 - Setup time: 1.378 + Clock delay at ending point: 0.000 (ideal) = Required time: 38.622 - Propagation time: 33.882 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 4.740 Number of logic level(s): 8 Starting point: MyDAC.MyAD5360.ResetCounter[2] / Q Ending point: MyDAC.MyAD5360.ResetCounter[39] / D The start point is clocked by IGLOO_TOP|Clk [rising] on pin CLK The end point is clocked by IGLOO_TOP|Clk [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------------------------- MyDAC.MyAD5360.ResetCounter[2] DFN1C0 Q Out 1.771 1.771 - ResetCounter[2] Net - - 3.938 - 8 MyDAC.MyAD5360.ResetCounter_RNID33E1[1] NOR3C C In - 5.709 - MyDAC.MyAD5360.ResetCounter_RNID33E1[1] NOR3C Y Out 1.541 7.250 - ResetCounter_m2_0_a2_2 Net - - 0.773 - 1 MyDAC.MyAD5360.ResetCounter_RNINBIB3[1] NOR3B A In - 8.023 - MyDAC.MyAD5360.ResetCounter_RNINBIB3[1] NOR3B Y Out 1.541 9.564 - ResetCounter_N_5_mux_0_0 Net - - 3.074 - 5 MyDAC.MyAD5360.ResetCounter_RNI2GRR6[10] NOR3C C In - 12.637 - MyDAC.MyAD5360.ResetCounter_RNI2GRR6[10] NOR3C Y Out 1.541 14.178 - ResetCounter_N_13_mux_0 Net - - 3.667 - 7 MyDAC.MyAD5360.ResetCounter_m1_0_a2_2_5_RNI6AO29 NOR2B B In - 17.845 - MyDAC.MyAD5360.ResetCounter_m1_0_a2_2_5_RNI6AO29 NOR2B Y Out 1.508 19.353 - ResetCounter_N_13_mux Net - - 3.420 - 6 MyDAC.MyAD5360.ResetCounter_m5_0_a2_6_RNI3JGI9 NOR2B B In - 22.773 - MyDAC.MyAD5360.ResetCounter_m5_0_a2_6_RNI3JGI9 NOR2B Y Out 1.508 24.281 - ResetCounter_N_11_mux_1 Net - - 2.844 - 4 MyDAC.MyAD5360.ResetCounter_RNIT1TUA[34] NOR3C C In - 27.125 - MyDAC.MyAD5360.ResetCounter_RNIT1TUA[34] NOR3C Y Out 1.541 28.666 - ResetCounter_N_3_mux Net - - 0.927 - 2 MyDAC.MyAD5360.ResetCounter_RNO_0[39] OR2B A In - 29.593 - MyDAC.MyAD5360.ResetCounter_RNO_0[39] OR2B Y Out 1.236 30.829 - N_251 Net - - 0.773 - 1 MyDAC.MyAD5360.ResetCounter_RNO[39] XA1C B In - 31.602 - MyDAC.MyAD5360.ResetCounter_RNO[39] XA1C Y Out 1.508 33.109 - N_99 Net - - 0.773 - 1 MyDAC.MyAD5360.ResetCounter[39] DFN1C0 D In - 33.882 - ================================================================================================================= Total path delay (propagation time + setup) of 35.260 is 15.072(42.7%) logic and 20.188(57.3%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] Timing exceptions that could not be applied None Finished final timing analysis (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:13s; Memory used current: 147MB peak: 150MB) Finished timing report (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:13s; Memory used current: 147MB peak: 150MB) -------------------------------------------------------------------------------- Target Part: AGLN250V2_VQFP100_STD Report for cell IGLOO_TOP.igloo_top_arch Core Cell usage: cell count area count*area AND2 10 1.0 10.0 AO1 135 1.0 135.0 AO1A 71 1.0 71.0 AO1B 7 1.0 7.0 AO1C 2 1.0 2.0 AO1D 2 1.0 2.0 AOI1 8 1.0 8.0 AOI1B 2 1.0 2.0 AX1 2 1.0 2.0 AX1C 2 1.0 2.0 AXO7 2 1.0 2.0 AXOI1 1 1.0 1.0 AXOI4 1 1.0 1.0 AXOI5 1 1.0 1.0 CLKINT 4 0.0 0.0 GND 11 0.0 0.0 INV 12 1.0 12.0 MX2 38 1.0 38.0 MX2A 13 1.0 13.0 MX2B 1 1.0 1.0 MX2C 16 1.0 16.0 NAND2 2 1.0 2.0 NAND2A 1 1.0 1.0 NOR2 62 1.0 62.0 NOR2A 95 1.0 95.0 NOR2B 308 1.0 308.0 NOR3 12 1.0 12.0 NOR3A 72 1.0 72.0 NOR3B 64 1.0 64.0 NOR3C 80 1.0 80.0 OA1 54 1.0 54.0 OA1B 5 1.0 5.0 OA1C 12 1.0 12.0 OAI1 1 1.0 1.0 OR2 47 1.0 47.0 OR2A 32 1.0 32.0 OR2B 17 1.0 17.0 OR3 185 1.0 185.0 OR3A 7 1.0 7.0 OR3B 6 1.0 6.0 OR3C 4 1.0 4.0 VCC 11 0.0 0.0 XA1 2 1.0 2.0 XA1A 1 1.0 1.0 XA1B 16 1.0 16.0 XA1C 19 1.0 19.0 XNOR2 5 1.0 5.0 XO1 42 1.0 42.0 XO1A 1 1.0 1.0 XOR2 94 1.0 94.0 DFI1E1 1 1.0 1.0 DFN1C0 210 1.0 210.0 DFN1E0C0 112 1.0 112.0 DFN1E1 9 1.0 9.0 DFN1E1C0 910 1.0 910.0 DFN1P0 13 1.0 13.0 FIFO4K18 3 0.0 0.0 ----- ---------- TOTAL 2856 2827.0 IO Cell usage: cell count CLKBUF 2 INBUF 12 OUTBUF 41 ----- TOTAL 55 Core Cells : 2827 of 6144 (46%) IO Cells : 55 RAM/ROM Usage Summary Block Rams : 3 of 8 (37%) Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:14s; CPU Time elapsed 0h:00m:13s; Memory used current: 33MB peak: 150MB) Process took 0h:00m:14s realtime, 0h:00m:13s cputime # Fri Apr 07 12:05:22 2017 ###########################################################]