Project Settings
Project Name IGLOO_TOP_syn Implementation Name synthesis
Top Module work.IGLOO_TOP Retiming 0
Resource Sharing 1 Fanout Guide 24
Disable I/O Insertion 0 Disable Sequential Optimizations 0

Run Status
Job Name Status CPU Time Real Time Memory Date/Time
(compiler)Complete 168 16 0 - 00m:01s - 07/04/2017
12:05:04
(premap)Complete 6 2 0 0m:02s 0m:02s 120MB 07/04/2017
12:05:08
(fpga_mapper)Complete 18 3 0 0m:13s 0m:14s 150MB 07/04/2017
12:05:22
Multi-srs Generator Complete07/04/2017
12:05:05

Area Summary
Core Cells 2827 IO Cells 55
Block RAMs (v_ram) 3

Timing Summary
Clock NameReq FreqEst FreqSlack
HV2201|ClkHalf_inferred_clock100.0 MHz54.3 MHz-8.413
IGLOO_TOP|Clk25.0 MHz28.4 MHz4.740

Optimizations Summary
Combined Clock Conversion 1 / 1