library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;

use work.real_vector_pkg.all;  -- Import the real_vector and real_matrix definitions

entity tb_dptc_basic is
end entity;

architecture Behavioral_basic of tb_dptc_basic is

  -- Constants
  constant Nv : integer := 2;  -- Rows
  constant Nh : integer := 2;  -- Columns
  constant N  : integer := 4;  -- Vector size inside each DDot

  -- DUT Signals
  signal clk           : std_logic := '0';
  signal reset_n       : std_logic := '0';
  signal enable        : std_logic := '0';
  signal out_valid     : std_logic;
  signal x_matrix      : my_real_matrix(0 to Nv-1, 0 to N-1);
  signal y_matrix      : my_real_matrix(0 to Nh-1, 0 to N-1);
  signal result_matrix : real_matrix(0 to Nv-1, 0 to Nh-1);

  -- Clock period
  constant clk_period : time := 10 ns;

begin

  -- Instantiate DUT
  uut: entity work.dptc
    generic map (
      Nv => Nv,
      Nh => Nh,
      N  => N
    )
    port map (
      clk           => clk,
      reset_n       => reset_n,
      enable        => enable,
      x_matrix      => x_matrix,
      y_matrix      => y_matrix,
      out_valid     => out_valid,
      result_matrix => result_matrix
    );

  -- Clock generation
  clk_process : process
  begin
    clk <= '0';
    wait for clk_period/2;
    clk <= '1';
    wait for clk_period/2;
  end process;

  -- Stimulus process
  stim_proc: process
  begin
    -- Reset the system
    reset_n <= '0';
    enable <= '0';
    wait for 20 ns;
    reset_n <= '1';
    wait for clk_period;

    -- Apply test inputs
    -- X Matrix (2x4)
    x_matrix(0,0) <= 1.0; x_matrix(0,1) <= 2.0; x_matrix(0,2) <= 3.0; x_matrix(0,3) <= 4.0;
    x_matrix(1,0) <= 5.0; x_matrix(1,1) <= 6.0; x_matrix(1,2) <= 7.0; x_matrix(1,3) <= 8.0;

    -- Y Matrix (2x4)
    y_matrix(0,0) <= 1.0; y_matrix(0,1) <= 0.0; y_matrix(0,2) <= 1.0; y_matrix(0,3) <= 0.0;
    y_matrix(1,0) <= 0.0; y_matrix(1,1) <= 1.0; y_matrix(1,2) <= 0.0; y_matrix(1,3) <= 1.0;

    -- Enable operation
    wait for clk_period;
    enable <= '1';
    
    wait until rising_edge(clk) and out_valid = '1';  -- Wait for computation to complete
    enable <= '0';

    -- Wait to observe outputs
    wait for 50 ns;

    -- Report the result
    report "Result Matrix (After Multiplication): ";
    report "Row 0, Col 0: " & real'image(result_matrix(0,0));
    report "Row 0, Col 1: " & real'image(result_matrix(0,1));
    report "Row 1, Col 0: " & real'image(result_matrix(1,0));
    report "Row 1, Col 1: " & real'image(result_matrix(1,1));
    --new input
    wait for 50 ns;

    -- Apply test inputs
    -- X Matrix (2x4)
    x_matrix(0,0) <= 2.0; x_matrix(0,1) <= 4.0; x_matrix(0,2) <= 1.0; x_matrix(0,3) <= 1.0;
    x_matrix(1,0) <= 4.0; x_matrix(1,1) <= 3.0; x_matrix(1,2) <= 4.0; x_matrix(1,3) <= 3.0;

    -- Y Matrix (2x4)
    y_matrix(0,0) <= 0.0; y_matrix(0,1) <= 1.0; y_matrix(0,2) <= 2.0; y_matrix(0,3) <= 3.0;
    y_matrix(1,0) <= 1.0; y_matrix(1,1) <= 1.0; y_matrix(1,2) <= 1.0; y_matrix(1,3) <= 0.0;

    -- Enable operation
    wait for clk_period;
    enable <= '1';
  
    wait until rising_edge(clk) and out_valid = '1';  -- Wait for computation to complete
    enable <= '0';

    -- Wait to observe outputs
    wait for 50 ns;

    -- Report the result
    report "Result Matrix (After Multiplication): ";
    report "Row 0, Col 0: " & real'image(result_matrix(0,0));
    report "Row 0, Col 1: " & real'image(result_matrix(0,1));
    report "Row 1, Col 0: " & real'image(result_matrix(1,0));
    report "Row 1, Col 1: " & real'image(result_matrix(1,1));
    -- 3rd input
    wait for 50 ns;
    x_matrix(0,0) <= 1.0; x_matrix(0,1) <= 2.0; x_matrix(0,2) <= 5.0; x_matrix(0,3) <= 6.0;
    x_matrix(1,0) <= 3.0; x_matrix(1,1) <= 3.0; x_matrix(1,2) <= 7.0; x_matrix(1,3) <= 2.0;

    -- Y Matrix (2x4)
    y_matrix(0,0) <= 1.0; y_matrix(0,1) <= 4.0; y_matrix(0,2) <= 1.0; y_matrix(0,3) <= 0.0;
    y_matrix(1,0) <= 2.0; y_matrix(1,1) <= 3.0; y_matrix(1,2) <= 1.0; y_matrix(1,3) <= 1.0;

    -- Enable operation
    wait for clk_period;
    enable <= '1';
    
    wait until rising_edge(clk) and out_valid = '1';  -- Wait for computation to complete
    enable <= '0';

    -- Wait to observe outputs
    wait for 50 ns;

    -- Report the result
    report "Result Matrix (After Multiplication): ";
    report "Row 0, Col 0: " & real'image(result_matrix(0,0));
    report "Row 0, Col 1: " & real'image(result_matrix(0,1));
    report "Row 1, Col 0: " & real'image(result_matrix(1,0));
    report "Row 1, Col 1: " & real'image(result_matrix(1,1));
    wait; -- End of simulation
  end process;

end architecture;