library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;

use work.real_vector_pkg.all;


entity tb_ddot_unit is
end tb_ddot_unit;

architecture Behavioral of tb_ddot_unit is
  -- Parameters
  constant N : integer := 4; -- must match DDOT generic

  -- DUT signals
  signal clk     : std_logic := '0';
  signal reset_n : std_logic := '0';
  signal enable  : std_logic := '0';
  signal out_valid : std_logic;
  signal x_vec   : my_real_vector(0 to N-1);
  signal y_vec   : my_real_vector(0 to N-1);
  signal dot_out : real;

  -- Clock period
  constant clk_period : time := 10 ns;
begin

  -- Instantiate the DUT
  uut: entity work.ddot_unit
    generic map (
      N => N
    )
    port map (
      clk     => clk,
      reset_n => reset_n,
      enable => enable,
      x_vec   => x_vec,
      y_vec   => y_vec,
      out_valid => out_valid,
      dot_out => dot_out
    );

  -- Clock generation
  clk_process : process
  begin
    clk <= '0';
    wait for clk_period/2;
    clk <= '1';
    wait for clk_period/2;
  end process;

  -- Stimulus process
  stim_proc: process
  begin
    -- Reset
    reset_n <= '0';
    enable <= '0';
    wait for 20 ns;
    reset_n <= '1';
    wait for 10 ns;--

    -- Apply first test vector
    x_vec(0) <= 1.0; y_vec(0) <= 2.0;
    x_vec(1) <= 3.0; y_vec(1) <= 4.0;
    x_vec(2) <= 5.0; y_vec(2) <= 6.0;
    x_vec(3) <= 7.0; y_vec(3) <= 8.0;
    wait for clk_period;--
    enable <= '1';

    wait until rising_edge(clk) and out_valid = '1';
    --wait for 10 ns;
    enable <= '0';

    -- Wait and observe output
    wait for 50 ns;

    -- Apply second test vector
    x_vec(0) <= 2.0; y_vec(0) <= 3.0;
    x_vec(1) <= 4.0; y_vec(1) <= 5.0;
    x_vec(2) <= 6.0; y_vec(2) <= 7.0;
    x_vec(3) <= 8.0; y_vec(3) <= 9.0;
    wait for clk_period;

    enable <= '1';
    wait until rising_edge(clk) and out_valid = '1';
    --wait for 10 ns;
    enable <= '0';
    -- Wait and observe output
    wait for 50 ns;

    -- Finish simulation
    wait;
  end process;

end architecture;