67 lines
2.2 KiB
VHDL
67 lines
2.2 KiB
VHDL
library ieee;
|
|
use ieee.std_logic_1164.all;
|
|
use ieee.numeric_std.all;
|
|
use ieee.math_real.all; -- for floating point operations
|
|
|
|
use work.real_vector_pkg.all;
|
|
|
|
entity ddot_unit is --stands for double-precision dot product unit
|
|
generic (
|
|
N : integer := 2 -- number of vector elements (default 2 for a 2x2 matrix)
|
|
);
|
|
port (
|
|
clk : in std_logic;
|
|
reset_n : in std_logic; -- Active-low reset
|
|
enable : in std_logic; -- Control signal to trigger dot product calculation
|
|
x_vec : in my_real_vector(0 to N-1); -- input row vector x
|
|
y_vec : in my_real_vector(0 to N-1); -- input column vector y as transposed for ease of calculation
|
|
out_valid : out std_logic; -- Output signal indicating result validity
|
|
dot_out : out my_real -- output: dot product
|
|
);
|
|
end entity;
|
|
|
|
architecture Behavioral of ddot_unit is
|
|
begin
|
|
|
|
process(clk, reset_n)
|
|
-- Variables used for combinational operations within process
|
|
variable partial_products : my_real_vector(0 to N-1); --Stores individual multiplication results of vector elements.
|
|
variable temp_sum : my_real; --Accumulates the total dot product
|
|
variable temp_valid : std_logic; -- Temporarily holds the validity flag for the output
|
|
begin
|
|
if reset_n = '0' then
|
|
dot_out <= ZERO_REAL;
|
|
out_valid <= '0';
|
|
|
|
-- Also reset variables to known state (important for simulation correctness)
|
|
partial_products := (others => ZERO_REAL);
|
|
temp_sum := ZERO_REAL;
|
|
temp_valid := '0';
|
|
|
|
elsif rising_edge(clk) then
|
|
if enable = '1' then
|
|
-- Step 1: Multiply corresponding elements
|
|
for i in 0 to N-1 loop
|
|
partial_products(i) := x_vec(i) * y_vec(i);
|
|
end loop;
|
|
|
|
-- Step 2: Sum up all the partial products
|
|
temp_sum := ZERO_REAL;
|
|
for i in 0 to N-1 loop
|
|
temp_sum := temp_sum + partial_products(i);
|
|
end loop;
|
|
|
|
temp_valid := '1';
|
|
|
|
-- Output assignments after processing
|
|
dot_out <= temp_sum;
|
|
out_valid <= temp_valid;
|
|
else
|
|
-- Disable case: reset valid output
|
|
out_valid <= '0';
|
|
end if;
|
|
end if;
|
|
end process;
|
|
|
|
end architecture;
|
|
|