149 lines
3.5 KiB
VHDL
149 lines
3.5 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use std.textio.all;
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use work.real_vector_pkg.all;
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--use work.tile_array_pkg.all;
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entity tile_array_tb is
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end tile_array_tb;
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architecture Behavioral of tile_array_tb is
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-- Constants
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constant Np : integer := 4;
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constant Nm : integer := 4;
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constant Nq : integer := 4;
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constant Nt : integer := 2;
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constant Nd : integer := 2;
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constant Nh : integer := 2;
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constant N : integer := 2;
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constant clk_period : time := 10 ns;
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-- Signals
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signal clk : std_logic := '0';
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signal reset_n : std_logic := '0';
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signal enable : std_logic := '0';
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signal m1 : my_real_matrix(0 to Np-1, 0 to Nm-1);
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signal m2 : my_real_matrix(0 to Nq-1, 0 to Nm-1);
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signal result_valid : std_logic;
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signal result : real_matrix(0 to Np-1, 0 to Nq-1);
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begin
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-- Clock generation
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clk_process : process
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begin
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while true loop
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clk <= '0';
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wait for clk_period / 2;
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clk <= '1';
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wait for clk_period / 2;
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end loop;
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end process;
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-- DUT instantiation
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uut: entity work.tile_array
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generic map (
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Np => Np, Nm => Nm, Nq => Nq, Nt => Nt,
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Nd => Nd, Nh => Nh, N => N
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)
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port map (
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clk => clk,
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reset_n => reset_n,
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enable => enable,
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m1 => m1,
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m2 => m2,
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result_valid => result_valid,
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result => result
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);
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-- Stimulus process
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stim_proc: process
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variable i, j : integer;
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variable L : line;
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file out_file : text open write_mode is "tile_array_out.txt"; --n
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file m1_file : text open write_mode is "m1.txt"; --n
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file m2_file : text open write_mode is "m2.txt"; --n
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begin
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-- Reset and initialize
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reset_n <= '0';
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wait for 2 * clk_period;
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reset_n <= '1';
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wait for clk_period;
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-- Initialize M1 matrix (values 1 to 16)
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for i in 0 to Np-1 loop
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for j in 0 to Nm-1 loop
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m1(i, j) <= real(i * Nm + j + 1);
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end loop;
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end loop;
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wait for clk_period;
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-- Write M1 to file
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for i in 0 to Np-1 loop
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L := null;
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for j in 0 to Nm-1 loop
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write(L, m1(i,j), right, 0, 6);
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write(L, string'(" "));
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end loop;
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writeline(m1_file, L);
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end loop;
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-- Initialize M2 matrix (row i: 10*(i+1) + j + 1)
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for i in 0 to Nq-1 loop
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for j in 0 to Nm-1 loop
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m2(i, j) <= real((i + 1) * 5 + j + 1);
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end loop;
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end loop;
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wait for clk_period;
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-- Write M2 to file
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for i in 0 to Nq-1 loop
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L := null;
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for j in 0 to Nm-1 loop
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write(L, m2(i,j), right, 0, 6);
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write(L, string'(" "));
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end loop;
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writeline(m2_file, L);
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end loop;
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wait for clk_period * 2;
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enable <= '1';
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wait until rising_edge(result_valid);
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enable <= '0';
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wait for clk_period;
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-- Print final result
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write(L, string'("===== FINAL RESULT ===== at time " & time'image(now)));
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writeline(out_file, L);
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for i in 0 to Np-1 loop
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L := null;
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for j in 0 to Nq-1 loop
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write(L, result(i,j), right, 0, 6);
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write(L, string'(" "));
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end loop;
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writeline(out_file, L);
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end loop;
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report "Matrix multiplication result is valid.";
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-- Detailed reporting
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for i in 0 to Np-1 loop
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for j in 0 to Nq-1 loop
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report "Result(" & integer'image(i) & "," & integer'image(j) & ") = " &
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real'image(result(i, j));
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end loop;
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end loop;
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wait;
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end process;
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end Behavioral;
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