109 lines
2.3 KiB
VHDL
109 lines
2.3 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.math_real.all;
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use work.real_vector_pkg.all; -- for my_real_matrix, real_matrix
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entity tile_unit_tb is
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end;
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architecture sim of tile_unit_tb is
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-- Constants matching the DUT generics
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constant Nv : integer := 2;
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constant Nh : integer := 2;
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constant Nm : integer := 4;
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constant Nd : integer := 2;
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constant N : integer := 2;
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-- Clock period
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constant clk_period : time := 10 ns;
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-- DUT signals
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signal clk : std_logic := '0';
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signal reset_n : std_logic := '0';
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signal enable : std_logic := '0';
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signal m1_chunk : my_real_matrix(0 to Nv-1, 0 to Nm-1);
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signal m2_chunk : my_real_matrix(0 to Nh-1, 0 to Nm-1);
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signal out_valid : std_logic;
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signal result_out : real_matrix(0 to Nv-1, 0 to Nh-1);
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begin
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-- Clock generation
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clk_process : process
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begin
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while now < 500 ns loop
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clk <= '0';
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wait for clk_period / 2;
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clk <= '1';
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wait for clk_period / 2;
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end loop;
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wait;
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end process;
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-- DUT instantiation
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uut: entity work.tile_unit
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generic map (
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N => N,
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Nv => Nv,
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Nh => Nh,
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Nm => Nm,
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Nd => Nd
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)
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port map (
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clk => clk,
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reset_n => reset_n,
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enable => enable,
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m1_chunk => m1_chunk,
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m2_chunk => m2_chunk,
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out_valid => out_valid,
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result_out => result_out
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);
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-- Stimulus
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stim_proc: process
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begin
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-- Reset sequence
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reset_n <= '0';
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enable <= '0';
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wait for 2 * clk_period;
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reset_n <= '1';
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-- Load test data
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wait for clk_period;
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-- Example:
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-- m1_chunk = identity 2x4
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-- m2_chunk = 2x4 row-wise [1 2 3 4], [5 6 7 8]
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for i in 0 to Nv-1 loop
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for j in 0 to Nm-1 loop
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if i = j then
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m1_chunk(i, j) <= 2.0;
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else
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m1_chunk(i, j) <= 1.0;
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end if;
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end loop;
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end loop;
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for i in 0 to Nh-1 loop
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for j in 0 to Nm-1 loop
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m2_chunk(i, j) <= real(i * Nm + j + 1); -- row major fill
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end loop;
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end loop;
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-- Start computation
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enable <= '1';
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wait for 2 * clk_period;
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enable <= '0';
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-- Wait for valid
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wait until out_valid = '1';
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report "Matrix multiplication result is valid.";
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wait;
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end process;
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end architecture;
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