fix: bugs resolved

router.vhdl

@@ -22,8 +22,8 @@ generic (
 port (
     clk             :   in std_logic;
     rstN            :   in std_logic;
-    buffers_in      :   in t_PORT_IN(num_paths_up+num_paths_down*4-1 downto 0);
-    buffers_out     :   out t_PORT_OUT(num_paths_up+num_paths_down*4-1 downto 0)
+    buffers_in      :   inout t_PORT_IN(num_paths_up+num_paths_down*4-1 downto 0);
+    buffers_out     :   inout t_PORT_OUT(num_paths_up+num_paths_down*4-1 downto 0)
 );
 end router;
 
@@ -34,41 +34,11 @@ architecture impl of router is
     signal chip_r_y              :   std_logic_vector(CHIP_ADDR_SIZE-1 downto 0);
     signal core_r_x              :   std_logic_vector(DEST_ADDR_SIZE-level-1 downto 0);
     signal core_r_y              :   std_logic_vector(DEST_ADDR_SIZE-level-1 downto 0);
-    signal rd_data, rd_data_nxt  :   t_DATA(TOT_NUM_PATHS);
-    signal rd_data_valid         :   t_DATA_VAL(TOT_NUM_PATHS);
-    signal avai_paths            :   t_PATHS(TOT_NUM_PATHS);
+    signal rd_data, rd_data_nxt  :   t_DATA(TOT_NUM_PATHS downto 0);
+    signal rd_data_valid         :   t_DATA_VAL(TOT_NUM_PATHS downto 0);
+    signal avai_paths            :   t_PATHS(TOT_NUM_PATHS downto 0);
     signal out_buff_if           :   t_PORT_IN(TOT_NUM_PATHS-1 downto 0);
 
-    procedure arbitration (
-        signal rd_data        :   in t_DATA(TOT_NUM_PATHS);
-        signal rd_data_valid  :   in t_DATA_VAL(TOT_NUM_PATHS);
-        signal chip_r_x       :   in std_logic_vector(CHIP_ADDR_SIZE-1 downto 0);
-        signal chip_r_y       :   in std_logic_vector(CHIP_ADDR_SIZE-1 downto 0);
-        signal core_r_x       :   in std_logic_vector(DEST_ADDR_SIZE-level-1 downto 0);
-        signal core_r_y       :   in std_logic_vector(DEST_ADDR_SIZE-level-1 downto 0);
-        signal avai_paths     :   in t_PATHS(TOT_NUM_PATHS)
-    ) is
-        variable rout_dirs              :   t_DATA_DIRS(TOT_NUM_PATHS);
-        variable avai_pos               :   t_AVAI_POS(TOT_NUM_PATHS);
-        variable path_index, out_index  :   integer;
-    begin
-        routing(level, rd_data, rd_data_valid, chip_r_x, chip_r_y, core_r_x, 
-                core_r_y, avai_paths, num_paths_up, num_paths_down, rout_dirs,
-                avai_pos);
-        -- sending data
-        for j in 0 to NUM_DIRS loop
-            path_index := 0;
-            for i in 0 to TOT_NUM_PATHS-1 loop
-                if rd_data_valid(i)='1' and rout_dirs(i)(j)='1' then
-                    out_index  := retrieve_avai_path_index(j, path_index, 
-                                    num_paths_up, num_paths_down, avai_pos);
-                    path_index := path_index + 1;
-                    out_buff_if(out_index).data_in <= rd_data(i);
-                    out_buff_if(i).req <= '1';
-                end if;
-            end loop;
-        end loop;
-    end procedure;
 begin
     -- implements all buffers for each path
     g_IN_BUFF_GEN: for i in 0 to TOT_NUM_PATHS-1 generate
@@ -96,22 +66,20 @@ begin
         variable dir      :  positive;
     begin
         for i in 0 to TOT_NUM_PATHS-1 loop
-            if out_buff_if(i).full'event then
-                if i < num_paths_up then
-                    avai_paths(i)(0) <= not out_buff_if(i).full;
-                elsif i < num_paths_up + num_paths_down then
-                    ds_ind := i - num_paths_up;
-                    avai_paths(i)(1) <= not out_buff_if(i).full;
-                elsif i < num_paths_up + num_paths_down*2 then
-                    ds_ind := i - num_paths_up - num_paths_down;
-                    avai_paths(i)(2) <= not out_buff_if(i).full;
-                elsif i < num_paths_up + num_paths_down*3 then
-                    ds_ind := i - num_paths_up - num_paths_down*2;
-                    avai_paths(i)(3) <= not out_buff_if(i).full;
-                else
-                    ds_ind := i - num_paths_up - num_paths_down*3;
-                    avai_paths(i)(4) <= not out_buff_if(i).full;
-                end if;
+            if i < num_paths_up then
+                avai_paths(i)(0) <= not out_buff_if(i).full;
+            elsif i < num_paths_up + num_paths_down then
+                ds_ind := i - num_paths_up;
+                avai_paths(i)(1) <= not out_buff_if(i).full;
+            elsif i < num_paths_up + num_paths_down*2 then
+                ds_ind := i - num_paths_up - num_paths_down;
+                avai_paths(i)(2) <= not out_buff_if(i).full;
+            elsif i < num_paths_up + num_paths_down*3 then
+                ds_ind := i - num_paths_up - num_paths_down*2;
+                avai_paths(i)(3) <= not out_buff_if(i).full;
+            else
+                ds_ind := i - num_paths_up - num_paths_down*3;
+                avai_paths(i)(4) <= not out_buff_if(i).full;
             end if;
         end loop;
     end process;
@@ -119,13 +87,16 @@ begin
     end_wr_req: process(out_buff_if)
     begin
         for i in 0 to TOT_NUM_PATHS-1 loop
-            if out_buff_if(i).ack'event and out_buff_if(i).ack = '1' then
+            if out_buff_if(i).ack = '1' then
                 out_buff_if(i).req <= '0';
             end if;
         end loop;
     end process;
 
     switching: process(rstN, clk)
+        variable rout_dirs   :   t_DATA_DIRS(tot_num_paths-1 downto 0);
+        variable avai_pos    :   t_AVAI_POS(tot_num_paths-1 downto 0);
+        variable path_index, out_index  :   integer;
     begin
         if rstN = '0' then
             rd_data        <= (others => (others => '0'));
@@ -140,8 +111,22 @@ begin
                                 val_core_r_y, core_r_y'length));
         elsif rising_edge(clk) then
             rd_data     <= rd_data_nxt;
-            arbitration(rd_data, rd_data_valid, chip_r_x, chip_r_y, core_r_x,
-                            core_r_y, avai_paths);
+            routing(level, rd_data, rd_data_valid, chip_r_x, chip_r_y, core_r_x, 
+                    core_r_y, avai_paths, num_paths_up, num_paths_down, rout_dirs,
+                    avai_pos);
+            -- sending data
+            for j in 0 to NUM_DIRS loop
+                path_index := 0;
+                for i in 0 to TOT_NUM_PATHS-1 loop
+                    if rd_data_valid(i)='1' and rout_dirs(i)(j)='1' then
+                        out_index  := retrieve_avai_path_index(j, path_index, 
+                                        num_paths_up, num_paths_down, avai_pos);
+                        path_index := path_index + 1;
+                        out_buff_if(out_index).data_in <= rd_data(i);
+                        out_buff_if(i).req <= '1';
+                    end if;
+                end loop;
+            end loop;
         end if;
     end process;
 end impl;

router_types.vhdl

@@ -47,11 +47,6 @@ package router_types is
     type t_DATA_VAL     is array (integer range <>) of std_logic;
     type t_DATA_DIRS    is array (integer range <>) of
                             std_logic_vector(NUM_DIRS-1 downto 0);
-
-    --type t_pos_and_index is record
-    --    avai_pos        :  t_avai_positions;
-    --    path_ind        :  integer;
-    --end record;
 end package;
 
 package body router_types is

routing_functions.vhdl

@@ -57,6 +57,14 @@ package routing_functions is
         num_ds_paths    : in positive;
         avai_pos        : in t_AVAI_POS
     ) return integer;
+
+    --function set_out_buffer (
+    --    num_paths_up, num_paths_down    :   in integer;
+    --    rd_data                         :   in t_DATA;
+    --    rd_data_valid                   :   in t_DATA_VAL;
+    --    rout_dirs                       :   in t_DATA_DIRS;
+    --    avai_pos                        :   in t_AVAI_POS
+    --) return t_PORT_IN;
 end package;
 
 package body routing_functions is
@@ -248,28 +256,6 @@ package body routing_functions is
     end loop;
     end procedure;
 
-    procedure routing (
-        level           : in positive;
-        read_data       : in t_DATA;
-        read_data_valid : in t_DATA_VAL;
-        chip_r_x        : in std_logic_vector(CHIP_ADDR_SIZE-1 downto 0);
-        chip_r_y        : in std_logic_vector(CHIP_ADDR_SIZE-1 downto 0);
-        core_r_x        : in std_logic_vector;
-        core_r_y        : in std_logic_vector;
-        paths           : in t_PATHS;
-        num_us_paths    : in positive;
-        num_ds_paths    : in positive;
-        rout_dirs       : inout t_DATA_DIRS;
-        avai_pos        : out t_AVAI_POS
-    ) is
-    begin
-        rout_dir_determination(level, read_data, 
-                        read_data_valid, chip_r_x, chip_r_y,
-                        core_r_x, core_r_y, rout_dirs);
-        rout_path_determination(read_data, read_data_valid, rout_dirs, paths, 
-                        num_us_paths, num_ds_paths, avai_pos);
-    end routing;
-
     function retrieve_avai_path_index (
         dir             : in positive;
         path_index      : in integer;
@@ -295,4 +281,56 @@ package body routing_functions is
             return to_integer(unsigned(avai_pos(avai_pos_index)));
         end if;
     end retrieve_avai_path_index;
+
+    --function set_out_buffer (
+    --    num_paths_up, num_paths_down    :   in integer;
+    --    rd_data                         :   in t_DATA;
+    --    rd_data_valid                   :   in t_DATA_VAL;
+    --    rout_dirs                       :   in t_DATA_DIRS;
+    --    avai_pos                        :   in t_AVAI_POS
+    --) return t_PORT_IN
+    --is
+    --    variable out_buff_if                           :   t_PORT_IN;
+    --    variable path_index, out_index, tot_num_paths  :   integer;
+    --begin
+    --    tot_num_paths := num_paths_up+num_paths_down*4;
+    --    for i in 0 to tot_num_paths-1 loop
+    --        out_buff_if(i).data_in := (others => '0');
+    --        out_buff_if(i).req := '0';
+    --    end loop;
+    --    for j in 0 to NUM_DIRS loop
+    --        path_index := 0;
+    --        for i in 0 to tot_num_paths-1 loop
+    --            if rd_data_valid(i)='1' and rout_dirs(i)(j)='1' then
+    --                out_index  := retrieve_avai_path_index(j, path_index, 
+    --                                num_paths_up, num_paths_down, avai_pos);
+    --                path_index := path_index + 1;
+    --                out_buff_if(out_index).data_in := rd_data(i);
+    --                out_buff_if(i).req := '1';
+    --            end if;
+    --        end loop;
+    --    end loop;
+    --end set_out_buffer;
+
+    procedure routing (
+        level           : in positive;
+        read_data       : in t_DATA;
+        read_data_valid : in t_DATA_VAL;
+        chip_r_x        : in std_logic_vector(CHIP_ADDR_SIZE-1 downto 0);
+        chip_r_y        : in std_logic_vector(CHIP_ADDR_SIZE-1 downto 0);
+        core_r_x        : in std_logic_vector;
+        core_r_y        : in std_logic_vector;
+        paths           : in t_PATHS;
+        num_us_paths    : in positive;
+        num_ds_paths    : in positive;
+        rout_dirs       : inout t_DATA_DIRS;
+        avai_pos        : out t_AVAI_POS
+    ) is
+    begin
+        rout_dir_determination(level, read_data, 
+                        read_data_valid, chip_r_x, chip_r_y,
+                        core_r_x, core_r_y, rout_dirs);
+        rout_path_determination(read_data, read_data_valid, rout_dirs, paths, 
+                        num_us_paths, num_ds_paths, avai_pos);
+    end routing;
 end package body;