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compare: jneyra:4b33acdae6eefbaa268fcbb30c5a63b7e5c5a626
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Author SHA1 Message Date
Retrocamara42
4b33acdae6 fix: synchronization issues, random test passed successfully 2025-06-17 04:10:29 -05:00
Retrocamara42
d62a06976b fix: header with 1 replaced by valid_data signal, generate_test_files now have repetitions 2025-06-15 09:19:39 -05:00
21 changed files with 113281 additions and 25402 deletions
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3
Readme.md
View file

@ -39,5 +39,4 @@ FIFO5 -> U -> Upstream
![alt text](./drawings/router.png)
# TODO: delete line where header is compared to 1
# TODO: do throttle (many same data points) testw
# TODO: run simulation again, observing router L5
# TODO: do throttle (many same data points) testw

29
router/arbiter.vhdl
View file

@ -14,6 +14,7 @@ port (
clk, arstN : in std_logic;
rout_pos : in t_pos_addr;
packets : in t_DATA(num_paths_up+num_paths_down*4-1 downto 0);
valid_data : in std_logic_vector(num_paths_up+num_paths_down*4-1 downto 0);
avai_paths : in std_logic_vector(num_paths_up+num_paths_down*4-1 downto 0);
arb_complete : out std_logic_vector(num_paths_up+num_paths_down*4-1 downto 0);
buff_wr_in : out t_FIFO_WR_INS(num_paths_up+num_paths_down*4-1 downto 0)
@ -25,17 +26,16 @@ architecture impl of arbiter is
signal dirs : t_DATA_DIRS(TOT_NUM_PATHS-1 downto 0) := (others => (others => '0'));
signal ps_dirs : t_DATA_DIRS(TOT_NUM_PATHS-1 downto 0) := (others => (others => '0'));
signal avai_pos_nxt : t_AVAI_POS(TOT_NUM_PATHS-1 downto 0);
signal avai_pos : t_AVAI_POS(TOT_NUM_PATHS-1 downto 0);
begin
get_rout_dir: process(rout_pos, packets)
get_rout_dir: process(rout_pos, valid_data, packets)
variable pack_dest : t_pos_addr;
variable header : std_logic_vector(3 downto 0);
--variable header : std_logic_vector(3 downto 0);
variable is_upstream : boolean;
begin
for i in 0 to packets'length-1 loop
header := packets(i)(63 downto 60);
if header(0) = '1' then
if valid_data(i) = '1' then
--header := packets(i)(63 downto 60);
pack_dest.chip_x := packets(i)(59 downto 55);
pack_dest.chip_y := packets(i)(54 downto 50);
pack_dest.core_x := packets(i)(49 downto 45);
@ -64,31 +64,31 @@ begin
if i < num_paths_down then
if avai_path = '1' then
avai_index := avai_pos_sizes(0);
avai_pos_nxt(avai_index) <= i;
avai_pos(avai_index) <= i;
avai_pos_sizes(0) := avai_pos_sizes(0) + 1;
end if;
elsif i < num_paths_down*2 then
if avai_path = '1' then
avai_index := avai_pos_sizes(1) + num_paths_down;
avai_pos_nxt(avai_index) <= i;
avai_pos(avai_index) <= i;
avai_pos_sizes(1) := avai_pos_sizes(1) + 1;
end if;
elsif i < num_paths_down*3 then
if avai_path = '1' then
avai_index := avai_pos_sizes(2) + num_paths_down*2;
avai_pos_nxt(avai_index) <= i;
avai_pos(avai_index) <= i;
avai_pos_sizes(2) := avai_pos_sizes(2) + 1;
end if;
elsif i < num_paths_down*4 then
if avai_path = '1' then
avai_index := avai_pos_sizes(3) + num_paths_down*3;
avai_pos_nxt(avai_index) <= i;
avai_pos(avai_index) <= i;
avai_pos_sizes(3) := avai_pos_sizes(3) + 1;
end if;
else
if avai_path = '1' then
avai_index := avai_pos_sizes(4) + num_paths_down*4;
avai_pos_nxt(avai_index) <= i;
avai_pos(avai_index) <= i;
avai_pos_sizes(4) := avai_pos_sizes(4) + 1;
end if;
end if;
@ -195,13 +195,4 @@ begin
end loop;
end loop;
end process;
update_regs: process(clk, arstN)
begin
if arstN = '0' then
avai_pos <= (others => 0);
elsif rising_edge(clk) then
avai_pos <= avai_pos_nxt;
end if;
end process;
end impl;

29
router/fifo.vhdl
View file

@ -23,8 +23,8 @@ type T_FIFO is array (0 to DEPTH-1) of std_logic_vector(WIDTH-1 downto 0);
signal wr_ptr, rd_ptr : unsigned(F_PTR_SIZE-1 downto 0);
signal wr_ptr_nxt, rd_ptr_nxt : unsigned(F_PTR_SIZE-1 downto 0);
signal full_nxt, empty_nxt : std_logic;
signal data_out_nxt : std_logic_vector(WIDTH-1 downto 0);
signal s_full, s_empty : std_logic;
signal fifo, fifo_nxt : T_FIFO;
signal fifo_sel : std_logic_vector(DEPTH-1 downto 0);
@ -35,33 +35,29 @@ begin
wr_ptr <= (others => '0');
rd_ptr <= (others => '0');
fifo <= (others => (others => '0'));
full <= '0';
empty <= '1';
data_out <= (others => '0');
elsif clk'event and clk='1' then
fifo <= fifo_nxt;
wr_ptr <= wr_ptr_nxt;
rd_ptr <= rd_ptr_nxt;
full <= full_nxt;
empty <= empty_nxt;
data_out <= data_out_nxt;
end if;
end process;
update_wr_ptr: process(wr_req, full_nxt, wr_ptr)
update_wr_ptr: process(wr_req, s_full, wr_ptr)
begin
if wr_req = '1' and full_nxt = '0' then
if wr_req = '1' and s_full = '0' then
wr_ptr_nxt <= wr_ptr + 1;
else
wr_ptr_nxt <= wr_ptr;
end if;
end process;
select_fifo_for_writing: process(wr_req, wr_ptr)
select_fifo_for_writing: process(wr_req, s_full, wr_ptr)
variable one : unsigned(DEPTH-1 downto 0);
begin
fifo_sel <= (others => '0');
if wr_req = '1' then
if wr_req = '1' and s_full = '0' then
one := to_unsigned(1, DEPTH);
fifo_sel <= std_logic_vector(shift_left(one, to_integer(wr_ptr(F_PTR_SIZE-2 downto 0))));
end if;
@ -78,9 +74,9 @@ begin
end loop;
end process write;
update_rd_ptr: process(rd_req, empty_nxt, rd_ptr)
update_rd_ptr: process(rd_req, s_empty, rd_ptr)
begin
if rd_req = '1' and empty_nxt = '0' then
if rd_req = '1' and s_empty = '0' then
rd_ptr_nxt <= rd_ptr + 1;
else
rd_ptr_nxt <= rd_ptr;
@ -96,18 +92,21 @@ begin
begin
if rd_ptr(F_PTR_SIZE-2 downto 0) = wr_ptr(F_PTR_SIZE-2 downto 0) and
rd_ptr(F_PTR_SIZE-1) /= wr_ptr(F_PTR_SIZE-1) then
full_nxt <= '1';
s_full <= '1';
else
full_nxt <= '0';
s_full <= '0';
end if;
end process;
determine_empty_flag: process(rd_ptr, wr_ptr)
begin
if rd_ptr = wr_ptr then
empty_nxt <= '1';
s_empty <= '1';
else
empty_nxt <= '0';
s_empty <= '0';
end if;
end process;
full <= s_full;
empty <= s_empty;
end impl;

35
router/parent_arbiter.vhdl
View file

@ -14,6 +14,7 @@ port (
clk, arstN : in std_logic;
rout_pos : in t_pos_addr;
packets : in t_DATA(num_paths_up*4+num_paths_down*4-1 downto 0);
valid_data : in std_logic_vector(num_paths_up*4+num_paths_down*4-1 downto 0);
avai_paths : in std_logic_vector(num_paths_up*4+num_paths_down*4-1 downto 0);
arb_complete : out std_logic_vector(num_paths_up*4+num_paths_down*4-1 downto 0);
buff_wr_in : out t_FIFO_WR_INS(num_paths_up*4+num_paths_down*4-1 downto 0)
@ -25,16 +26,15 @@ architecture impl of parent_arbiter is
signal dirs : t_DATA_DIRS_EXT(TOT_NUM_PATHS-1 downto 0) := (others => (others => '0'));
signal ps_dirs : t_DATA_DIRS_EXT(TOT_NUM_PATHS-1 downto 0) := (others => (others => '0'));
signal avai_pos_nxt : t_EX_AVAI_POS(TOT_NUM_PATHS-1 downto 0);
signal avai_pos : t_EX_AVAI_POS(TOT_NUM_PATHS-1 downto 0);
begin
L5_get_rout_dir: process(rout_pos, packets)
L5_get_rout_dir: process(rout_pos, valid_data, packets)
variable pack_dest : t_pos_addr;
variable header : std_logic_vector(3 downto 0);
--variable header : std_logic_vector(3 downto 0);
begin
for i in 0 to packets'length-1 loop
header := packets(i)(63 downto 60);
if header(0) = '1' then
if valid_data(i) = '1' then
--header := packets(i)(63 downto 60);
pack_dest.chip_x := packets(i)(59 downto 55);
pack_dest.chip_y := packets(i)(54 downto 50);
pack_dest.core_x := packets(i)(49 downto 45);
@ -63,49 +63,49 @@ begin
if i < num_paths_down then
if avai_path = '1' then
avai_index := avai_pos_sizes(0);
avai_pos_nxt(avai_index) <= i;
avai_pos(avai_index) <= i;
avai_pos_sizes(0) := avai_pos_sizes(0) + 1;
end if;
elsif i < num_paths_down*2 then
if avai_path = '1' then
avai_index := avai_pos_sizes(1) + num_paths_down;
avai_pos_nxt(avai_index) <= i;
avai_pos(avai_index) <= i;
avai_pos_sizes(1) := avai_pos_sizes(1) + 1;
end if;
elsif i < num_paths_down*3 then
if avai_path = '1' then
avai_index := avai_pos_sizes(2) + num_paths_down*2;
avai_pos_nxt(avai_index) <= i;
avai_pos(avai_index) <= i;
avai_pos_sizes(2) := avai_pos_sizes(2) + 1;
end if;
elsif i < num_paths_down*4 then
if avai_path = '1' then
avai_index := avai_pos_sizes(3) + num_paths_down*3;
avai_pos_nxt(avai_index) <= i;
avai_pos(avai_index) <= i;
avai_pos_sizes(3) := avai_pos_sizes(3) + 1;
end if;
elsif i < num_paths_down*4 + num_paths_up then
if avai_path = '1' then
avai_index := avai_pos_sizes(4) + num_paths_down*4;
avai_pos_nxt(avai_index) <= i;
avai_pos(avai_index) <= i;
avai_pos_sizes(4) := avai_pos_sizes(4) + 1;
end if;
elsif i < num_paths_down*4 + num_paths_up*2 then
if avai_path = '1' then
avai_index := avai_pos_sizes(5)+num_paths_down*4+num_paths_up;
avai_pos_nxt(avai_index) <= i;
avai_pos(avai_index) <= i;
avai_pos_sizes(5) := avai_pos_sizes(5) + 1;
end if;
elsif i < num_paths_down*4 + num_paths_up*3 then
if avai_path = '1' then
avai_index:=avai_pos_sizes(6)+num_paths_down*4+num_paths_up*2;
avai_pos_nxt(avai_index) <= i;
avai_pos(avai_index) <= i;
avai_pos_sizes(6) := avai_pos_sizes(6) + 1;
end if;
else
if avai_path = '1' then
avai_index:=avai_pos_sizes(7)+num_paths_down*4+num_paths_up*3;
avai_pos_nxt(avai_index) <= i;
avai_pos(avai_index) <= i;
avai_pos_sizes(7) := avai_pos_sizes(7) + 1;
end if;
end if;
@ -218,13 +218,4 @@ begin
end loop;
end loop;
end process;
update_regs: process(clk, arstN)
begin
if arstN = '0' then
avai_pos <= (others => 0);
elsif rising_edge(clk) then
avai_pos <= avai_pos_nxt;
end if;
end process;
end impl;

72
router/parent_router.vhdl
View file

@ -42,14 +42,19 @@ architecture impl of parent_router is
signal snd_buff_rd_in : std_logic_vector(TOT_NUM_PATHS-1 downto 0);
signal rcv_accept_ack : std_logic_vector(TOT_NUM_PATHS-1 downto 0);
signal rd_data, rd_data_nxt : t_DATA(TOT_NUM_PATHS-1 downto 0);
signal valid_data_nxt : std_logic_vector(TOT_NUM_PATHS-1 downto 0);
signal valid_data : std_logic_vector(TOT_NUM_PATHS-1 downto 0);
signal req_flag : std_logic_vector(TOT_NUM_PATHS-1 downto 0);
signal rcv_data : t_DATA(TOT_NUM_PATHS-1 downto 0);
signal rd_reqs : std_logic_vector(TOT_NUM_PATHS-1 downto 0);
signal continue_send : std_logic_vector(TOT_NUM_PATHS-1 downto 0);
signal avai_paths : std_logic_vector(TOT_NUM_PATHS-1 downto 0);
signal arb_complete : std_logic_vector(TOT_NUM_PATHS-1 downto 0);
signal out_buff_rd_reqs : std_logic_vector(TOT_NUM_PATHS-1 downto 0);
signal packet_states : t_PACKET_STATES(TOT_NUM_PATHS-1 downto 0);
signal packet_states_nxt : t_PACKET_STATES(TOT_NUM_PATHS-1 downto 0);
signal outb_rd_states : t_OUT_BUFF_RD_STATES(TOT_NUM_PATHS-1 downto 0);
signal outb_rd_states_nxt : t_OUT_BUFF_RD_STATES(TOT_NUM_PATHS-1 downto 0);
begin
g_IN_BUFF_GEN: for i in 0 to TOT_NUM_PATHS-1 generate
input_fifo: fifo
@ -66,7 +71,7 @@ begin
generic map(WIDTH => buffer_width, DEPTH => buffer_depth,
F_PTR_SIZE => fifo_ptr_size)
port map(arstN => arstN, clk => clk, wr_req => snd_buff_wr_in(i).wr_req,
rd_req => snd_buff_rd_in(i), data_in => snd_buff_wr_in(i).data,
rd_req => out_buff_rd_reqs(i), data_in => snd_buff_wr_in(i).data,
data_out => snd_buff_out(i).data,
full => snd_buff_out(i).full, empty => snd_buff_out(i).empty);
end generate;
@ -119,6 +124,7 @@ begin
arstN => arstN,
rout_pos => rout_pos,
packets => rd_data,
valid_data => valid_data,
avai_paths => avai_paths,
arb_complete => arb_complete,
buff_wr_in => snd_buff_wr_in
@ -135,7 +141,57 @@ begin
begin
for i in 0 to TOT_NUM_PATHS-1 loop
avai_paths(i) <= not snd_buff_out(i).full;
continue_send(i) <= not snd_buff_out(i).empty;
end loop;
end process;
read_out_buff_sm_next_logic: process(outb_rd_states, snd_buff_out, snd_buff_rd_in)
begin
for i in 0 to TOT_NUM_PATHS-1 loop
case outb_rd_states(i) is
when EmptyFifo =>
if snd_buff_out(i).empty = '0' then
outb_rd_states_nxt(i) <= StartRead;
else
outb_rd_states_nxt(i) <= EmptyFifo;
end if;
when StartRead =>
if snd_buff_out(i).empty = '1' then
outb_rd_states_nxt(i) <= EmptyFifo;
else
outb_rd_states_nxt(i) <= WaitForSender;
end if;
--when Sending =>
-- outb_rd_states_nxt(i) <= WaitForSender;
when WaitForSender =>
if snd_buff_rd_in(i) = '1' then
if snd_buff_out(i).empty = '1' then
outb_rd_states_nxt(i) <= EmptyFifo;
else
outb_rd_states_nxt(i) <= StartRead;
end if;
else
outb_rd_states_nxt(i) <= WaitForSender;
end if;
when others =>
outb_rd_states_nxt(i) <= EmptyFifo;
end case;
end loop;
end process;
read_out_buff_sm_out_gen: process(outb_rd_states)
begin
for i in 0 to TOT_NUM_PATHS-1 loop
case outb_rd_states(i) is
when StartRead =>
continue_send(i) <= '1';
out_buff_rd_reqs(i) <= '1';
--when Sending =>
-- continue_send(i) <= '1';
-- out_buff_rd_reqs(i) <= '0';
when others =>
continue_send(i) <= '0';
out_buff_rd_reqs(i) <= '0';
end case;
end loop;
end process;
@ -165,7 +221,7 @@ begin
end loop;
end process;
packet_sm_out_gen: process(packet_states, rcv_buff_out, arb_complete)
packet_sm_out_gen: process(packet_states, rcv_buff_out, arb_complete, rd_data)
begin
for i in 0 to TOT_NUM_PATHS-1 loop
case packet_states(i) is
@ -176,15 +232,19 @@ begin
rd_reqs(i) <= '0';
end if;
rd_data_nxt(i) <= (others => '0');
valid_data_nxt(i) <= '0';
when Arbitration =>
rd_reqs(i) <= '0';
rd_data_nxt(i) <= rcv_buff_out(i).data; -- first time read from buffer
valid_data_nxt(i) <= '1';
when others =>
rd_reqs(i) <= '0';
if arb_complete(i) = '1' then
rd_data_nxt(i) <= (others => '0');
valid_data_nxt(i) <= '0';
else
rd_data_nxt(i) <= rd_data(i);
valid_data_nxt(i) <= '1';
end if;
end case;
end loop;
@ -202,8 +262,10 @@ begin
packet_states <= (others => Idle);
rd_data <= (others => (others => '0'));
elsif rising_edge(clk) then
packet_states <= packet_states_nxt;
rd_data <= rd_data_nxt;
packet_states <= packet_states_nxt;
rd_data <= rd_data_nxt;
valid_data <= valid_data_nxt;
outb_rd_states <= outb_rd_states_nxt;
end if;
end process;
end impl;

83
router/router.vhdl
View file

@ -40,14 +40,19 @@ architecture impl of router is
signal snd_buff_rd_in : std_logic_vector(num_paths_up+num_paths_down*4-1 downto 0);
signal rcv_accept_ack : std_logic_vector(num_paths_up+num_paths_down*4-1 downto 0);
signal rd_data, rd_data_nxt : t_DATA(TOT_NUM_PATHS-1 downto 0);
signal valid_data_nxt : std_logic_vector(TOT_NUM_PATHS-1 downto 0);
signal valid_data : std_logic_vector(TOT_NUM_PATHS-1 downto 0);
signal req_flag : std_logic_vector(TOT_NUM_PATHS-1 downto 0);
signal rcv_data : t_DATA(TOT_NUM_PATHS-1 downto 0);
signal rd_reqs : std_logic_vector(TOT_NUM_PATHS-1 downto 0);
signal continue_send : std_logic_vector(TOT_NUM_PATHS-1 downto 0);
signal avai_paths : std_logic_vector(TOT_NUM_PATHS-1 downto 0);
signal arb_complete : std_logic_vector(TOT_NUM_PATHS-1 downto 0);
signal out_buff_rd_reqs : std_logic_vector(TOT_NUM_PATHS-1 downto 0);
signal packet_states : t_PACKET_STATES(TOT_NUM_PATHS-1 downto 0);
signal packet_states_nxt : t_PACKET_STATES(TOT_NUM_PATHS-1 downto 0);
signal outb_rd_states : t_OUT_BUFF_RD_STATES(TOT_NUM_PATHS-1 downto 0);
signal outb_rd_states_nxt : t_OUT_BUFF_RD_STATES(TOT_NUM_PATHS-1 downto 0);
begin
g_IN_BUFF_GEN: for i in 0 to TOT_NUM_PATHS-1 generate
input_fifo: fifo
@ -64,7 +69,7 @@ begin
generic map(WIDTH => buffer_width, DEPTH => buffer_depth,
F_PTR_SIZE => fifo_ptr_size)
port map(arstN => arstN, clk => clk, wr_req => snd_buff_wr_in(i).wr_req,
rd_req => snd_buff_rd_in(i), data_in => snd_buff_wr_in(i).data,
rd_req => out_buff_rd_reqs(i), data_in => snd_buff_wr_in(i).data,
data_out => snd_buff_out(i).data,
full => snd_buff_out(i).full, empty => snd_buff_out(i).empty);
end generate;
@ -96,6 +101,7 @@ begin
arstN => arstN,
rout_pos => rout_pos,
packets => rd_data,
valid_data => valid_data,
avai_paths => avai_paths,
arb_complete => arb_complete,
buff_wr_in => snd_buff_wr_in
@ -112,7 +118,57 @@ begin
begin
for i in 0 to TOT_NUM_PATHS-1 loop
avai_paths(i) <= not snd_buff_out(i).full;
continue_send(i) <= not snd_buff_out(i).empty;
end loop;
end process;
read_out_buff_sm_next_logic: process(outb_rd_states, snd_buff_out, snd_buff_rd_in)
begin
for i in 0 to TOT_NUM_PATHS-1 loop
case outb_rd_states(i) is
when EmptyFifo =>
if snd_buff_out(i).empty = '0' then
outb_rd_states_nxt(i) <= StartRead;
else
outb_rd_states_nxt(i) <= EmptyFifo;
end if;
when StartRead =>
if snd_buff_out(i).empty = '1' then
outb_rd_states_nxt(i) <= EmptyFifo;
else
outb_rd_states_nxt(i) <= WaitForSender;
end if;
--when Sending =>
-- outb_rd_states_nxt(i) <= WaitForSender;
when WaitForSender =>
if snd_buff_rd_in(i) = '1' then
if snd_buff_out(i).empty = '1' then
outb_rd_states_nxt(i) <= EmptyFifo;
else
outb_rd_states_nxt(i) <= StartRead;
end if;
else
outb_rd_states_nxt(i) <= WaitForSender;
end if;
when others =>
outb_rd_states_nxt(i) <= EmptyFifo;
end case;
end loop;
end process;
read_out_buff_sm_out_gen: process(outb_rd_states)
begin
for i in 0 to TOT_NUM_PATHS-1 loop
case outb_rd_states(i) is
when StartRead =>
continue_send(i) <= '1';
out_buff_rd_reqs(i) <= '1';
--when Sending =>
-- continue_send(i) <= '1';
-- out_buff_rd_reqs(i) <= '0';
when others =>
continue_send(i) <= '0';
out_buff_rd_reqs(i) <= '0';
end case;
end loop;
end process;
@ -152,16 +208,20 @@ begin
else
rd_reqs(i) <= '0';
end if;
rd_data_nxt(i) <= (others => '0');
rd_data_nxt(i) <= (others => '0');
valid_data_nxt(i) <= '0';
when Arbitration =>
rd_reqs(i) <= '0';
rd_data_nxt(i) <= rcv_buff_out(i).data; -- first time read from buffer
rd_reqs(i) <= '0';
rd_data_nxt(i) <= rcv_buff_out(i).data; -- first time read from buffer
valid_data_nxt(i) <= '1';
when others =>
rd_reqs(i) <= '0';
rd_reqs(i) <= '0';
if arb_complete(i) = '1' then
rd_data_nxt(i) <= (others => '0');
rd_data_nxt(i) <= (others => '0');
valid_data_nxt(i) <= '0';
else
rd_data_nxt(i) <= rd_data(i);
rd_data_nxt(i) <= rd_data(i);
valid_data_nxt(i) <= '1';
end if;
end case;
end loop;
@ -177,10 +237,13 @@ begin
rout_pos.copy_x <= (others => '-');
rout_pos.copy_y <= (others => '-');
packet_states <= (others => Idle);
outb_rd_states <= (others => EmptyFifo);
rd_data <= (others => (others => '0'));
elsif rising_edge(clk) then
packet_states <= packet_states_nxt;
rd_data <= rd_data_nxt;
packet_states <= packet_states_nxt;
rd_data <= rd_data_nxt;
valid_data <= valid_data_nxt;
outb_rd_states <= outb_rd_states_nxt;
end if;
end process;
end impl;

3
router/router_components.vhdl
View file

@ -46,6 +46,8 @@ package router_components is
clk, arstN : in std_logic;
rout_pos : in t_pos_addr;
packets : in t_DATA(num_paths_up+num_paths_down*4-1 downto 0);
valid_data : in std_logic_vector(
num_paths_up+num_paths_down*4-1 downto 0);
avai_paths : in std_logic_vector(
num_paths_up+num_paths_down*4-1 downto 0);
arb_complete : out std_logic_vector(
@ -65,6 +67,7 @@ package router_components is
clk, arstN : in std_logic;
rout_pos : in t_pos_addr;
packets : in t_DATA(num_paths_up*4+num_paths_down*4-1 downto 0);
valid_data : in std_logic_vector(num_paths_up*4+num_paths_down*4-1 downto 0);
avai_paths : in std_logic_vector(num_paths_up*4+num_paths_down*4-1 downto 0);
arb_complete : out std_logic_vector(num_paths_up*4+num_paths_down*4-1 downto 0);
buff_wr_in : out t_FIFO_WR_INS(num_paths_up*4+num_paths_down*4-1 downto 0)

4
router/router_types.vhdl
View file

@ -15,8 +15,10 @@ package router_types is
subtype WORD is std_logic_vector(63 downto 0);
subtype H_WORD is std_logic_vector(31 downto 0);
type t_PACKET_STATE is (Idle, Arbitration, InArbQueue);
type t_PACKET_STATE is (Idle, Arbitration, InArbQueue, WritingFifo);
type t_PACKET_STATES is array (integer range <>) of t_PACKET_STATE;
type t_OUT_BUFF_RD_STATE is (EmptyFifo, StartRead, Sending, WaitForSender);
type t_OUT_BUFF_RD_STATES is array (integer range <>) of t_OUT_BUFF_RD_STATE;
type t_PATHS is array (integer range <>) of
std_logic_vector(NUM_DIRS-1 downto 0);
type t_AVAI_POS is array(integer range <>) of

2
router/sender.vhdl
View file

@ -22,7 +22,7 @@ begin
when ack_edge = '1' else upd_req;
data_nxt_mux <= '1' when upd_req = '1' and continue_send = '1' else '0';
req_nxt <= not sgn_req when data_nxt_mux = '1' else sgn_req;
rd_req <= data_nxt_mux;
rd_req <= ack_edge; -- means that the data has been received
ack_edge <= ack2 xor ack3;
data_nxt <= data_in when data_nxt_mux = '1' else sgn_data;
req <= sgn_req;

19732
test/input/noc_tests/random_pe_to_pe_test/result.ref
View file

File diff suppressed because it is too large Load diff

19732
test/input/noc_tests/random_pe_to_pe_test/simulation.log
View file

File diff suppressed because it is too large Load diff

120
test/input/noc_tests/random_pe_to_pe_test/stimuli.txt
View file

@ -1,11 +1,111 @@
# is external? | path | data
0 346 0001000000000010000011000100010001000000000000000000000000000001 # origin: (11100-00011) --> dest: (10000-01100,11000-11101)
0 14 0001000000000011001011101010001001000000000000000000000000000001 # origin: (11100-11101) --> dest: (11001-01110,01101-00111)
0 459 0001000000000001100110101111111111000000000000000000000000000001 # origin: (10100-00110) --> dest: (01100-11010,01011-00010,01110-10100,11001-00001,01110-00100,00111-10001)
0 968 0001000000000001101110010000000000000000000000000000000000000001 # origin: (00101-00111) --> dest: (01101-11001)
0 535 0001000000000011101011110000000000000000000000000000000000000001 # origin: (01110-11000) --> dest: (11101-01111)
0 933 0001000000000001110010100000000000000000000000000000000000000001 # origin: (00011-01100) --> dest: (01110-01010)
0 665 0001000000000010000000001111111111000000000000000000000000000001 # origin: (00101-11010) --> dest: (10000-00000,01000-11100,10000-11000,10110-10110,10001-11011,10010-00110)
0 60 0001000000000000001000001111111111000000000000000000000000000001 # origin: (11001-11001) --> dest: (00001-00000,10111-00011,01110-01111,10000-11101)
0 798 0001000000000010110110111011111111000000000000000000000000000001 # origin: (01100-01001) --> dest: (10110-11011,10001-11110,00011-00101,10101-01110)
0 100 0001000000000011100101100000000000000000000000000000000000000001 # origin: (11011-10101) --> dest: (11100-10110)
0 946 0001000000000010010110010111000000000000000000000000000000000001 # origin: (00010-01011) --> dest: (10010-11001,11100-11001)
0 872 0001000000000001000101000111011111000000000000000000000000000010 # origin: (01001-00111) --> dest: (01000-10100,01110-10011,00100-01100)
0 997 0001000000000011101001001011111111000000000000000000000000000011 # origin: (00011-00100) --> dest: (11101-00100,01110-00001,11010-00100,11110-10011,01100-01011)
0 812 0001000000000000100000110000000000000000000000000000000000000100 # origin: (01001-01101) --> dest: (00100-00011)
0 293 0001000000000011100111110000000000000000000000000000000000000101 # origin: (11011-01100) --> dest: (11100-11111)
0 322 0001000000000001110111000000000000000000000000000000000000000110 # origin: (11110-00111) --> dest: (01110-11100)
0 253 0001000000000001110010001111111110000000000000000000000000000111 # origin: (10001-10000) --> dest: (01110-01000,01011-10110,10001-00110)
0 442 0001000000000010101000100101101101000000000000000000000000001000 # origin: (10000-01011) --> dest: (10101-00010,11110-01111)
0 222 0001000000000011001101000000000000000000000000000000000000001001 # origin: (10100-10001) --> dest: (11001-10100)
0 779 0001000000000010010100001011111101000000000000000000000000001010 # origin: (01100-01110) --> dest: (10010-10000,10010-00100,00100-01100,10101-01001,10011-01101)
0 946 0001000000000010010110010111000000000000000000000000000000001011 # origin: (00010-01011) --> dest: (10010-11001,11100-11001)
0 872 0001000000000001000101000111011111000000000000000000000000001100 # origin: (01001-00111) --> dest: (01000-10100,01110-10011,00100-01100)
0 997 0001000000000011101001001011111111000000000000000000000000001101 # origin: (00011-00100) --> dest: (11101-00100,01110-00001,11010-00100,11110-10011,01100-01011)
0 812 0001000000000000100000110000000000000000000000000000000000001110 # origin: (01001-01101) --> dest: (00100-00011)
0 293 0001000000000011100111110000000000000000000000000000000000001111 # origin: (11011-01100) --> dest: (11100-11111)
0 322 0001000000000001110111000000000000000000000000000000000000010000 # origin: (11110-00111) --> dest: (01110-11100)
0 253 0001000000000001110010001111111110000000000000000000000000010001 # origin: (10001-10000) --> dest: (01110-01000,01011-10110,10001-00110)
0 442 0001000000000010101000100101101101000000000000000000000000010010 # origin: (10000-01011) --> dest: (10101-00010,11110-01111)
0 222 0001000000000011001101000000000000000000000000000000000000010011 # origin: (10100-10001) --> dest: (11001-10100)
0 779 0001000000000010010100001011111101000000000000000000000000010100 # origin: (01100-01110) --> dest: (10010-10000,10010-00100,00100-01100,10101-01001,10011-01101)
0 946 0001000000000010010110010111000000000000000000000000000000010101 # origin: (00010-01011) --> dest: (10010-11001,11100-11001)
0 872 0001000000000001000101000111011111000000000000000000000000010110 # origin: (01001-00111) --> dest: (01000-10100,01110-10011,00100-01100)
0 997 0001000000000011101001001011111111000000000000000000000000010111 # origin: (00011-00100) --> dest: (11101-00100,01110-00001,11010-00100,11110-10011,01100-01011)
0 812 0001000000000000100000110000000000000000000000000000000000011000 # origin: (01001-01101) --> dest: (00100-00011)
0 293 0001000000000011100111110000000000000000000000000000000000011001 # origin: (11011-01100) --> dest: (11100-11111)
0 322 0001000000000001110111000000000000000000000000000000000000011010 # origin: (11110-00111) --> dest: (01110-11100)
0 253 0001000000000001110010001111111110000000000000000000000000011011 # origin: (10001-10000) --> dest: (01110-01000,01011-10110,10001-00110)
0 442 0001000000000010101000100101101101000000000000000000000000011100 # origin: (10000-01011) --> dest: (10101-00010,11110-01111)
0 222 0001000000000011001101000000000000000000000000000000000000011101 # origin: (10100-10001) --> dest: (11001-10100)
0 779 0001000000000010010100001011111101000000000000000000000000011110 # origin: (01100-01110) --> dest: (10010-10000,10010-00100,00100-01100,10101-01001,10011-01101)
0 946 0001000000000010010110010111000000000000000000000000000000011111 # origin: (00010-01011) --> dest: (10010-11001,11100-11001)
0 872 0001000000000001000101000111011111000000000000000000000000100000 # origin: (01001-00111) --> dest: (01000-10100,01110-10011,00100-01100)
0 997 0001000000000011101001001011111111000000000000000000000000100001 # origin: (00011-00100) --> dest: (11101-00100,01110-00001,11010-00100,11110-10011,01100-01011)
0 812 0001000000000000100000110000000000000000000000000000000000100010 # origin: (01001-01101) --> dest: (00100-00011)
0 293 0001000000000011100111110000000000000000000000000000000000100011 # origin: (11011-01100) --> dest: (11100-11111)
0 322 0001000000000001110111000000000000000000000000000000000000100100 # origin: (11110-00111) --> dest: (01110-11100)
0 253 0001000000000001110010001111111110000000000000000000000000100101 # origin: (10001-10000) --> dest: (01110-01000,01011-10110,10001-00110)
0 442 0001000000000010101000100101101101000000000000000000000000100110 # origin: (10000-01011) --> dest: (10101-00010,11110-01111)
0 222 0001000000000011001101000000000000000000000000000000000000100111 # origin: (10100-10001) --> dest: (11001-10100)
0 779 0001000000000010010100001011111101000000000000000000000000101000 # origin: (01100-01110) --> dest: (10010-10000,10010-00100,00100-01100,10101-01001,10011-01101)
0 946 0001000000000010010110010111000000000000000000000000000000101001 # origin: (00010-01011) --> dest: (10010-11001,11100-11001)
0 872 0001000000000001000101000111011111000000000000000000000000101010 # origin: (01001-00111) --> dest: (01000-10100,01110-10011,00100-01100)
0 997 0001000000000011101001001011111111000000000000000000000000101011 # origin: (00011-00100) --> dest: (11101-00100,01110-00001,11010-00100,11110-10011,01100-01011)
0 812 0001000000000000100000110000000000000000000000000000000000101100 # origin: (01001-01101) --> dest: (00100-00011)
0 293 0001000000000011100111110000000000000000000000000000000000101101 # origin: (11011-01100) --> dest: (11100-11111)
0 322 0001000000000001110111000000000000000000000000000000000000101110 # origin: (11110-00111) --> dest: (01110-11100)
0 253 0001000000000001110010001111111110000000000000000000000000101111 # origin: (10001-10000) --> dest: (01110-01000,01011-10110,10001-00110)
0 442 0001000000000010101000100101101101000000000000000000000000110000 # origin: (10000-01011) --> dest: (10101-00010,11110-01111)
0 222 0001000000000011001101000000000000000000000000000000000000110001 # origin: (10100-10001) --> dest: (11001-10100)
0 779 0001000000000010010100001011111101000000000000000000000000110010 # origin: (01100-01110) --> dest: (10010-10000,10010-00100,00100-01100,10101-01001,10011-01101)
0 946 0001000000000010010110010111000000000000000000000000000000110011 # origin: (00010-01011) --> dest: (10010-11001,11100-11001)
0 872 0001000000000001000101000111011111000000000000000000000000110100 # origin: (01001-00111) --> dest: (01000-10100,01110-10011,00100-01100)
0 997 0001000000000011101001001011111111000000000000000000000000110101 # origin: (00011-00100) --> dest: (11101-00100,01110-00001,11010-00100,11110-10011,01100-01011)
0 812 0001000000000000100000110000000000000000000000000000000000110110 # origin: (01001-01101) --> dest: (00100-00011)
0 293 0001000000000011100111110000000000000000000000000000000000110111 # origin: (11011-01100) --> dest: (11100-11111)
0 322 0001000000000001110111000000000000000000000000000000000000111000 # origin: (11110-00111) --> dest: (01110-11100)
0 253 0001000000000001110010001111111110000000000000000000000000111001 # origin: (10001-10000) --> dest: (01110-01000,01011-10110,10001-00110)
0 442 0001000000000010101000100101101101000000000000000000000000111010 # origin: (10000-01011) --> dest: (10101-00010,11110-01111)
0 222 0001000000000011001101000000000000000000000000000000000000111011 # origin: (10100-10001) --> dest: (11001-10100)
0 779 0001000000000010010100001011111101000000000000000000000000111100 # origin: (01100-01110) --> dest: (10010-10000,10010-00100,00100-01100,10101-01001,10011-01101)
0 946 0001000000000010010110010111000000000000000000000000000000111101 # origin: (00010-01011) --> dest: (10010-11001,11100-11001)
0 872 0001000000000001000101000111011111000000000000000000000000111110 # origin: (01001-00111) --> dest: (01000-10100,01110-10011,00100-01100)
0 997 0001000000000011101001001011111111000000000000000000000000111111 # origin: (00011-00100) --> dest: (11101-00100,01110-00001,11010-00100,11110-10011,01100-01011)
0 812 0001000000000000100000110000000000000000000000000000000001000000 # origin: (01001-01101) --> dest: (00100-00011)
0 293 0001000000000011100111110000000000000000000000000000000001000001 # origin: (11011-01100) --> dest: (11100-11111)
0 322 0001000000000001110111000000000000000000000000000000000001000010 # origin: (11110-00111) --> dest: (01110-11100)
0 253 0001000000000001110010001111111110000000000000000000000001000011 # origin: (10001-10000) --> dest: (01110-01000,01011-10110,10001-00110)
0 442 0001000000000010101000100101101101000000000000000000000001000100 # origin: (10000-01011) --> dest: (10101-00010,11110-01111)
0 222 0001000000000011001101000000000000000000000000000000000001000101 # origin: (10100-10001) --> dest: (11001-10100)
0 779 0001000000000010010100001011111101000000000000000000000001000110 # origin: (01100-01110) --> dest: (10010-10000,10010-00100,00100-01100,10101-01001,10011-01101)
0 946 0001000000000010010110010111000000000000000000000000000001000111 # origin: (00010-01011) --> dest: (10010-11001,11100-11001)
0 872 0001000000000001000101000111011111000000000000000000000001001000 # origin: (01001-00111) --> dest: (01000-10100,01110-10011,00100-01100)
0 997 0001000000000011101001001011111111000000000000000000000001001001 # origin: (00011-00100) --> dest: (11101-00100,01110-00001,11010-00100,11110-10011,01100-01011)
0 812 0001000000000000100000110000000000000000000000000000000001001010 # origin: (01001-01101) --> dest: (00100-00011)
0 293 0001000000000011100111110000000000000000000000000000000001001011 # origin: (11011-01100) --> dest: (11100-11111)
0 322 0001000000000001110111000000000000000000000000000000000001001100 # origin: (11110-00111) --> dest: (01110-11100)
0 253 0001000000000001110010001111111110000000000000000000000001001101 # origin: (10001-10000) --> dest: (01110-01000,01011-10110,10001-00110)
0 442 0001000000000010101000100101101101000000000000000000000001001110 # origin: (10000-01011) --> dest: (10101-00010,11110-01111)
0 222 0001000000000011001101000000000000000000000000000000000001001111 # origin: (10100-10001) --> dest: (11001-10100)
0 779 0001000000000010010100001011111101000000000000000000000001010000 # origin: (01100-01110) --> dest: (10010-10000,10010-00100,00100-01100,10101-01001,10011-01101)
0 946 0001000000000010010110010111000000000000000000000000000001010001 # origin: (00010-01011) --> dest: (10010-11001,11100-11001)
0 872 0001000000000001000101000111011111000000000000000000000001010010 # origin: (01001-00111) --> dest: (01000-10100,01110-10011,00100-01100)
0 997 0001000000000011101001001011111111000000000000000000000001010011 # origin: (00011-00100) --> dest: (11101-00100,01110-00001,11010-00100,11110-10011,01100-01011)
0 812 0001000000000000100000110000000000000000000000000000000001010100 # origin: (01001-01101) --> dest: (00100-00011)
0 293 0001000000000011100111110000000000000000000000000000000001010101 # origin: (11011-01100) --> dest: (11100-11111)
0 322 0001000000000001110111000000000000000000000000000000000001010110 # origin: (11110-00111) --> dest: (01110-11100)
0 253 0001000000000001110010001111111110000000000000000000000001010111 # origin: (10001-10000) --> dest: (01110-01000,01011-10110,10001-00110)
0 442 0001000000000010101000100101101101000000000000000000000001011000 # origin: (10000-01011) --> dest: (10101-00010,11110-01111)
0 222 0001000000000011001101000000000000000000000000000000000001011001 # origin: (10100-10001) --> dest: (11001-10100)
0 779 0001000000000010010100001011111101000000000000000000000001011010 # origin: (01100-01110) --> dest: (10010-10000,10010-00100,00100-01100,10101-01001,10011-01101)
0 946 0001000000000010010110010111000000000000000000000000000001011011 # origin: (00010-01011) --> dest: (10010-11001,11100-11001)
0 872 0001000000000001000101000111011111000000000000000000000001011100 # origin: (01001-00111) --> dest: (01000-10100,01110-10011,00100-01100)
0 997 0001000000000011101001001011111111000000000000000000000001011101 # origin: (00011-00100) --> dest: (11101-00100,01110-00001,11010-00100,11110-10011,01100-01011)
0 812 0001000000000000100000110000000000000000000000000000000001011110 # origin: (01001-01101) --> dest: (00100-00011)
0 293 0001000000000011100111110000000000000000000000000000000001011111 # origin: (11011-01100) --> dest: (11100-11111)
0 322 0001000000000001110111000000000000000000000000000000000001100000 # origin: (11110-00111) --> dest: (01110-11100)
0 253 0001000000000001110010001111111110000000000000000000000001100001 # origin: (10001-10000) --> dest: (01110-01000,01011-10110,10001-00110)
0 442 0001000000000010101000100101101101000000000000000000000001100010 # origin: (10000-01011) --> dest: (10101-00010,11110-01111)
0 222 0001000000000011001101000000000000000000000000000000000001100011 # origin: (10100-10001) --> dest: (11001-10100)
0 779 0001000000000010010100001011111101000000000000000000000001100100 # origin: (01100-01110) --> dest: (10010-10000,10010-00100,00100-01100,10101-01001,10011-01101)

19732
test/input/noc_tests/random_pe_to_pe_test/test.log
View file

File diff suppressed because it is too large Load diff

25
test/noc_tb.vhdl
View file

@ -49,8 +49,7 @@ architecture bench of noc_tb is
procedure log_test_result (
index : integer;
istwert : WORD;
is_external : std_logic;
istpath : integer
is_external : std_logic
) is
variable rowOut : LINE;
begin
@ -104,19 +103,30 @@ begin
variable is_external : std_logic_vector(0 downto 0);
variable path : integer;
variable data : std_logic_vector(63 downto 0);
variable wait_for_pe : boolean;
variable wait_for_ec : boolean;
begin
arstN <= '0';
data_chip_in <= (others => (others => '0'));
c_rcv_reqs <= (others => '0');
pe_data_in <= (others => (others => '0'));
pe_rcv_reqs <= (others => '0');
wait_for_pe := false;
wait_for_ec := false;
wait until rising_edge(clk);
arstN <= '1';
wait until rising_edge(clk);
while not(endfile(stimuli_file)) loop
readline(stimuli_file, input_line);
if input_line.all'length = 0 then
wait until rising_edge(clk);
if wait_for_pe then
wait on pe_rcv_acks;
elsif wait_for_ec then
wait on c_rcv_ack;
end if;
wait_for_pe := false;
wait_for_ec := false;
--wait until rising_edge(clk);
next;
elsif input_line.all(1) = '#' then
next;
@ -139,11 +149,13 @@ begin
report "Invalid path index value in file (external)" severity error;
data_chip_in(path) <= data;
c_rcv_reqs(path) <= not c_rcv_reqs(path);
wait_for_ec := true;
else
assert path < 4**level-1
report "Invalid path index value in file (ds)" severity error;
pe_data_in(path) <= data;
pe_rcv_reqs(path) <= not pe_rcv_reqs(path);
wait_for_pe := true;
end if;
exit when endfile(stimuli_file);
end loop;
@ -154,15 +166,13 @@ begin
c_send_reqs_prev, pe_send_reqs_prev,
data_chip_out, pe_data_out, pe_send_ack, c_send_ack)
variable istwert : WORD;
variable istpath : integer;
begin
if c_send_reqs'event or c_send_reqs_prev'event then
for i in 0 to num_paths_ext*4-1 loop
if (c_send_reqs(i) = '0' and c_send_reqs_prev(i) = '1') or
(c_send_reqs(i) = '1' and c_send_reqs_prev(i) = '0') then
istwert := data_chip_out(i);
istpath := i;
log_test_result(i, istwert, '1', istpath);
log_test_result(i, istwert, '1');
c_send_ack_nxt(i) <= not c_send_ack(i);
else
c_send_ack_nxt(i) <= c_send_ack(i);
@ -179,8 +189,7 @@ begin
if (pe_send_reqs(i) = '0' and pe_send_reqs_prev(i) = '1') or
(pe_send_reqs(i) = '1' and pe_send_reqs_prev(i) = '0') then
istwert := pe_data_out(i);
istpath := i;
log_test_result(i, istwert, '0', istpath);
log_test_result(i, istwert, '0');
pe_send_ack_nxt(i) <= not pe_send_ack(i);
else
pe_send_ack_nxt(i) <= pe_send_ack(i);

31
test/scripts/generate_test_files/generate_test_files.py
View file

@ -6,6 +6,7 @@ from utils import *
#recv_paths = [["00010","01110","11110","10011","10011","00000",
# "01101","01001","11011","11011","10101","01100"]]
sender_paths, recv_paths = generate_random_send_recv_paths(10)
repetitions = 10
test_name = "random_pe_to_pe_test"
# constants
@ -13,20 +14,22 @@ stimuli = "# is external? | path | data\n"
reference = ""
data_packet = 1
for p, path in enumerate(sender_paths):
if len(path) == 2:
index_path = get_index_path(path[0], path[1])
stimuli += "0 " + str(index_path) + " "
if len(recv_paths[p]) == 1:
data_packet, stimuli, reference = gen_ref_for_direct_msg(
path, recv_paths[p], data_packet, stimuli, reference)
elif len(recv_paths[p]) == 2:
data_packet, stimuli, reference = gen_ref_for_sing_dir_multicast(
path, recv_paths[p], data_packet, stimuli, reference)
else:
data_packet, stimuli, reference = gen_ref_for_mult_dir_multicast(
path, recv_paths[p], data_packet, stimuli, reference)
data_packet += 1
for i in range(repetitions):
for p, path in enumerate(sender_paths):
if len(path) == 2:
index_path = get_index_path(path[0], path[1])
stimuli += "0 " + str(index_path) + " "
if len(recv_paths[p]) == 1:
data_packet, stimuli, reference = gen_ref_for_direct_msg(
path, recv_paths[p], data_packet, stimuli, reference)
elif len(recv_paths[p]) == 2:
data_packet, stimuli, reference = gen_ref_for_sing_dir_multicast(
path, recv_paths[p], data_packet, stimuli, reference)
else:
data_packet, stimuli, reference = gen_ref_for_mult_dir_multicast(
path, recv_paths[p], data_packet, stimuli, reference)
data_packet += 1
stimuli += "\n"
with open("stimuli.txt", "w") as f:
f.write(stimuli)

19732
test/scripts/generate_test_files/result.ref
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File diff suppressed because it is too large Load diff

120
test/scripts/generate_test_files/stimuli.txt
View file

@ -1,11 +1,111 @@
# is external? | path | data
0 346 0001000000000010000011000100010001000000000000000000000000000001 # origin: (11100-00011) --> dest: (10000-01100,11000-11101)
0 14 0001000000000011001011101010001001000000000000000000000000000001 # origin: (11100-11101) --> dest: (11001-01110,01101-00111)
0 459 0001000000000001100110101111111111000000000000000000000000000001 # origin: (10100-00110) --> dest: (01100-11010,01011-00010,01110-10100,11001-00001,01110-00100,00111-10001)
0 968 0001000000000001101110010000000000000000000000000000000000000001 # origin: (00101-00111) --> dest: (01101-11001)
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3
test/scripts/generate_test_files/utils.py
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@ -147,7 +147,7 @@ def gen_ref_for_mult_dir_multicast(path, recv_path, data_packet, stimuli, refere
return data_packet, stimuli, reference
def generate_random_send_recv_paths(num_msgs):
def generate_random_send_recv_paths(num_msgs, repetitions = 1):
sender_paths = []
recv_paths = []
for i in range(num_msgs):
@ -168,4 +168,5 @@ def generate_random_send_recv_paths(num_msgs):
recv_path.append(f'{np.random.randint(32):05b}')
recv_path.append(f'{np.random.randint(32):05b}')
recv_paths.append(recv_path)
return sender_paths, recv_paths

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