fix: changes tested successfully

noc/quadtree.vhdl

@@ -45,34 +45,34 @@ end quadtree;
 
 architecture impl of quadtree is
     constant num_routers :   integer := calculate_num_routers_qt(level, top_level);
-    signal r_core_x      :   std_logic_vector(19 downto 0) := (others => '0');
-    signal r_core_y      :   std_logic_vector(19 downto 0) := (others => '0');
+    signal r_core_x      :   std_logic_vector(19 downto 0);
+    signal r_core_y      :   std_logic_vector(19 downto 0);
 begin
     set_router_core: process(arstN, core_x, core_y)
-        variable s_core_x, s_core_y :   std_logic_vector(19 downto 0);
+        variable v_core_x, v_core_y :   std_logic_vector(19 downto 0);
     begin
         if arstN = '0' then
-            s_core_x := (others => '-');
-            s_core_y := (others => '-');
+            v_core_x := (others => '-');
+            v_core_y := (others => '-');
             for i in 0 to 3 loop
-                s_core_x((i+1)*5-1 downto i*5) := core_x;
-                s_core_y((i+1)*5-1 downto i*5) := core_y;
+                v_core_x((i+1)*5-1 downto i*5) := core_x;
+                v_core_y((i+1)*5-1 downto i*5) := core_y;
                 if i = 0 then
-                    s_core_x(5*i+level-1) := '1';
-                    s_core_y(5*i+level-1) := '1';
+                    v_core_x(5*i+level-1) := '1';
+                    v_core_y(5*i+level-1) := '1';
                 elsif i = 1 then
-                    s_core_x(5*i+level-1) := '1';
-                    s_core_y(5*i+level-1) := '0';
+                    v_core_x(5*i+level-1) := '1';
+                    v_core_y(5*i+level-1) := '0';
                 elsif i = 2 then
-                    s_core_x(5*i+level-1) := '0';
-                    s_core_y(5*i+level-1) := '1';
+                    v_core_x(5*i+level-1) := '0';
+                    v_core_y(5*i+level-1) := '1';
                 else
-                    s_core_x(5*i+level-1) := '0';
-                    s_core_y(5*i+level-1) := '0';
+                    v_core_x(5*i+level-1) := '0';
+                    v_core_y(5*i+level-1) := '0';
                 end if;
             end loop;
-            r_core_x <= s_core_x;
-            r_core_y <= s_core_y;
+            r_core_x <= v_core_x;
+            r_core_y <= v_core_y;
         end if;
     end process;
 

router/arbiter.vhdl

@@ -11,8 +11,8 @@ generic(
     num_paths_down      :   integer := 1
 );
 port (
-    clk, arstN      : in std_logic;
-    rout_pos        : in t_pos_addr;
+    chip_pos        : in t_chip_addr;
+    core_pos        : in t_addr;
     packets         : in t_DATA(num_paths_up+num_paths_down*4-1 downto 0);
     valid_data      : in std_logic_vector(num_paths_up+num_paths_down*4-1 downto 0);
     avai_paths      : in std_logic_vector(num_paths_up+num_paths_down*4-1 downto 0);
@@ -26,7 +26,7 @@ architecture impl of arbiter is
 
     signal dirs          :  t_DATA_DIRS(TOT_NUM_PATHS-1 downto 0);
 begin
-    get_rout_dir: process(rout_pos, valid_data, packets)
+    get_rout_dir: process(chip_pos, core_pos, valid_data, packets)
         variable pack_dest   : t_pos_addr;
         --variable header      : std_logic_vector(3 downto 0);
         variable is_upstream : boolean;
@@ -34,14 +34,15 @@ begin
         for i in 0 to TOT_NUM_PATHS-1 loop
             if valid_data(i) = '1' then
                 --header := packets(i)(63 downto 60);
-                pack_dest.chip_x := packets(i)(59 downto 55);
-                pack_dest.chip_y := packets(i)(54 downto 50);
-                pack_dest.core_x := packets(i)(49 downto 45);
-                pack_dest.core_y := packets(i)(44 downto 40);
-                pack_dest.copy_x := packets(i)(39 downto 35);
-                pack_dest.copy_y := packets(i)(34 downto 30);
+                pack_dest.chip_pos.x := packets(i)(59 downto 55);
+                pack_dest.chip_pos.y := packets(i)(54 downto 50);
+                pack_dest.core_pos.x := packets(i)(49 downto 45);
+                pack_dest.core_pos.y := packets(i)(44 downto 40);
+                pack_dest.copy_pos.x := packets(i)(39 downto 35);
+                pack_dest.copy_pos.y := packets(i)(34 downto 30);
                 is_upstream      := i >= num_paths_down*4;
-                dirs(i) <= single_packet_rout_dir_det(level, pack_dest, rout_pos, is_upstream);
+                dirs(i) <= single_packet_rout_dir_det(level, pack_dest, chip_pos, 
+                                                    core_pos, is_upstream);
             else
                 dirs(i) <= (others => '0');
             end if;

router/fifo.vhdl

@@ -47,21 +47,11 @@ begin
         end if;
     end process;
 
-    update_wr_ptr: process(wr_req, s_full, wr_ptr)
-    begin
-        if wr_req = '1' and s_full = '0' then
-            wr_ptr_nxt <= wr_ptr + 1;
-        else
-            wr_ptr_nxt <= wr_ptr;
-        end if;
-    end process;
-
     select_fifo_for_writing: process(wr_req, s_full, wr_ptr)
-        variable one    :   unsigned(DEPTH-1 downto 0);
+        constant one    :   unsigned(DEPTH-1 downto 0) := to_unsigned(1, DEPTH);
     begin
         fifo_sel <= (others => '0');
         if wr_req = '1' and s_full = '0' then
-            one      := to_unsigned(1, DEPTH);
             fifo_sel <= std_logic_vector(shift_left(one, to_integer(wr_ptr(F_PTR_SIZE-2 downto 0))));
         end if;
     end process;
@@ -77,38 +67,15 @@ begin
         end loop;
     end process write;
 
-    update_rd_ptr: process(rd_req, s_empty, rd_ptr)
-    begin
-        if rd_req = '1' and s_empty = '0' then
-            rd_ptr_nxt <= rd_ptr + 1;
-        else
-            rd_ptr_nxt <= rd_ptr;
-        end if;
-    end process;
+    data_out_nxt <= fifo(to_integer(rd_ptr(F_PTR_SIZE-2 downto 0)));
+    
+    s_full_nxt <= '1' when 
+        rd_ptr_nxt(F_PTR_SIZE-2 downto 0) = wr_ptr_nxt(F_PTR_SIZE-2 downto 0) and
+        rd_ptr_nxt(F_PTR_SIZE-1) /= wr_ptr_nxt(F_PTR_SIZE-1) else '0';
+    s_empty_nxt <= '1' when rd_ptr_nxt = wr_ptr_nxt else '0';
 
-    read: process(rd_ptr, fifo)
-    begin
-        data_out_nxt <= fifo(to_integer(rd_ptr(F_PTR_SIZE-2 downto 0)));
-    end process read;
-
-    determine_full_flag: process(rd_ptr_nxt, wr_ptr_nxt)
-    begin
-        if rd_ptr_nxt(F_PTR_SIZE-2 downto 0) = wr_ptr_nxt(F_PTR_SIZE-2 downto 0) and
-                rd_ptr_nxt(F_PTR_SIZE-1) /= wr_ptr_nxt(F_PTR_SIZE-1) then
-            s_full_nxt <= '1';
-        else
-            s_full_nxt <= '0';
-        end if;
-    end process;
-
-    determine_empty_flag: process(rd_ptr_nxt, wr_ptr_nxt)
-    begin
-        if rd_ptr_nxt = wr_ptr_nxt then
-            s_empty_nxt <= '1';
-        else
-            s_empty_nxt <= '0';
-        end if;
-    end process;
+    rd_ptr_nxt <= rd_ptr + 1 when rd_req = '1' and s_empty = '0' else rd_ptr;
+    wr_ptr_nxt <= wr_ptr + 1 when wr_req = '1' and s_full = '0' else wr_ptr;
 
     full  <= s_full;
     empty <= s_empty;

router/parent_arbiter.vhdl

@@ -11,8 +11,8 @@ generic(
     num_paths_down      :   integer := 16
 );
 port (
-    clk, arstN      : in std_logic;
-    rout_pos        : in t_pos_addr;
+    chip_pos        : in t_chip_addr;
+    core_pos        : in t_addr;
     packets         : in t_DATA(num_paths_up*4+num_paths_down*4-1 downto 0);
     valid_data      : in std_logic_vector(num_paths_up*4+num_paths_down*4-1 downto 0);
     avai_paths      : in std_logic_vector(num_paths_up*4+num_paths_down*4-1 downto 0);
@@ -26,21 +26,21 @@ architecture impl of parent_arbiter is
 
     signal dirs          :  t_DATA_DIRS_EXT(TOT_NUM_PATHS-1 downto 0);
 begin
-    L5_get_rout_dir: process(rout_pos, valid_data, packets)
+    L5_get_rout_dir: process(chip_pos, core_pos, valid_data, packets)
     variable pack_dest   : t_pos_addr;
     --variable header      : std_logic_vector(3 downto 0);
     begin
         for i in 0 to TOT_NUM_PATHS-1 loop
             if valid_data(i) = '1' then
                 --header := packets(i)(63 downto 60);
-                pack_dest.chip_x := packets(i)(59 downto 55);
-                pack_dest.chip_y := packets(i)(54 downto 50);
-                pack_dest.core_x := packets(i)(49 downto 45);
-                pack_dest.core_y := packets(i)(44 downto 40);
-                pack_dest.copy_x := packets(i)(39 downto 35);
-                pack_dest.copy_y := packets(i)(34 downto 30);
+                pack_dest.chip_pos.x := packets(i)(59 downto 55);
+                pack_dest.chip_pos.y := packets(i)(54 downto 50);
+                pack_dest.core_pos.x := packets(i)(49 downto 45);
+                pack_dest.core_pos.y := packets(i)(44 downto 40);
+                pack_dest.copy_pos.x := packets(i)(39 downto 35);
+                pack_dest.copy_pos.y := packets(i)(34 downto 30);
                 dirs(i) <= single_packet_parent_rout_dir_det(level, 
-                        pack_dest, rout_pos);
+                                pack_dest, chip_pos, core_pos);
             else
                 dirs(i) <= (others => '0');
             end if;

router/parent_router.vhdl

@@ -34,8 +34,9 @@ end parent_router;
 
 architecture impl of parent_router is
     constant TOT_NUM_PATHS      :   integer := num_paths_up*4 + num_paths_down*4;
+    constant chip_pos           :   t_chip_addr := (x => chip_x, y=> chip_y);
     
-    signal rout_pos             :   t_pos_addr;
+    signal core_pos             :   t_addr;
     signal rcv_buff_out         :   t_FIFO_OUTS(TOT_NUM_PATHS-1 downto 0);
     signal snd_buff_wr_in       :   t_FIFO_WR_INS(TOT_NUM_PATHS-1 downto 0);
     signal snd_buff_out         :   t_FIFO_OUTS(TOT_NUM_PATHS-1 downto 0);
@@ -120,9 +121,8 @@ begin
         num_paths_down=>num_paths_down
     )
     port map(
-        clk                 => clk,
-        arstN               => arstN,
-        rout_pos            => rout_pos,
+        chip_pos            => chip_pos,
+        core_pos            => core_pos,
         packets             => rd_data,
         valid_data          => valid_data,
         avai_paths          => avai_paths,
@@ -253,12 +253,6 @@ begin
     update_regs: process(arstN, clk)
     begin
         if arstN = '0' then
-            rout_pos.chip_x <= chip_x;
-            rout_pos.chip_y <= chip_y;
-            rout_pos.core_x <= core_x;
-            rout_pos.core_y <= core_y;
-            rout_pos.copy_x <= (others => '-');
-            rout_pos.copy_y <= (others => '-');
             packet_states   <= (others => Idle);
             rd_data         <= (others => (others => '0'));
         elsif rising_edge(clk) then
@@ -268,4 +262,7 @@ begin
             outb_rd_states  <= outb_rd_states_nxt;
         end if;
     end process;
+
+    core_pos.x <= core_x;
+    core_pos.y <= core_y;
 end impl;

router/router.vhdl

@@ -32,8 +32,9 @@ end router;
 
 architecture impl of router is
     constant TOT_NUM_PATHS      :   integer := num_paths_up + num_paths_down*4;
-    
-    signal rout_pos             :   t_pos_addr;
+    constant chip_pos           :   t_chip_addr := (x => chip_x, y=> chip_y);
+
+    signal core_pos             :   t_addr;
     signal rcv_buff_out         :   t_FIFO_OUTS(TOT_NUM_PATHS-1 downto 0);
     signal snd_buff_wr_in       :   t_FIFO_WR_INS(TOT_NUM_PATHS-1 downto 0);
     signal snd_buff_out         :   t_FIFO_OUTS(num_paths_up+num_paths_down*4-1 downto 0);
@@ -97,9 +98,8 @@ begin
         num_paths_down=>num_paths_down
     )
     port map(
-        clk                 => clk,
-        arstN               => arstN,
-        rout_pos            => rout_pos,
+        chip_pos            => chip_pos,
+        core_pos            => core_pos,
         packets             => rd_data,
         valid_data          => valid_data,
         avai_paths          => avai_paths,
@@ -230,12 +230,6 @@ begin
     update_regs: process(arstN, clk)
     begin
         if arstN = '0' then
-            rout_pos.chip_x <= chip_x;
-            rout_pos.chip_y <= chip_y;
-            rout_pos.core_x <= core_x;
-            rout_pos.core_y <= core_y;
-            rout_pos.copy_x <= (others => '-');
-            rout_pos.copy_y <= (others => '-');
             packet_states   <= (others => Idle);
             outb_rd_states  <= (others => EmptyFifo);
             rd_data         <= (others => (others => '0'));
@@ -246,4 +240,7 @@ begin
             outb_rd_states  <= outb_rd_states_nxt;
         end if;
     end process;
+
+    core_pos.x <= core_x;
+    core_pos.y <= core_y;
 end impl;

router/router_components.vhdl

@@ -43,8 +43,8 @@ package router_components is
             num_paths_down      :   integer := 1
         );
         port (
-            clk, arstN        : in std_logic;
-            rout_pos          : in t_pos_addr;
+            chip_pos          : in t_chip_addr;
+            core_pos          : in t_addr;
             packets           : in t_DATA(num_paths_up+num_paths_down*4-1 downto 0);
             valid_data        : in std_logic_vector(
                                     num_paths_up+num_paths_down*4-1 downto 0);
@@ -64,8 +64,8 @@ package router_components is
         num_paths_down      :   integer := 16
     );
     port (
-        clk, arstN      : in std_logic;
-        rout_pos        : in t_pos_addr;
+        chip_pos        : in t_chip_addr;
+        core_pos        : in t_addr;
         packets         : in t_DATA(num_paths_up*4+num_paths_down*4-1 downto 0);
         valid_data      : in std_logic_vector(num_paths_up*4+num_paths_down*4-1 downto 0);
         avai_paths      : in std_logic_vector(num_paths_up*4+num_paths_down*4-1 downto 0);

router/router_types.vhdl

@@ -41,13 +41,20 @@ package router_types is
         full        :   std_logic;
     end record;
 
+    type t_chip_addr is record
+        x :   std_logic_vector(CHIP_ADDR_SIZE-1 downto 0);
+        y :   std_logic_vector(CHIP_ADDR_SIZE-1 downto 0);
+    end record;
+
+    type t_addr is record
+        x :   std_logic_vector(DEST_ADDR_SIZE-1 downto 0);
+        y :   std_logic_vector(DEST_ADDR_SIZE-1 downto 0);
+    end record;
+
     type t_pos_addr is record
-        chip_x :   std_logic_vector(CHIP_ADDR_SIZE-1 downto 0);
-        chip_y :   std_logic_vector(CHIP_ADDR_SIZE-1 downto 0);
-        core_x :   std_logic_vector(DEST_ADDR_SIZE-1 downto 0);
-        core_y :   std_logic_vector(DEST_ADDR_SIZE-1 downto 0);
-        copy_x :   std_logic_vector(DEST_ADDR_SIZE-1 downto 0);
-        copy_y :   std_logic_vector(DEST_ADDR_SIZE-1 downto 0);
+        chip_pos :   t_chip_addr;
+        core_pos :   t_addr;
+        copy_pos :   t_addr;
     end record;
 
     type t_FIFO_WR_INS   is array (integer range <>) of t_fifo_wr_in;

router/routing_functions.vhdl

@@ -8,14 +8,16 @@ package routing_functions is
     function single_packet_rout_dir_det (
         level         :   in integer; 
         pack_dest     :   in t_pos_addr; 
-        rout_pos      :   in t_pos_addr;
+        chip_pos      :   in t_chip_addr;
+        core_pos      :   in t_addr;
         is_upstream   :   in boolean
     ) return std_logic_vector;
 
     function single_packet_parent_rout_dir_det (
         level         :   in integer; 
         pack_dest     :   in t_pos_addr; 
-        rout_pos      :   in t_pos_addr
+        chip_pos      :   in t_chip_addr;
+        core_pos      :   in t_addr
     ) return std_logic_vector;
 
     function retrieve_avai_path_index (
@@ -38,18 +40,19 @@ end package;
 package body routing_functions is
     function single_packet_parent_rout_dir_det(
         level         :   in integer; 
-        pack_dest     :   in t_pos_addr; 
-        rout_pos      :   in t_pos_addr
+        pack_dest     :   in t_pos_addr;
+        chip_pos      :   in t_chip_addr;
+        core_pos      :   in t_addr
     ) return std_logic_vector is
         variable chip_d_x, chip_d_y : std_logic_vector(CHIP_ADDR_SIZE-1 downto 0); 
         variable chip_r_x, chip_r_y : std_logic_vector(CHIP_ADDR_SIZE-1 downto 0);
         variable is_upstream        : boolean;
     begin
         is_upstream := true;
-        chip_r_x := rout_pos.chip_x;
-        chip_r_y := rout_pos.chip_y;
-        chip_d_x := pack_dest.chip_x;
-        chip_d_y := pack_dest.chip_y;
+        chip_r_x := chip_pos.x;
+        chip_r_y := chip_pos.y;
+        chip_d_x := pack_dest.chip_pos.x;
+        chip_d_y := pack_dest.chip_pos.y;
         
         if to_integer(unsigned(chip_d_y)) < to_integer(unsigned(chip_r_y)) then
             return "10000000"; -- north
@@ -61,14 +64,15 @@ package body routing_functions is
             return "00010000"; -- east
         else
             return "000" & single_packet_rout_dir_det(
-                            level, pack_dest, rout_pos, is_upstream);
+                            level, pack_dest, chip_pos, core_pos, is_upstream);
         end if;
     end function;
 
     function single_packet_rout_dir_det (
         level         :   in integer; 
         pack_dest     :   in t_pos_addr; 
-        rout_pos      :   in t_pos_addr;
+        chip_pos      :   in t_chip_addr;
+        core_pos      :   in t_addr;
         is_upstream   :   in boolean
     ) return std_logic_vector is
         variable dest_x, dest_y, copy_x, copy_y :   std_logic;
@@ -76,23 +80,22 @@ package body routing_functions is
         variable is_cousin_core                 :   boolean;
         variable needs_multicast                :   boolean;
     begin
-        dest_x := pack_dest.core_x(level-1);
-        dest_y := pack_dest.core_y(level-1);
-        copy_x := pack_dest.copy_x(level-1);
-        copy_y := pack_dest.copy_y(level-1);
+        dest_x := pack_dest.core_pos.x(level-1);
+        dest_y := pack_dest.core_pos.y(level-1);
+        copy_x := pack_dest.copy_pos.x(level-1);
+        copy_y := pack_dest.copy_pos.y(level-1);
         if level /=5 then
-            is_other_chip  := pack_dest.chip_x /= rout_pos.chip_x or 
-                                pack_dest.chip_y /= rout_pos.chip_y;
-            is_cousin_core := (pack_dest.core_x(DEST_ADDR_SIZE-1 downto level) /= 
-                                rout_pos.core_x(DEST_ADDR_SIZE-1 downto level)) or
-                                (pack_dest.core_y(DEST_ADDR_SIZE-1 downto level) /= 
-                                rout_pos.core_y(DEST_ADDR_SIZE-1 downto level));
-                --pack_dest.core_x(DEST_ADDR_SIZE-1 downto level) /= rout_pos.core_x or
-                --pack_dest.core_y(DEST_ADDR_SIZE-1 downto level) /= rout_pos.core_y;
+            is_other_chip  := pack_dest.chip_pos.x /= chip_pos.x or 
+                                pack_dest.chip_pos.y /= chip_pos.y;
+            is_cousin_core := (pack_dest.core_pos.x(DEST_ADDR_SIZE-1 downto level) /= 
+                                core_pos.x(DEST_ADDR_SIZE-1 downto level)) or
+                                (pack_dest.core_pos.y(DEST_ADDR_SIZE-1 downto level) /= 
+                                core_pos.y(DEST_ADDR_SIZE-1 downto level));
             needs_multicast := FALSE;
             for i in level to DEST_ADDR_SIZE-1 loop
-                needs_multicast := needs_multicast or (pack_dest.copy_x(i) = '1') or 
-                                                    (pack_dest.copy_y(i) = '1');
+                needs_multicast := needs_multicast or (
+                                    pack_dest.copy_pos.x(i) = '1') or (
+                                    pack_dest.copy_pos.y(i) = '1');
             end loop;
         else
             is_other_chip := FALSE;

synthesis/cmd/do_synth_arbiter.tcl

@@ -2,13 +2,11 @@ set level [getenv LEVEL]
 set npu [getenv NPU]
 set npd [getenv NPD]
 
-analyze -library WORK -format vhdl {../router/fifo.vhdl}
 analyze -library WORK -format vhdl {../router/router_types.vhdl}
 analyze -library WORK -format vhdl {../router/routing_functions.vhdl}
-analyze -library WORK -format vhdl {../router/receiver.vhdl}
-analyze -library WORK -format vhdl {../router/sender.vhdl}
 analyze -library WORK -format vhdl {../router/arbiter.vhdl}
 elaborate arbiter -library WORK -parameters "level = $level, num_paths_up = $npu, num_paths_down = $npd"
+check_design
 
 create_clock [get_ports clk]  -period 8.0  -waveform {0 4} -name clk
 
@@ -17,16 +15,11 @@ set_clock_uncertainty 0.025  -hold [get_clocks clk]
 set_clock_transition -fall 0.04 [get_clocks clk]
 set_clock_transition -rise 0.04 [get_clocks clk]
 
-set_dont_touch clk
-set_dont_touch arstN
-
 set_clock_latency -max -source 0.1 [get_clocks clk] 
 
 set_input_delay -max -clock clk  0.05 [get_ports {rout_pos packets valid_data avai_paths}]
 set_output_delay -max -clock clk  0.05 [all_outputs]
 
-set_false_path -from [get_ports arstN]
-
 check_timing
 compile
 report_area > reports/arbiter-$level-spl_synth.area

synthesis/cmd/do_synth_parent_arbiter.tcl

@@ -2,11 +2,8 @@ set level [getenv LEVEL]
 set npu [getenv NPU]
 set npd [getenv NPD]
 
-analyze -library WORK -format vhdl {../router/fifo.vhdl}
 analyze -library WORK -format vhdl {../router/router_types.vhdl}
 analyze -library WORK -format vhdl {../router/routing_functions.vhdl}
-analyze -library WORK -format vhdl {../router/receiver.vhdl}
-analyze -library WORK -format vhdl {../router/sender.vhdl}
 analyze -library WORK -format vhdl {../router/parent_arbiter.vhdl}
 elaborate parent_arbiter -library WORK -parameters "level = $level, num_paths_up = $npu, num_paths_down = $npd"
 
@@ -17,16 +14,11 @@ set_clock_uncertainty 0.025  -hold [get_clocks clk]
 set_clock_transition -fall 0.04 [get_clocks clk]
 set_clock_transition -rise 0.04 [get_clocks clk]
 
-set_dont_touch clk
-set_dont_touch arstN
-
 set_clock_latency -max -source 0.1 [get_clocks clk] 
 
 set_input_delay -max -clock clk  0.05 [get_ports {rout_pos packets valid_data avai_paths}]
 set_output_delay -max -clock clk  0.05 [all_outputs]
 
-set_false_path -from [get_ports arstN]
-
 check_timing
 compile
 report_area > reports/parent-arbiter-$level-spl_synth.area

synthesis/cmd/do_synth_router.tcl

@@ -10,11 +10,13 @@ analyze -library WORK -format vhdl {../router/routing_functions.vhdl}
 analyze -library WORK -format vhdl {../router/receiver.vhdl}
 analyze -library WORK -format vhdl {../router/sender.vhdl}
 analyze -library WORK -format vhdl {../router/arbiter.vhdl}
+link
 analyze -library WORK -format vhdl {../router/router.vhdl}
 elaborate router -library WORK -parameters 
 "level = $level, num_paths_up = $npu, num_paths_down = $npd,
 buffer_width = 64, buffer_depth = 4, fifo_ptr_size = 3,
 chip_x = $chip_x, chip_y = $chip_y"
+check_design
 
 create_clock [get_ports clk]  -period 8.0  -waveform {0 4} -name clk
 
@@ -28,7 +30,7 @@ set_dont_touch arstN
 
 set_clock_latency -max -source 0.1 [get_clocks clk] 
 
-set_input_delay -max -clock clk  0.05 [get_ports {rout_pos packets valid_data avai_paths arb_complete buff_wr_in}]
+set_input_delay -max -clock clk  0.05 [get_ports {core_x core_y data_in rcv_reqs send_ack rcv_acks send_reqs data_out}]
 set_output_delay -max -clock clk  0.05 [all_outputs]
 
 set_false_path -from [get_ports arstN]

synthesis/cmd/do_synth_router_lvl1.sh

@@ -0,0 +1 @@
+LEVEL=1 NPU=2 NPD=1 CHIP_X=00001 CHIP_Y=00001 dc_shell -x "source cmd/do_synth_arbiter.tcl; quit" | tee -a log/synthesis.log

test/input/noc_tests/simple_pe_to_pe_test/simulation.log

@@ -0,0 +1 @@
+0 972 0001000000000000101001010000000000000000000000000000000000000100

test/input/noc_tests/simple_pe_to_pe_test/test.log

@@ -0,0 +1,2 @@
+0 972 0001000000000000101001010000000000000000000000000000000000000100 # path = 1023-(4**2)*3-(4**0)* ---> failed!
+One or more test failed :(