refactor: retyping, simplifying and comments

Readme.md

@@ -38,4 +38,5 @@ FIFO5 -> U   -> Upstream
 ### Router
 ![alt text](./drawings/router.png)
 
+# TODO: rewrite sh and tcl files
 # TODO: cadence-area consumption (synthesis)

noc/noc.vhdl

@@ -8,12 +8,12 @@ use work.noc_conf.all;
 
 entity noc is
 generic ( 
-    num_paths_ext     :   integer := 32;
+    num_paths_ext     :   positive := 32;
-    buffer_width      :   integer := 64;
+    buffer_width      :   positive := 64;
-    buffer_depth      :   integer := 4;
+    buffer_depth      :   positive := 4;
-    fifo_ptr_size     :   integer := 3;
+    fifo_ptr_size     :   positive := 3;
-    level             :   integer := 5;
+    level             :   positive := 5;
-    top_level         :   integer := 5;
+    top_level         :   positive := 5;
     chip_x            :   std_logic_vector(4 downto 0) := "00000";
     chip_y            :   std_logic_vector(4 downto 0) := "00000"
 );
@@ -41,11 +41,13 @@ port (
 end noc;
 
 architecture impl of noc is
-    constant l5_core_x       :   std_logic_vector(4 downto 0) := "-----";
+    constant l5_core_x       :   std_logic_vector(4 downto 0) := "00000";
-    constant l5_core_y       :   std_logic_vector(4 downto 0) := "-----";
+    constant l5_core_y       :   std_logic_vector(4 downto 0) := "00000";
-    constant num_paths_up    :   integer := 32;
+    constant num_paths_up    :   positive := 32;
-    constant num_paths_down  :   integer := 16;
+    constant num_paths_down  :   positive := 16;
-    constant num_routers     :   integer := calculate_num_routers(top_level);
+    constant npu_bit_size    :   positive := 5;
+    constant npd_bit_size    :   positive := 4;
+    constant num_routers     :   positive := calculate_num_routers(top_level);
 
     signal r_data_ds_in      :   t_DATA(4*num_paths_down-1 downto 0);
     signal r_data_ds_out     :   t_DATA(4*num_paths_down-1 downto 0);
@@ -80,6 +82,7 @@ begin
 
     router_l5:  parent_router
     generic map(num_paths_up => num_paths_up, num_paths_down => num_paths_down, 
+        npu_bit_size => npu_bit_size, npd_bit_size => npd_bit_size,
         level => level, buffer_width => buffer_width, buffer_depth => buffer_depth, 
         fifo_ptr_size => fifo_ptr_size, chip_x => chip_x, chip_y => chip_y)
     port map(clk => clks(num_routers-1), arstN => arstN, core_x => l5_core_x, core_y => l5_core_y,
@@ -90,6 +93,7 @@ begin
 
     quadtree_inst: quadtree
         generic map(num_paths_up => num_paths_up, num_paths_down => num_paths_down,
+            npu_bit_size => npu_bit_size, npd_bit_size => npd_bit_size, 
             level => level, top_level => top_level,
             buffer_width => buffer_width, buffer_depth => buffer_depth, 
             fifo_ptr_size => fifo_ptr_size, chip_x => chip_x, chip_y => chip_y)

noc/noc_conf.vhdl

@@ -7,12 +7,14 @@ use work.quadtree_components.all;
 package noc_conf is
     component parent_router is
     generic ( 
-        num_paths_up      :   integer := 32;
+        num_paths_up      :   positive := 32;
-        num_paths_down    :   integer := 16;
+        num_paths_down    :   positive := 16;
-        level             :   integer := 5;
+        npu_bit_size      :   positive := 5;
-        buffer_width      :   integer := 64;
+        npd_bit_size      :   positive := 4;
-        buffer_depth      :   integer := 4;
+        level             :   positive := 5;
-        fifo_ptr_size     :   integer := 3;
+        buffer_width      :   positive := 64;
+        buffer_depth      :   positive := 4;
+        fifo_ptr_size     :   positive := 3;
         chip_x            :   std_logic_vector(4 downto 0);
         chip_y            :   std_logic_vector(4 downto 0)
     );
@@ -34,13 +36,15 @@ package noc_conf is
 
     component quadtree is
     generic (
-        num_paths_up      :   integer := 32;
+        num_paths_up      :   positive := 32;
-        num_paths_down    :   integer := 16;
+        num_paths_down    :   positive := 16;
-        buffer_width      :   integer := 64;
+        npu_bit_size      :   positive := 5;
-        buffer_depth      :   integer := 4;
+        npd_bit_size      :   positive := 4;
-        fifo_ptr_size     :   integer := 3;
+        buffer_width      :   positive := 64;
-        level             :   integer := 5;
+        buffer_depth      :   positive := 4;
-        top_level         :   integer := 5;
+        fifo_ptr_size     :   positive := 3;
+        level             :   positive := 5;
+        top_level         :   positive := 5;
         chip_x            :   std_logic_vector(4 downto 0) := "00000";
         chip_y            :   std_logic_vector(4 downto 0) := "00000"
     );

noc/quadtree.vhdl

@@ -7,13 +7,15 @@ use work.quadtree_components.all;
 
 entity quadtree is
 generic (
-    num_paths_up      :   integer := 32;
+    num_paths_up      :   positive := 32;
-    num_paths_down    :   integer := 16;
+    num_paths_down    :   positive := 16;
-    buffer_width      :   integer := 64;
+    npu_bit_size      :   positive := 5;
-    buffer_depth      :   integer := 4;
+    npd_bit_size      :   positive := 4;
-    fifo_ptr_size     :   integer := 3;
+    buffer_width      :   positive := 64;
-    level             :   integer := 5;
+    buffer_depth      :   positive := 4;
-    top_level         :   integer := 5;
+    fifo_ptr_size     :   positive := 3;
+    level             :   positive := 5;
+    top_level         :   positive := 5;
     chip_x            :   std_logic_vector(4 downto 0) := "00000";
     chip_y            :   std_logic_vector(4 downto 0) := "00000"
 );
@@ -44,7 +46,7 @@ port (
 end quadtree;
 
 architecture impl of quadtree is
-    constant num_routers :   integer := calculate_num_routers_qt(level, top_level);
+    constant num_routers :   positive := calculate_num_routers_qt(level, top_level);
     signal r_core_x      :   std_logic_vector(19 downto 0);
     signal r_core_y      :   std_logic_vector(19 downto 0);
 begin
@@ -52,8 +54,8 @@ begin
         variable v_core_x, v_core_y :   std_logic_vector(19 downto 0);
     begin
         if arstN = '0' then
-            v_core_x := (others => '-');
+            v_core_x := (others => '0'); -- don't care
-            v_core_y := (others => '-');
+            v_core_y := (others => '0'); -- don't care
             for i in 0 to 3 loop
                 v_core_x((i+1)*5-1 downto i*5) := core_x;
                 v_core_y((i+1)*5-1 downto i*5) := core_y;
@@ -87,9 +89,9 @@ begin
     end generate;
     
     g_quadtree: if level > 1 generate
-        constant npu         :   integer := num_paths_up/2;
+        constant npu         :   positive := num_paths_up/2;
-        constant npd         :   integer := num_paths_down/2;
+        constant npd         :   positive := num_paths_down/2;
-        constant pow_level   :   integer := 4**(level-1);
+        constant pow_level   :   positive := 4**(level-1);
 
         signal r_data_in         :   t_DATA(4*npu+16*npd-1 downto 0);
         signal r_data_ds_in      :   t_DATA(16*npd-1 downto 0);
@@ -116,37 +118,41 @@ begin
         map_routers_inputs_outputs: process(data_in_us, r_data_ds_in, rcv_reqs_us, 
                                 r_rcv_reqs_ds, send_ack_us, r_snd_ack_ds, r_rcv_ack, 
                                 r_snd_reqs, r_data_out)
-        variable r_up_ind, r_low_ind : integer;
+        variable rui, rmi, rli, usri, dsri : natural range 0 to (16*npd+4*npu);
         begin
             for i in 0 to 3 loop
-                r_up_ind  := (4*npd+npu)*(i+1);
+                rui  := (4*npd+npu)*(i+1); -- router upper index
-                r_low_ind := (4*npd)*(i+1)+npu*i;
+                rmi := (4*npd)*(i+1)+npu*i; -- router middle index
+                rli := (4*npd+npu)*i; -- router middle index
+                usri := npu*(i+1); -- upstream router index
+                dsri := 4*npd*(i+1); -- downstream router index
 
                 -- inputs
-                r_data_in(r_up_ind-1 downto r_low_ind)       <= data_in_us(npu*(i+1)-1 downto npu*i);
+                r_data_in(rui-1 downto rmi)  <= data_in_us(usri-1 downto npu*i);
-                r_data_in(r_low_ind-1 downto (4*npd+npu)*i)  <= r_data_ds_in(4*npd*(i+1)-1 downto 4*npd*i);
+                r_data_in(rmi-1 downto rli)  <= r_data_ds_in(dsri-1 downto 4*npd*i);
             
-                r_rcv_reqs(r_up_ind-1 downto r_low_ind)      <= rcv_reqs_us(npu*(i+1)-1 downto npu*i);
+                r_rcv_reqs(rui-1 downto rmi) <= rcv_reqs_us(usri-1 downto npu*i);
-                r_rcv_reqs(r_low_ind-1 downto (4*npd+npu)*i) <= r_rcv_reqs_ds(4*npd*(i+1)-1 downto 4*npd*i);
+                r_rcv_reqs(rmi-1 downto rli) <= r_rcv_reqs_ds(dsri-1 downto 4*npd*i);
                 
-                r_snd_ack(r_up_ind-1 downto r_low_ind)       <= send_ack_us(npu*(i+1)-1 downto npu*i);
+                r_snd_ack(rui-1 downto rmi)  <= send_ack_us(usri-1 downto npu*i);
-                r_snd_ack(r_low_ind-1 downto (4*npd+npu)*i)  <= r_snd_ack_ds(4*npd*(i+1)-1 downto 4*npd*i);
+                r_snd_ack(rmi-1 downto rli)  <= r_snd_ack_ds(dsri-1 downto 4*npd*i);
 
                 -- outputs
-                r_rcv_ack_us(npu*(i+1)-1 downto npu*i)       <= r_rcv_ack(r_up_ind-1 downto r_low_ind);
+                r_rcv_ack_us(usri-1 downto npu*i)    <= r_rcv_ack(rui-1 downto rmi);
-                r_rcv_ack_ds(4*npd*(i+1)-1 downto 4*npd*i)   <= r_rcv_ack(r_low_ind-1 downto (4*npd+npu)*i);
+                r_rcv_ack_ds(dsri-1 downto 4*npd*i)  <= r_rcv_ack(rmi-1 downto rli);
                 
-                r_snd_reqs_us(npu*(i+1)-1 downto npu*i)      <= r_snd_reqs(r_up_ind-1 downto r_low_ind);
+                r_snd_reqs_us(usri-1 downto npu*i)   <= r_snd_reqs(rui-1 downto rmi);
-                r_snd_reqs_ds(4*npd*(i+1)-1 downto 4*npd*i)  <= r_snd_reqs(r_low_ind-1 downto (4*npd+npu)*i);
+                r_snd_reqs_ds(dsri-1 downto 4*npd*i) <= r_snd_reqs(rmi-1 downto rli);
                 
-                r_data_us_out(npu*(i+1)-1 downto npu*i)      <= r_data_out(r_up_ind-1 downto r_low_ind);
+                r_data_us_out(usri-1 downto npu*i)   <= r_data_out(rui-1 downto rmi);
-                r_data_ds_out(4*npd*(i+1)-1 downto 4*npd*i)  <= r_data_out(r_low_ind-1 downto (4*npd+npu)*i);
+                r_data_ds_out(dsri-1 downto 4*npd*i) <= r_data_out(rmi-1 downto rli);
             end loop;
         end process;
 
         g_elements: for i in 0 to 3 generate
             router_inst:  Router
             generic map(num_paths_up => npu, num_paths_down => npd, 
+                npu_bit_size => npu_bit_size-1, npd_bit_size => npd_bit_size-1,
                 level => level-1, buffer_width => buffer_width, 
                 buffer_depth => buffer_depth, fifo_ptr_size => fifo_ptr_size, 
                 chip_x => chip_x, chip_y => chip_y)
@@ -162,6 +168,7 @@ begin
 
             router_subtree: entity work.quadtree
             generic map(num_paths_up => npu, num_paths_down => npd,
+                npu_bit_size => npu_bit_size-1, npd_bit_size => npd_bit_size-1,
                 level => level-1, top_level => top_level, 
                 buffer_width => buffer_width,
                 buffer_depth => buffer_depth, fifo_ptr_size => fifo_ptr_size,

noc/quadtree_components.vhdl

@@ -6,12 +6,14 @@ use work.router_types.all;
 package quadtree_components is
     component Router is
     generic ( 
-        num_paths_up      :   integer := 1;
+        num_paths_up      :   positive := 1;
-        num_paths_down    :   integer := 1;
+        num_paths_down    :   positive := 1;
-        level             :   integer := 1;
+        npu_bit_size      :   positive := 2;
-        buffer_width      :   integer := 64;
+        npd_bit_size      :   positive := 1;
-        buffer_depth      :   integer := 4;
+        level             :   positive := 1;
-        fifo_ptr_size     :   integer := 3;
+        buffer_width      :   positive := 64;
+        buffer_depth      :   positive := 4;
+        fifo_ptr_size     :   positive := 3;
         chip_x            :   std_logic_vector(4 downto 0);
         chip_y            :   std_logic_vector(4 downto 0)
     );

router/NthLsbDetector.vhdl

@@ -4,8 +4,8 @@ use ieee.numeric_std.all;
 
 entity NthLsbDetector is
 generic(
-    num_dirs     :   integer := 2;
+    num_dirs     :   positive := 2;
-    n            :   integer := 1
+    n            :   positive := 1
 );
 port (
     dirs         :   in std_logic_vector(num_dirs-1 downto 0);

router/arbiter.vhdl

@@ -6,11 +6,14 @@ use work.routing_functions.all;
 
 entity arbiter is
 generic(
-    level               :   integer := 1;
+    level               :   positive := 1;
-    num_paths_up        :   integer := 2;
+    num_paths_up        :   positive := 2;
-    num_paths_down      :   integer := 1
+    num_paths_down      :   positive := 1;
+    lsb_size_up         :   positive := 2;
+    lsb_size_down       :   positive := 1
 );
 port (
+    clk, arstN      : in std_logic;
     chip_pos        : in t_chip_addr;
     core_pos        : in t_core_addr;
     packets         : in t_DATA(num_paths_up+num_paths_down*4-1 downto 0);
@@ -22,11 +25,38 @@ port (
 end arbiter;
 
 architecture impl of arbiter is
-    constant TOT_NUM_PATHS   :   integer := num_paths_up + num_paths_down*4;
+    constant TOT_NUM_PATHS   :   positive := num_paths_up + num_paths_down*4;
-    constant NUM_PORTS_UP    :   integer := 1;
+    constant NUM_PORTS_UP    :   positive := 1;
-    constant NUM_PORTS_DOWN  :   integer := 4;
+    constant NUM_PORTS_DOWN  :   positive := 4;
 
-    signal dirs          :  t_DATA_DIRS(TOT_NUM_PATHS-1 downto 0);
+    component arbiter_unit is
+    generic(
+        num_paths_in     :   positive;
+        num_paths_out    :   positive;
+        lsb_sels_size    :   positive
+    );
+    port (
+        dirs         :   in std_logic_vector(num_paths_in-1 downto 0);
+        packets      :   in t_DATA(num_paths_in-1 downto 0);
+        avai_paths   :   in std_logic_vector(num_paths_out-1 downto 0);
+        out_paths    :   out t_DATA(num_paths_out-1 downto 0);
+        valids_out   :   out std_logic_vector(num_paths_out-1 downto 0);
+        updated_dirs :   out std_logic_vector(num_paths_in-1 downto 0)
+    );
+    end component arbiter_unit;
+
+    type t_PORT_DIRS is array (natural range <>) of 
+                            std_logic_vector(TOT_NUM_PATHS-1 downto 0);
+    signal dirs              :   t_DATA_DIRS_EXT(TOT_NUM_PATHS-1 downto 0);
+    signal port_dirs         :   t_PORT_DIRS(NUM_DIRS_PARENT-1 downto 0);
+    signal updated_dirs      :   t_DATA_DIRS_EXT(TOT_NUM_PATHS-1 downto 0);
+    signal updated_port_dirs :   t_PORT_DIRS(NUM_DIRS_PARENT-1 downto 0);
+    signal ps_dirs           :   t_DATA_DIRS_EXT(TOT_NUM_PATHS-1 downto 0);
+    signal ps_dirs_nxt       :   t_DATA_DIRS_EXT(TOT_NUM_PATHS-1 downto 0);
+    signal out_packets       :   t_DATA(TOT_NUM_PATHS-1 downto 0);
+    signal packets_1d        :   t_DATA(TOT_NUM_PATHS-1 downto 0);
+    signal packets_1d_nxt    :   t_DATA(TOT_NUM_PATHS-1 downto 0);
+    signal valids_out        :   std_logic_vector(TOT_NUM_PATHS-1 downto 0);
 begin        
     decode_direction: process(chip_pos, core_pos, valid_data, packets)
         variable pack_dest   : t_pos_addr;
@@ -51,132 +81,85 @@ begin
         end loop;
     end process;
 
-    rout_path_determination: process(packets, dirs, avai_paths)
+    ds_ports_arbiter_units: for i in 0 to NUM_PORTS_DOWN-1 generate
-        variable sum_dirs          :   integer;
-        variable dir_index         :   integer;
-        variable avai_path         :   std_logic;
-        variable avai_pos_sizes    :   t_AVAI_POS_SIZES;
-        variable avai_index        :   integer;
-        variable ps_dirs           :   t_DATA_DIRS(TOT_NUM_PATHS-1 downto 0);
-        variable avai_pos          :   t_AVAI_POS(TOT_NUM_PATHS-1 downto 0);
-        variable path_index        :   integer;
-        variable out_index         :   integer;
     begin
-        avai_pos_sizes := (others => 0);
+        g_port_dirs: for p in 0 to TOT_NUM_PATHS-1 generate
-        avai_pos       := (others => 0);
+            port_dirs(i)(p) <= ps_dirs(p)(i);
-        -- find available paths and n_j (avai pos sizes)
+        end generate;
-        for j in 0 to NUM_PORTS_DOWN-1 loop
-            for i in 0 to num_paths_down-1 loop
-                avai_path := avai_paths(i+num_paths_down*j);
-                if avai_path = '1' then
-                    avai_index := avai_pos_sizes(j) + num_paths_down*j;
-                    avai_pos(avai_index) := i+num_paths_down*j;
-                    avai_pos_sizes(j) := avai_pos_sizes(j) + 1;
-                end if;
-            end loop;
-        end loop;
-        for j in NUM_PORTS_DOWN to NUM_PORTS_DOWN+NUM_PORTS_UP-1 loop
-            for i in 0 to num_paths_up-1 loop
-                avai_path := avai_paths(i+num_paths_down*4);--+num_paths_up*(j-NUM_PORTS_DOWN));
-                if avai_path = '1' then
-                    avai_index := avai_pos_sizes(j) + num_paths_down*4;
-                    avai_pos(avai_index) := i+num_paths_down*4;--+num_paths_up*(j-NUM_PORTS_DOWN);
-                    avai_pos_sizes(j) := avai_pos_sizes(j) + 1;
-                end if;
-            end loop;
-        end loop;
 
-        -- set rout_dirs to 0 when no more avai_pos (avai_pos_sizes(i) = 0)
+        ds_port_arbiter_unit: arbiter_unit
-        for i in 0 to TOT_NUM_PATHS-1  loop
+        generic map(
-            sum_dirs := 0;
+            num_paths_in => TOT_NUM_PATHS, 
-            for j in 0 to NUM_DIRS-1 loop
+            num_paths_out => num_paths_down,
-                sum_dirs := sum_dirs + to_integer(unsigned'('0' & dirs(i)(j)));
+            lsb_sels_size => lsb_size_down
-            end loop;
+        )
-            -- unicast
+        port map(
-            if sum_dirs = 1 then
+            dirs => port_dirs(i), 
-                dir_index := 0;
+            packets => packets_1d,
-                for j in 0 to NUM_DIRS-1 loop
+            avai_paths => avai_paths(num_paths_down*(i+1)-1 downto num_paths_down*i),
-                    if dirs(i)(j) = '1' then
+            out_paths => out_packets(num_paths_down*(i+1)-1 downto num_paths_down*i),
-                        dir_index := j;
+            valids_out => valids_out(num_paths_down*(i+1)-1 downto num_paths_down*i),
-                    end if;
+            updated_dirs => updated_port_dirs(i)
-                end loop;
+        );
-                if avai_pos_sizes(dir_index) <= 0 then
+    end generate;
-                    ps_dirs(i) := (others => '0');
-                else
-                    ps_dirs(i) := dirs(i);
-                    avai_pos_sizes(dir_index) := avai_pos_sizes(dir_index)-1;
-                end if;
-            -- 1 to 2 multicast
-            elsif sum_dirs = 2 then
-                if dirs(i)(1) = '1' and dirs(i)(3) = '1' then
-                    if avai_pos_sizes(1) <= 0 or avai_pos_sizes(3) <= 0 then
-                        ps_dirs(i) := (others => '0');
-                    else
-                        ps_dirs(i) := dirs(i);
-                        avai_pos_sizes(1) := avai_pos_sizes(1)-1;
-                        avai_pos_sizes(3) := avai_pos_sizes(3)-1;
-                    end if;
-                elsif dirs(i)(0) = '1' and dirs(i)(2) = '1' then
-                    if avai_pos_sizes(0) <= 0 or avai_pos_sizes(2) <= 0 then
-                        ps_dirs(i) := (others => '0');
-                    else
-                        ps_dirs(i) := dirs(i);
-                        avai_pos_sizes(0) := avai_pos_sizes(0)-1;
-                        avai_pos_sizes(2) := avai_pos_sizes(2)-1;
-                    end if;
-                elsif dirs(i)(2) = '1' and dirs(i)(3) = '1' then
-                    if avai_pos_sizes(2) <= 0 or avai_pos_sizes(3) <= 0 then
-                        ps_dirs(i) := (others => '0');
-                    else
-                        ps_dirs(i) := dirs(i);
-                        avai_pos_sizes(2) := avai_pos_sizes(2)-1;
-                        avai_pos_sizes(3) := avai_pos_sizes(3)-1;
-                    end if;
-                --elsif dirs(i)(1) = '1' and dirs(i)(2) = '1' then
-                else
-                    if avai_pos_sizes(0) <= 0 or avai_pos_sizes(1) <= 0 then
-                        ps_dirs(i) := (others => '0');
-                    else
-                        ps_dirs(i) := dirs(i);
-                        avai_pos_sizes(0) := avai_pos_sizes(0)-1;
-                        avai_pos_sizes(1) := avai_pos_sizes(1)-1;
-                    end if;
-                end if;
-            -- 1 to 4 multicast
-            elsif sum_dirs = 4 then
-                if avai_pos_sizes(0) <= 0 or avai_pos_sizes(1) <= 0 or 
-                        avai_pos_sizes(2) <= 0 or avai_pos_sizes(3) <= 0 then
-                    ps_dirs(i) := (others => '0');
-                else
-                    ps_dirs(i) := dirs(i);
-                    avai_pos_sizes(0) := avai_pos_sizes(0)-1;
-                    avai_pos_sizes(1) := avai_pos_sizes(1)-1;
-                    avai_pos_sizes(2) := avai_pos_sizes(2)-1;
-                    avai_pos_sizes(3) := avai_pos_sizes(3)-1;
-                end if;
-            else
-                ps_dirs(i) := (others => '0');
-            end if;
-        end loop;
 
-        -- set out buffer
+    g_port_dirs: for p in 0 to TOT_NUM_PATHS-1 generate
+        port_dirs(NUM_DIRS-1)(p) <= ps_dirs(p)(NUM_DIRS-1);
+    end generate;
+
+    u_port_arbiter_unit: arbiter_unit
+    generic map(
+        num_paths_in => TOT_NUM_PATHS, 
+        num_paths_out => num_paths_up,
+        lsb_sels_size => lsb_size_up
+    )
+    port map(
+        dirs => port_dirs(NUM_DIRS-1), 
+        packets => packets_1d,
+        avai_paths => avai_paths(num_paths_up+(NUM_DIRS-1)*num_paths_down-1 downto (NUM_DIRS-1)*num_paths_down),
+        out_paths => out_packets(num_paths_up+(NUM_DIRS-1)*num_paths_down-1 downto (NUM_DIRS-1)*num_paths_down),
+        valids_out => valids_out(num_paths_up+(NUM_DIRS-1)*num_paths_down-1 downto (NUM_DIRS-1)*num_paths_down),
+        updated_dirs => updated_port_dirs(NUM_DIRS-1)
+    );
+
+    g_set_buff_wr_in: for i in 0 to TOT_NUM_PATHS-1 generate
+        buff_wr_in(i).data   <= out_packets(i);
+        buff_wr_in(i).wr_req <= valids_out(i);
+    end generate;
+
+    g_updated_dirs: for p in 0 to TOT_NUM_PATHS-1 generate
+        g_updated_dir: for i in 0 to NUM_DIRS_PARENT-1 generate
+            updated_dirs(p)(i) <= updated_port_dirs(i)(p);
+        end generate;
+    end generate;
+
+    set_ps_dirs_nxt: process(dirs, updated_dirs, packets_1d, packets)
+        type t_OR_DIRS is array(natural range<>) of std_logic_vector(NUM_DIRS_PARENT-1 downto 0);
+        variable or_dirs :   t_OR_DIRS(TOT_NUM_PATHS-1 downto 0);
+    begin
         for i in 0 to TOT_NUM_PATHS-1 loop
-            buff_wr_in(i).data     <= (others => '0');
+            or_dirs(i)(0) := updated_dirs(i)(0);
-            buff_wr_in(i).wr_req   <= '0';
+            for j in 1 to NUM_DIRS_PARENT-1 loop
-            arb_complete(i)        <= '0';
+                or_dirs(i)(j) := or_dirs(i)(j-1) or updated_dirs(i)(j);
-        end loop;
-        for j in 0 to NUM_DIRS-1 loop
-            path_index := 0;
-            for i in 0 to TOT_NUM_PATHS-1 loop
-                if ps_dirs(i)(j)='1' then
-                    out_index  := retrieve_avai_path_index(j, path_index, 
-                                            num_paths_down, avai_pos);
-                    path_index := path_index + 1;
-                    buff_wr_in(out_index).data   <= packets(i);
-                    buff_wr_in(out_index).wr_req <= '1';
-                    arb_complete(i)              <= '1';
-                end if;
             end loop;
+            if or_dirs(i)(NUM_DIRS_PARENT-1) = '0' then
+                ps_dirs_nxt(i) <= dirs(i);
+                packets_1d_nxt(i) <= packets(i);
+            else
+                ps_dirs_nxt(i) <= updated_dirs(i);
+                packets_1d_nxt(i) <= packets_1d(i);
+            end if;
+            arb_complete(i) <= not or_dirs(i)(NUM_DIRS_PARENT-1);
         end loop;
     end process;
+
+    update_signals: process(arstN, clk)
+    begin
+        if arstN = '0' then
+            ps_dirs <= (others => (others => '0'));
+        elsif rising_edge(clk) then
+            ps_dirs <= ps_dirs_nxt;
+            packets_1d <= packets_1d_nxt;
+        end if;
+    end process;
 end impl;

router/arbiter_unit.vhdl

@@ -6,9 +6,9 @@ use work.encoder_components.all;
 
 entity arbiter_unit is
 generic(
-    num_paths_in     :   integer;
+    num_paths_in     :   positive := 2;
-    num_paths_out    :   integer;
+    num_paths_out    :   positive := 1;
-    lsb_sels_size    :   integer
+    lsb_sels_size    :   positive := 4
 );
 port (
     dirs         :   in std_logic_vector(num_paths_in-1 downto 0);
@@ -23,205 +23,132 @@ end arbiter_unit;
 architecture rtl of arbiter_unit is
     component NthLsbDetector is
     generic(
-        num_dirs     :   integer := 1;
+        num_dirs     :   positive := 1;
-        n            :   integer := 1
+        n            :   positive := 1
     );
     port (
         dirs         :   in std_logic_vector(num_dirs-1 downto 0);
         grant_dirs   :   out std_logic_vector(num_dirs-1 downto 0)
     );
     end component NthLsbDetector;
+
+    type t_N_LSB_SELS is array(natural range<>) of std_logic_vector(lsb_sels_size-1 downto 0); -- size depends on num_paths_out
+    type t_GRANT_DIRS is array(natural range<>) of std_logic_vector(num_paths_in-1 downto 0);
+    
+    signal n_lsb_sels        : t_N_LSB_SELS(num_paths_out-1 downto 0);
+    signal nlsb_grant_dirs   : t_GRANT_DIRS(num_paths_out-1 downto 0);
+    signal grant_dirs        : t_GRANT_DIRS(num_paths_out-1 downto 0);
 begin
-    g_L5_ArbiterUnit: if num_paths_in = 192 and (num_paths_out = 16 or num_paths_out = 32) generate
+    set_n_lsb_sel: process(avai_paths)
-        constant MUX_SIZE           : integer := 5;
+        type t_SUM_AVAI_PATHS is array(natural range<>) of integer range 0 to num_paths_out;
-        type t_N_LSB_SELS is array(natural range<>) of std_logic_vector(LSB_SELS_SIZE-1 downto 0); -- size depends on num_paths_out
-        type t_GRANT_DIRS is array(natural range<>) of std_logic_vector(num_paths_in-1 downto 0);
-        type t_SELECTORS is array(natural range<>) of std_logic_vector(MUX_SIZE-1 downto 0);
-        type t_GRANT_DIRS32 is array(natural range<>) of std_logic_vector(31 downto 0);
         
-        signal grant_dirs0       : t_GRANT_DIRS32(num_paths_out-1 downto 0);
+        variable sum_avai_paths : t_SUM_AVAI_PATHS(num_paths_out-1 downto 0);
-        signal grant_dirs1       : t_GRANT_DIRS32(num_paths_out-1 downto 0);
-        signal grant_dirs2       : t_GRANT_DIRS32(num_paths_out-1 downto 0);
-        signal grant_dirs3       : t_GRANT_DIRS32(num_paths_out-1 downto 0);
-        signal grant_dirs4       : t_GRANT_DIRS32(num_paths_out-1 downto 0);
-        signal grant_dirs5       : t_GRANT_DIRS32(num_paths_out-1 downto 0);
-        signal selectors0        : t_SELECTORS(num_paths_out-1 downto 0);
-        signal selectors1        : t_SELECTORS(num_paths_out-1 downto 0);
-        signal selectors2        : t_SELECTORS(num_paths_out-1 downto 0);
-        signal selectors3        : t_SELECTORS(num_paths_out-1 downto 0);
-        signal selectors4        : t_SELECTORS(num_paths_out-1 downto 0);
-        signal selectors5        : t_SELECTORS(num_paths_out-1 downto 0);
-        signal valids0           : std_logic_vector(num_paths_out-1 downto 0);
-        signal valids1           : std_logic_vector(num_paths_out-1 downto 0);
-        signal valids2           : std_logic_vector(num_paths_out-1 downto 0);
-        signal valids3           : std_logic_vector(num_paths_out-1 downto 0);
-        signal valids4           : std_logic_vector(num_paths_out-1 downto 0);
-        signal valids5           : std_logic_vector(num_paths_out-1 downto 0);
-        signal grant_dirs        : t_GRANT_DIRS(num_paths_out-1 downto 0);
-        signal nlsb_grant_dirs   : t_GRANT_DIRS(num_paths_out-1 downto 0);
-        signal n_lsb_sels        : t_N_LSB_SELS(num_paths_out-1 downto 0);
     begin
-        set_n_lsb_sel: process(avai_paths)
+        sum_avai_paths(0) := 0;
-            type t_SUM_AVAI_PATHS is array(natural range<>) of integer;
+        n_lsb_sels(0) <= (others => '0');
+        for i in 1 to num_paths_out-1 loop
+            if avai_paths(0) = '1' then
+                sum_avai_paths(i) := sum_avai_paths(i-1)+1;
+            else
+                sum_avai_paths(i) := sum_avai_paths(i-1);
+            end if;
+            n_lsb_sels(i) <= std_logic_vector(to_unsigned(sum_avai_paths(i), LSB_SELS_SIZE));
+        end loop;
+    end process;
 
-            variable sum_avai_paths : t_SUM_AVAI_PATHS(num_paths_out-1 downto 0);
+    g_NLSB_UNIT: for i in 0 to num_paths_out-1 generate
-        begin
+    nlsb_detector: NthLsbDetector
-            sum_avai_paths(0) := 0;
+        generic map(num_dirs => num_paths_in, n => i+1)
-            n_lsb_sels(0) <= (others => '0');
+        port map(dirs => dirs, grant_dirs => nlsb_grant_dirs(i));
-            for i in 1 to num_paths_out-1 loop
+    end generate;
-                if avai_paths(i) = '1' then
-                    sum_avai_paths(i) := sum_avai_paths(i-1)+1;
-                else
-                    sum_avai_paths(i) := sum_avai_paths(i-1);
-                end if;
-                n_lsb_sels(i) <= std_logic_vector(to_unsigned(sum_avai_paths(i), LSB_SELS_SIZE));
-            end loop;
-        end process;
 
-        g_NLSB_UNIT: for i in 0 to num_paths_out-1 generate
+    g_grant_dirs: for i in 0 to num_paths_out-1 generate
-        nlsb_detector: NthLsbDetector
+        grant_dirs(i) <= nlsb_grant_dirs(to_integer(unsigned(n_lsb_sels(i))));
-            generic map(num_dirs => num_paths_in, n => i+1)
+    end generate;
-            port map(dirs => dirs, grant_dirs => nlsb_grant_dirs(i));
-        end generate;
 
-        g_grant_dirs: for i in 0 to num_paths_out-1 generate
-            grant_dirs(i) <= nlsb_grant_dirs(to_integer(unsigned(n_lsb_sels(i))));
-        end generate;
 
+    g_L5_Encoders: if num_paths_in = 192 generate
+        constant MUX_SIZE           : positive := 5;
+        constant NUM_ENCODERS       : positive := 6;
+        type t_SELECTORS is array(natural range<>) of std_logic_vector(MUX_SIZE-1 downto 0);
+
+        signal selectors         : t_SELECTORS(NUM_ENCODERS*num_paths_out-1 downto 0);
+        signal valids            : std_logic_vector(NUM_ENCODERS*num_paths_out-1 downto 0);
+        signal packet_index      : integer range 0 to 192;
+    begin
         g_encoders: for i in 0 to num_paths_out-1 generate
         begin
-            grant_dirs0(i) <= grant_dirs(i)(31 downto 0);
+            g_encoder: for e in 0 to NUM_ENCODERS-1 generate
-            grant_dirs1(i) <= grant_dirs(i)(63 downto 32);
+                encoder32: encoder32to5
-            grant_dirs2(i) <= grant_dirs(i)(95 downto 64);
+                port map (din => grant_dirs(i)((e+1)*32-1 downto e*32), 
-            grant_dirs3(i) <= grant_dirs(i)(127 downto 96);
+                        dout => selectors(i+num_paths_out*(e+1)), 
-            grant_dirs4(i) <= grant_dirs(i)(159 downto 128);
+                        valid => valids(i+num_paths_out*(e+1)));
-            grant_dirs5(i) <= grant_dirs(i)(191 downto 160);
+            end generate;
 
-            encoder32_0: encoder32to5
+            packet_index <= 
-            port map (din => grant_dirs0(i), dout => selectors0(i), 
+                to_integer(unsigned(selectors(i))) when valids(i) = '1' else
-                    valid => valids0(i));
+                to_integer(unsigned(selectors(i+num_paths_out)))+32 
-            encoder32_1: encoder32to5
+                    when valids(i+num_paths_out) = '1' else
-            port map (din => grant_dirs1(i), dout => selectors1(i), 
+                to_integer(unsigned(selectors(i+num_paths_out*2)))+64
-                    valid => valids1(i));
+                    when valids(i+num_paths_out*2) = '1' else
-            encoder32_2: encoder32to5
+                to_integer(unsigned(selectors(i+num_paths_out*3)))+96
-            port map (din => grant_dirs2(i), dout => selectors2(i), 
+                    when valids(i+num_paths_out*3) = '1' else
-                    valid => valids2(i));
+                to_integer(unsigned(selectors(i+num_paths_out*4)))+128
-            encoder32_3: encoder32to5
+                    when valids(i+num_paths_out*4) = '1' else
-            port map (din => grant_dirs3(i), dout => selectors3(i), 
+                to_integer(unsigned(selectors(i+num_paths_out*5)))+160
-                    valid => valids3(i));
+                    when valids(i+num_paths_out*5) = '1' else 0;
-            encoder32_4: encoder32to5
-            port map (din => grant_dirs4(i), dout => selectors4(i), 
-                    valid => valids4(i));
-            encoder32_5: encoder32to5
-            port map (din => grant_dirs5(i), dout => selectors5(i), 
-                    valid => valids5(i));
 
-            set_outputs: process(selectors0, selectors1, selectors2, selectors3,
+            out_paths(i) <= packets(packet_index);
-                                    selectors4, selectors4, valids0, valids1,
+            valids_out(i) <= avai_paths(i) and (valids(i) or valids(i+num_paths_out) 
-                                    valids2, valids3, valids4, valids5, avai_paths)
+                        or valids(i+num_paths_out*2) or valids(i+num_paths_out*3) 
-                variable packet_index   :   integer;
+                        or valids(i+num_paths_out*4) or valids(i+num_paths_out*5));
-                variable is_valid       :   std_logic;
-            begin
-                is_valid := avai_paths(i) and (valids0(i) or valids1(i) or 
-                        valids2(i) or valids3(i) or valids4(i) or valids5(i));
-                if valids0(i) = '1' then
-                    packet_index := to_integer(unsigned(selectors0(i)));
-                elsif valids1(i) = '1' then
-                    packet_index := to_integer(unsigned(selectors1(i)))+32;
-                elsif valids2(i) = '1' then 
-                    packet_index := to_integer(unsigned(selectors2(i)))+64;
-                elsif valids3(i) = '1' then 
-                    packet_index := to_integer(unsigned(selectors3(i)))+96;
-                elsif valids4(i) = '1' then 
-                    packet_index := to_integer(unsigned(selectors4(i)))+128;
-                elsif valids5(i) = '1' then 
-                    packet_index := to_integer(unsigned(selectors5(i)))+160;
-                else
-                    packet_index := 0;
-                end if;
-                if is_valid = '1' then
-                    out_paths(i) <= packets(packet_index);
-                else 
-                    out_paths(i) <= (others => '0');
-                end if;
-                valids_out(i) <= is_valid;
-            end process;
         end generate;
 
-        set_updated_dirs: process(dirs, selectors0, selectors1, selectors2, 
+        set_updated_dirs: process(dirs, selectors, valids, avai_paths)
-                                    selectors3, selectors4, selectors5,
+            variable updated_dirs_index :   integer range 0 to 192;
-                                    valids0, valids1, valids2, valids3,
-                                    valids4, valids5, avai_paths)
         begin
             updated_dirs <= dirs;
             for i in 0 to num_paths_out-1 loop
                 if avai_paths(i) = '1' then
-                    if valids0(i) = '1' then
+                    if valids(i) = '1' then
-                        updated_dirs(to_integer(unsigned(selectors0(i)))) <= '0';
+                        updated_dirs_index := to_integer(unsigned(selectors(i)));
-                    elsif valids1(i) = '1' then
+                        updated_dirs(updated_dirs_index) <= '0';
-                        updated_dirs(to_integer(unsigned(selectors1(i)))+32) <= '0';
+                    elsif valids(i+num_paths_out) = '1' then
-                    elsif valids2(i) = '1' then
+                        updated_dirs_index := to_integer(unsigned(selectors(i+num_paths_out)));
-                        updated_dirs(to_integer(unsigned(selectors2(i)))+64) <= '0';
+                        updated_dirs(updated_dirs_index+32) <= '0';
-                    elsif valids3(i) = '1' then
+                    elsif valids(i+num_paths_out*2) = '1' then
-                        updated_dirs(to_integer(unsigned(selectors3(i)))+96) <= '0';
+                        updated_dirs_index := to_integer(unsigned(selectors(i+num_paths_out*2)));
-                    elsif valids4(i) = '1' then
+                        updated_dirs(updated_dirs_index+64) <= '0';
-                        updated_dirs(to_integer(unsigned(selectors4(i)))+128) <= '0';
+                    elsif valids(i+num_paths_out*3) = '1' then
-                    elsif valids5(i) = '1' then
+                        updated_dirs_index := to_integer(unsigned(selectors(i+num_paths_out*3)));
-                        updated_dirs(to_integer(unsigned(selectors5(i)))+160) <= '0';
+                        updated_dirs(updated_dirs_index+96) <= '0';
-                    end if; -- else?
+                    elsif valids(i+num_paths_out*4) = '1' then
+                        updated_dirs_index := to_integer(unsigned(selectors(i+num_paths_out*4)));
+                        updated_dirs(updated_dirs_index+128) <= '0';
+                    elsif valids(i+num_paths_out*5) = '1' then
+                        updated_dirs_index := to_integer(unsigned(selectors(i+num_paths_out*5)));
+                        updated_dirs(updated_dirs_index+160) <= '0';
+                    end if;
                 end if;
             end loop;
         end process;
     end generate;
 
-    g_L4_ArbiterUnit: if num_paths_in < 64 and num_paths_in > 32 and (num_paths_out = 8 or num_paths_out = 16) generate
+    g_L4_Encoders: if num_paths_in < 64 generate
-        constant MUX_SIZE           : integer := 5;
+        constant MUX_SIZE           : positive := 5;
-        --constant LSB_SELS_SIZE      : integer := 3;
-        type t_N_LSB_SELS is array(natural range<>) of std_logic_vector(LSB_SELS_SIZE-1 downto 0); -- size depends on num_paths_out
-        type t_GRANT_DIRS is array(natural range<>) of std_logic_vector(num_paths_in-1 downto 0);
         type t_SELECTORS is array(natural range<>) of std_logic_vector(MUX_SIZE-1 downto 0);
 
         signal selectors0        :   t_SELECTORS(num_paths_out-1 downto 0);
         signal selectors1        :   t_SELECTORS(num_paths_out-1 downto 0);
         signal valids0           :   std_logic_vector(num_paths_out-1 downto 0);
         signal valids1           :   std_logic_vector(num_paths_out-1 downto 0);
-        signal grant_dirs        :   t_GRANT_DIRS(num_paths_out-1 downto 0);
-        signal nlsb_grant_dirs   :   t_GRANT_DIRS(num_paths_out-1 downto 0);
-        signal n_lsb_sels        :   t_N_LSB_SELS(num_paths_out-1 downto 0);
     begin
-        set_n_lsb_sel: process(avai_paths)
-            type t_SUM_AVAI_PATHS is array(natural range<>) of integer;
-            
-            variable sum_avai_paths : t_SUM_AVAI_PATHS(num_paths_out-1 downto 0);
-        begin
-            sum_avai_paths(0) := 0;
-            n_lsb_sels(0) <= (others => '0');
-            for i in 1 to num_paths_out-1 loop
-                if avai_paths(0) = '1' then
-                    sum_avai_paths(i) := sum_avai_paths(i-1)+1;
-                else
-                    sum_avai_paths(i) := sum_avai_paths(i-1);
-                end if;
-                n_lsb_sels(i) <= std_logic_vector(to_unsigned(sum_avai_paths(i), LSB_SELS_SIZE));
-            end loop;
-        end process;
-
-        g_NLSB_UNIT: for i in 0 to num_paths_out-1 generate
-        nlsb_detector: NthLsbDetector
-            generic map(num_dirs => num_paths_in, n => i+1)
-            port map(dirs => dirs, grant_dirs => nlsb_grant_dirs(i));
-        end generate;
-        
-        g_grant_dirs: for i in 0 to num_paths_out-1 generate
-            grant_dirs(i) <= nlsb_grant_dirs(to_integer(unsigned(n_lsb_sels(i))));
-        end generate;
-
         g_encoders: for i in 0 to num_paths_out-1 generate
             type t_GRANT_DIRS32 is array(natural range<>) of std_logic_vector(31 downto 0);
             
             signal grant_dirs0  : t_GRANT_DIRS32(num_paths_out-1 downto 0);
             signal grant_dirs1  : t_GRANT_DIRS32(num_paths_out-1 downto 0);
-            signal packet_index : integer;
+            signal packet_index : integer range 0 to num_paths_in;
         begin
             grant_dirs0(i) <= grant_dirs(i)(31 downto 0);
             grant_dirs1(i)(num_paths_out-33 downto 0) <= grant_dirs(i)(num_paths_out-1 downto 32);
@@ -240,155 +167,107 @@ begin
                                 when valids1(i) = '1' else 0;
 
             valids_out(i) <= valids0(i) or valids1(i);
-            out_paths(i) <= packets(packet_index) when avai_paths(i) = '1' else 
+            out_paths(i) <= packets(packet_index);
-                            (others => '0');
         end generate;
 
-        set_updated_dirs: process(dirs, selectors0, selectors1)
+        set_updated_dirs: process(dirs, selectors0, selectors1, valids0, valids1, avai_paths)
+            variable updated_dirs_index :   integer range 0 to num_paths_in;
         begin
             updated_dirs <= dirs;
             for i in 0 to num_paths_out-1 loop
                 if avai_paths(i) = '1' then
                     if valids0(i) = '1' then
-                        updated_dirs(to_integer(unsigned(selectors0(i)))) <= '0';
+                        updated_dirs_index := to_integer(unsigned(selectors0(i)));
+                        updated_dirs(updated_dirs_index) <= '0';
                     elsif valids1(i) = '1' then
-                        updated_dirs(to_integer(unsigned(selectors1(i)))) <= '0';
+                        updated_dirs_index := to_integer(unsigned(selectors1(i)));
-                    end if; -- else?
+                        updated_dirs(updated_dirs_index+32) <= '0';
+                    end if;
                 end if;
             end loop;
         end process;
     end generate;
 
-    g_L3_ArbiterUnit: if num_paths_in < 32 and (num_paths_out = 4 or num_paths_out = 8) generate
+    g_L3_Encoders: if num_paths_in < 32 generate
-        constant PATH_MUX_SIZE : integer := 5;
+        constant PATH_MUX_SIZE : positive := 5;
-        --constant LSB_SELS_SIZE : integer := 2;
-        type t_N_LSB_SELS is array(natural range<>) of std_logic_vector(LSB_SELS_SIZE-1 downto 0); -- size depends on num_paths_out
-        type t_GRANT_DIRS is array(natural range<>) of std_logic_vector(num_paths_in-1 downto 0);
         type t_SELECTORS is array(natural range<>) of std_logic_vector(PATH_MUX_SIZE-1 downto 0);
 
         signal selectors         :   t_SELECTORS(num_paths_out-1 downto 0);
-        signal grant_dirs        :   t_GRANT_DIRS(num_paths_out-1 downto 0);
-        signal nlsb_grant_dirs   :   t_GRANT_DIRS(num_paths_out-1 downto 0);
-        signal n_lsb_sels        :   t_N_LSB_SELS(num_paths_out-1 downto 0);
     begin
-        set_n_lsb_sel: process(avai_paths)
-            type t_SUM_AVAI_PATHS is array(natural range<>) of integer;
-            
-            variable sum_avai_paths : t_SUM_AVAI_PATHS(num_paths_out-1 downto 0);
-        begin
-            sum_avai_paths(0) := 0;
-            n_lsb_sels(0) <= (others => '0');
-            for i in 1 to num_paths_out-1 loop
-                if avai_paths(0) = '1' then
-                    sum_avai_paths(i) := sum_avai_paths(i-1)+1;
-                else
-                    sum_avai_paths(i) := sum_avai_paths(i-1);
-                end if;
-                n_lsb_sels(i) <= std_logic_vector(to_unsigned(sum_avai_paths(i), LSB_SELS_SIZE));
-            end loop;
-        end process;
-
-        g_NLSB_UNIT: for i in 0 to num_paths_out-1 generate
-        nlsb_detector: NthLsbDetector
-            generic map(num_dirs => num_paths_in, n => i+1)
-            port map(dirs => dirs, grant_dirs => nlsb_grant_dirs(i));
-        end generate;
-        
-        g_grant_dirs: for i in 0 to num_paths_out-1 generate
-            grant_dirs(i) <= nlsb_grant_dirs(to_integer(unsigned(n_lsb_sels(i))));
-        end generate;
-        
         g_encoders: for i in 0 to num_paths_out-1 generate
+            signal packet_index : integer range 0 to num_paths_in;
         begin
             encoder32: encoder32to5
             port map (din => grant_dirs(i), dout => selectors(i), 
                     valid => valids_out(i));
-
+            packet_index <= to_integer(unsigned(selectors(i)));
-            out_paths(i) <= packets(to_integer(unsigned(selectors(i)))) when
+            out_paths(i) <= packets(packet_index) when avai_paths(i) = '1' else 
-                        avai_paths(i) = '1' else (others => '0');
+                            (others => '0');
         end generate;
 
-        set_updated_dirs: process(dirs, selectors)
+        set_updated_dirs: process(dirs, selectors, avai_paths, valids_out)
         begin
             updated_dirs <= dirs;
             for i in 0 to num_paths_out-1 loop
-                if avai_paths(i) = '1' then
+                if avai_paths(i) = '1' and valids_out(i) = '1' then
                     updated_dirs(to_integer(unsigned(selectors(i)))) <= '0';
                 end if;
             end loop;
         end process;
     end generate;
 
-    -- UPDATE L2 AND l1
+    g_L2_Encoders: if num_paths_in < 16 generate
-    g_L2_ArbiterUnit: if num_paths_in < 16 and (num_paths_out = 2 or num_paths_out = 4) generate
+        constant PATH_MUX_SIZE : positive := 4;
-        constant PATH_MUX_SIZE : integer := 4;
-        type t_N_LSB_SELS is array(natural range<>) of std_logic_vector(0 downto 0);
-        type t_GRANT_DIRS is array(natural range<>) of std_logic_vector(num_paths_in-1 downto 0);
         type t_SELECTORS is array(natural range<>) of std_logic_vector(PATH_MUX_SIZE-1 downto 0);
-
         signal selectors         :   t_SELECTORS(num_paths_out-1 downto 0);
-        signal grant_dirs        :   t_GRANT_DIRS(num_paths_out-1 downto 0);
-        signal nlsb_grant_dirs   :   t_GRANT_DIRS(num_paths_out-1 downto 0);
-        signal n_lsb_sels        :   t_N_LSB_SELS(num_paths_out-1 downto 0);
     begin
-        n_lsb_sels(0) <= "0";
-        n_lsb_sels(1) <= "1" when avai_paths(0)='1' and avai_paths(1)='1' else "0";
-
-        g_NLSB_UNIT: for i in 0 to num_paths_out-1 generate
-        nlsb_detector: NthLsbDetector
-            generic map(num_dirs => num_paths_in, n => i+1)
-            port map(dirs => dirs, grant_dirs => nlsb_grant_dirs(i));
-        end generate;
-        
-        g_grant_dirs: for i in 0 to num_paths_out-1 generate
-            grant_dirs(i) <= nlsb_grant_dirs(to_integer(unsigned(n_lsb_sels(i))));
-        end generate;
-
         g_encoders: for i in 0 to num_paths_out-1 generate
+            signal packet_index : integer range 0 to num_paths_in;
         begin
             encoder16: encoder16to4
             port map (din => grant_dirs(i), dout => selectors(i), 
                 valid => valids_out(i));
+            
+            packet_index <= to_integer(unsigned(selectors(i)));
+            out_paths(i) <= packets(packet_index) when avai_paths(i) = '1' else 
+                            (others => '0');
         end generate;
 
-        set_updated_dirs: process(dirs, selectors)
+        set_updated_dirs: process(dirs, selectors, avai_paths, valids_out)
         begin
             updated_dirs <= dirs;
-            if avai_paths(0) = '1' then
+            for i in 0 to num_paths_out-1 loop
-                updated_dirs(to_integer(unsigned(selectors(0)))) <= '0';
+                if avai_paths(i) = '1' and valids_out(i) = '1' then
-            end if;
+                    updated_dirs(to_integer(unsigned(selectors(i)))) <= '0';
-            if avai_paths(1) = '1' then
+                end if;
-                updated_dirs(to_integer(unsigned(selectors(1)))) <= '0';
+            end loop;
-            end if;
         end process;
-
-        out_paths(0) <= packets(to_integer(unsigned(selectors(0)))) when
-                    avai_paths(0) = '1' else (others => '0');
-        out_paths(1) <= packets(to_integer(unsigned(selectors(1)))) when
-                    avai_paths(1) = '1' else (others => '0');
     end generate;
 
-    g_L1_ArbiterUnit: if num_paths_in < 8 and (num_paths_out = 1 or num_paths_out = 2) generate
+    g_L1_Encoders: if num_paths_in < 8 generate
-        signal grant_dirs        :   std_logic_vector(num_paths_in-1 downto 0);
+        constant PATH_MUX_SIZE : positive := 3;
-        signal selector          :   std_logic_vector(2 downto 0);
+        type t_SELECTORS is array(natural range<>) of std_logic_vector(PATH_MUX_SIZE-1 downto 0);
-        signal n_lsb_sel         :   std_logic_vector(0 downto 0);
+        signal selectors         : t_SELECTORS(6*num_paths_out-1 downto 0);
     begin
-        nlsb_detector: NthLsbDetector
+        g_encoders: for i in 0 to num_paths_out-1 generate
-            generic map(num_dirs => num_paths_in, n => 1)
+            signal packet_index : integer range 0 to num_paths_in;
-            port map(dirs => dirs, grant_dirs => grant_dirs);
+        begin
+            encoder8: encoder8to3
+            port map(din=>grant_dirs(i), dout=>selectors(i),valid=>valids_out(i));
 
-        encoder8: encoder8to3
+            packet_index <= to_integer(unsigned(selectors(i))) 
-            port map (din => grant_dirs, dout => selector, valid => valids_out(0));
+                    when avai_paths(i) = '1' and valids_out(i) = '1' else 0;
+            out_paths(i) <= packets(packet_index);
+        end generate;
 
-        set_updated_dirs: process(dirs, selector)
+        set_updated_dirs: process(dirs, selectors, avai_paths, valids_out)
         begin
             updated_dirs <= dirs;
-            if avai_paths(0) = '1' then
+            for i in 0 to num_paths_out-1 loop
-                updated_dirs(to_integer(unsigned(selector))) <= '0';
+                if avai_paths(i) = '1' and valids_out(i) = '1' then
-            end if;
+                    updated_dirs(to_integer(unsigned(selectors(i)))) <= '0';
+                end if;
+            end loop;
         end process;
-
-        out_paths(0) <= packets(to_integer(unsigned(selector))) when
-                    avai_paths(0) = '1' else (others => '0');
     end generate;
 end rtl;

router/fifo.vhdl

@@ -5,9 +5,9 @@ use ieee.numeric_std.all;
 --------------------------------------------------------
 entity fifo is
     generic (
-        WIDTH           : integer := 32;
+        WIDTH           : positive := 32;
-        DEPTH           : integer := 8;
+        DEPTH           : positive := 8;
-        F_PTR_SIZE      : integer := 4
+        F_PTR_SIZE      : positive := 4
     );
     port(
         arstN, clk, wr_req, rd_req  : in std_logic;
@@ -19,6 +19,7 @@ end fifo;
 
 --------------------------------------------------------
 architecture impl of fifo is
+constant one    :   unsigned(DEPTH-1 downto 0) := to_unsigned(1, DEPTH);
 type T_FIFO is array (0 to DEPTH-1) of std_logic_vector(WIDTH-1 downto 0);
 
 signal wr_ptr, rd_ptr           :   unsigned(F_PTR_SIZE-1 downto 0);
@@ -47,25 +48,12 @@ begin
         end if;
     end process;
 
-    select_fifo_for_writing: process(wr_req, s_full, wr_ptr)
+    g_write_mux: for i in 0 to DEPTH-1 generate
-        constant one    :   unsigned(DEPTH-1 downto 0) := to_unsigned(1, DEPTH);
+        fifo_nxt(i) <= data_in when fifo_sel(i) = '1' else fifo(i);
-    begin
+    end generate;
-        fifo_sel <= (others => '0');
-        if wr_req = '1' and s_full = '0' then
-            fifo_sel <= std_logic_vector(shift_left(one, to_integer(wr_ptr(F_PTR_SIZE-2 downto 0))));
-        end if;
-    end process;
 
-    write: process(fifo_sel, fifo, data_in)
+    fifo_sel <= std_logic_vector(shift_left(one, to_integer(wr_ptr(F_PTR_SIZE-2 downto 0)))) 
-    begin
+            when wr_req = '1' and s_full = '0'  else (others => '0');
-        for i in 0 to DEPTH-1 loop
-            if fifo_sel(i) = '1' then
-                fifo_nxt(i) <= data_in;
-            else
-                fifo_nxt(i) <= fifo(i);
-            end if;
-        end loop;
-    end process write;
 
     data_out_nxt <= fifo(to_integer(rd_ptr(F_PTR_SIZE-2 downto 0)));
     

router/parent_arbiter.vhdl

@@ -6,9 +6,11 @@ use work.routing_functions.all;
 
 entity parent_arbiter is
 generic(
-    level               :   integer := 5;
+    level               :   positive := 5;
-    num_paths_up        :   integer := 32;
+    num_paths_up        :   positive := 32;
-    num_paths_down      :   integer := 16
+    num_paths_down      :   positive := 16;
+    lsb_size_up         :   positive := 5;
+    lsb_size_down       :   positive := 4
 );
 port (
     clk, arstN      : in std_logic;
@@ -23,15 +25,15 @@ port (
 end parent_arbiter;
 
 architecture impl of parent_arbiter is
-    constant TOT_NUM_PATHS   :   integer := num_paths_up*4 + num_paths_down*4;
+    constant TOT_NUM_PATHS   :   positive := num_paths_up*4 + num_paths_down*4;
-    constant NUM_PORTS_UP    :   integer := 4;
+    constant NUM_PORTS_UP    :   positive := 4;
-    constant NUM_PORTS_DOWN  :   integer := 4;
+    constant NUM_PORTS_DOWN  :   positive := 4;
 
     component arbiter_unit is
     generic(
-        num_paths_in     :   integer;
+        num_paths_in     :   positive;
-        num_paths_out    :   integer;
+        num_paths_out    :   positive;
-        lsb_sels_size    :   integer
+        lsb_sels_size    :   positive
     );
     port (
         dirs         :   in std_logic_vector(num_paths_in-1 downto 0);
@@ -80,18 +82,15 @@ begin
 
     ds_ports_arbiter_units: for i in 0 to NUM_PORTS_DOWN-1 generate
     begin
-        set_port_dirs: process(ps_dirs)
+        g_port_dirs: for p in 0 to TOT_NUM_PATHS-1 generate
-        begin
+            port_dirs(i)(p) <= ps_dirs(p)(i);
-            for p in 0 to TOT_NUM_PATHS-1 loop
+        end generate;
-                port_dirs(i)(p) <= ps_dirs(p)(i);
-            end loop;
-        end process;
 
         ds_port_arbiter_unit: arbiter_unit
         generic map(
             num_paths_in => TOT_NUM_PATHS, 
             num_paths_out => num_paths_down,
-            lsb_sels_size => 4
+            lsb_sels_size => lsb_size_down
         )
         port map(
             dirs => port_dirs(i), 
@@ -104,20 +103,17 @@ begin
     end generate;
 
     us_ports_arbiter_units: for i in 0 to NUM_PORTS_UP-1 generate
-        constant NPOD       :   integer := NUM_PORTS_DOWN;
+        constant NPOD       :   positive := NUM_PORTS_DOWN;
     begin
-        set_port_dirs: process(ps_dirs)
+        g_port_dirs: for p in 0 to TOT_NUM_PATHS-1 generate
-        begin
+            port_dirs(i+NPOD)(p) <= ps_dirs(p)(i+NPOD);
-            for p in 0 to TOT_NUM_PATHS-1 loop
+        end generate;
-                port_dirs(i+NPOD)(p) <= ps_dirs(p)(i+NPOD);
-            end loop;
-        end process;
 
         u_port_arbiter_unit: arbiter_unit
         generic map(
             num_paths_in => TOT_NUM_PATHS, 
             num_paths_out => num_paths_up,
-            lsb_sels_size => 5
+            lsb_sels_size => lsb_size_up
         )
         port map(
             dirs => port_dirs(i+NPOD), 
@@ -134,14 +130,11 @@ begin
         buff_wr_in(i).wr_req <= valids_out(i);
     end generate;
 
-    set_updated_dirs: process(updated_port_dirs)
+    g_updated_dirs: for p in 0 to TOT_NUM_PATHS-1 generate
-    begin
+        g_updated_dir: for i in 0 to NUM_DIRS_PARENT-1 generate
-        for p in 0 to TOT_NUM_PATHS-1 loop
+            updated_dirs(p)(i) <= updated_port_dirs(i)(p);
-            for i in 0 to NUM_DIRS_PARENT-1 loop
+        end generate;
-                updated_dirs(p)(i) <= updated_port_dirs(i)(p);
+    end generate;
-            end loop;
-        end loop;
-    end process;
 
     set_ps_dirs_nxt: process(dirs, updated_dirs, packets_1d, packets)
         type t_OR_DIRS is array(natural range<>) of std_logic_vector(NUM_DIRS_PARENT-1 downto 0);

router/parent_router.vhdl

@@ -7,12 +7,14 @@ use work.router_components.all;
 
 entity parent_router is
 generic ( 
-    num_paths_up      :   integer := 32;
+    num_paths_up      :   positive := 32;
-    num_paths_down    :   integer := 16;
+    num_paths_down    :   positive := 16;
-    level             :   integer := 5;
+    npu_bit_size      :   positive := 5;
-    buffer_width      :   integer := 64;
+    npd_bit_size      :   positive := 4;
-    buffer_depth      :   integer := 4;
+    level             :   positive := 5;
-    fifo_ptr_size     :   integer := 3;
+    buffer_width      :   positive := 64;
+    buffer_depth      :   positive := 4;
+    fifo_ptr_size     :   positive := 3;
     chip_x            :   std_logic_vector(4 downto 0) := "00000";
     chip_y            :   std_logic_vector(4 downto 0) := "00000"
 );
@@ -33,7 +35,7 @@ port (
 end parent_router;
 
 architecture impl of parent_router is
-    constant TOT_NUM_PATHS      :   integer := num_paths_up*4 + num_paths_down*4;
+    constant TOT_NUM_PATHS      :   positive := num_paths_up*4 + num_paths_down*4;
     constant chip_pos           :   t_chip_addr := (x => chip_x, y=> chip_y);
     
     signal core_pos             :   t_core_addr;
@@ -118,7 +120,9 @@ begin
     generic map(
         level => level, 
         num_paths_up=>num_paths_up, 
-        num_paths_down=>num_paths_down
+        num_paths_down=>num_paths_down,
+        lsb_size_up => npu_bit_size,
+        lsb_size_down => npd_bit_size
     )
     port map(
         clk                 => clk,
@@ -132,19 +136,13 @@ begin
         buff_wr_in          => snd_buff_wr_in
     );
 
-    set_rcv_accept_ack: process(rcv_buff_out)
+    g_rcv_accept_ack: for i in 0 to TOT_NUM_PATHS-1 generate
-    begin
+        rcv_accept_ack(i) <= not rcv_buff_out(i).full;
-        for i in 0 to TOT_NUM_PATHS-1 loop
+    end generate;
-            rcv_accept_ack(i) <= not rcv_buff_out(i).full;
-        end loop;
-    end process;
 
-    process_snd_buff_out: process(snd_buff_out)
+    g_snd_buff_out: for i in 0 to TOT_NUM_PATHS-1 generate
-    begin
+        avai_paths(i)       <= not snd_buff_out(i).full;
-        for i in 0 to TOT_NUM_PATHS-1 loop
+    end generate;
-            avai_paths(i)       <= not snd_buff_out(i).full;
-        end loop;
-    end process;
 
     read_out_buff_sm_next_logic: process(outb_rd_states, snd_buff_out, snd_buff_rd_in)
     begin
@@ -162,8 +160,6 @@ begin
                     else
                         outb_rd_states_nxt(i) <= WaitForSender;
                     end if;
-                --when Sending =>
-                --    outb_rd_states_nxt(i) <= WaitForSender;
                 when WaitForSender =>
                     if snd_buff_rd_in(i) = '1' then
                         if snd_buff_out(i).empty = '1' then
@@ -187,9 +183,6 @@ begin
                 when StartRead =>
                     continue_send(i) <= '1';
                     out_buff_rd_reqs(i) <= '1';
-                --when Sending =>
-                --    continue_send(i) <= '1';
-                --    out_buff_rd_reqs(i) <= '0';
                 when others =>
                     continue_send(i) <= '0';
                     out_buff_rd_reqs(i) <= '0';

router/router.vhdl

@@ -7,12 +7,14 @@ use work.router_components.all;
 
 entity router is
 generic ( 
-    num_paths_up      :   integer := 1;
+    num_paths_up      :   positive := 2;
-    num_paths_down    :   integer := 1;
+    num_paths_down    :   positive := 1;
-    level             :   integer := 1;
+    npu_bit_size      :   positive := 2;
-    buffer_width      :   integer := 64;
+    npd_bit_size      :   positive := 1;
-    buffer_depth      :   integer := 4;
+    level             :   positive := 1;
-    fifo_ptr_size     :   integer := 3;
+    buffer_width      :   positive := 64;
+    buffer_depth      :   positive := 4;
+    fifo_ptr_size     :   positive := 3;
     chip_x            :   std_logic_vector(DEST_ADDR_SIZE-1 downto 0) := "00000";
     chip_y            :   std_logic_vector(DEST_ADDR_SIZE-1 downto 0) := "00000"
 );
@@ -31,7 +33,7 @@ port (
 end router;
 
 architecture impl of router is
-    constant TOT_NUM_PATHS      :   integer := num_paths_up + num_paths_down*4;
+    constant TOT_NUM_PATHS      :   positive := num_paths_up + num_paths_down*4;
     constant chip_pos           :   t_chip_addr := (x => chip_x, y=> chip_y);
 
     signal core_pos             :   t_core_addr;
@@ -95,9 +97,13 @@ begin
     generic map(
         level => level, 
         num_paths_up=>num_paths_up, 
-        num_paths_down=>num_paths_down
+        num_paths_down=>num_paths_down,
+        lsb_size_up=>npu_bit_size,
+        lsb_size_down=>npd_bit_size
     )
     port map(
+        clk                 => clk,
+        arstN               => arstN,
         chip_pos            => chip_pos,
         core_pos            => core_pos,
         packets             => rd_data,
@@ -107,19 +113,13 @@ begin
         buff_wr_in          => snd_buff_wr_in
     );
 
-    set_rcv_accept_ack: process(rcv_buff_out)
+    g_cv_accept_ack: for i in 0 to TOT_NUM_PATHS-1 generate
-    begin
+        rcv_accept_ack(i) <= not rcv_buff_out(i).full;
-        for i in 0 to TOT_NUM_PATHS-1 loop
+    end generate;
-            rcv_accept_ack(i) <= not rcv_buff_out(i).full;
-        end loop;
-    end process;
 
-    process_snd_buff_out: process(snd_buff_out)
+    g_snd_buff_out: for i in 0 to TOT_NUM_PATHS-1 generate
-    begin
+        avai_paths(i) <= not snd_buff_out(i).full;
-        for i in 0 to TOT_NUM_PATHS-1 loop
+    end generate;
-            avai_paths(i)       <= not snd_buff_out(i).full;
-        end loop;
-    end process;
 
     read_out_buff_sm_next_logic: process(outb_rd_states, snd_buff_out, snd_buff_rd_in)
     begin
@@ -137,8 +137,6 @@ begin
                     else
                         outb_rd_states_nxt(i) <= WaitForSender;
                     end if;
-                --when Sending =>
-                --    outb_rd_states_nxt(i) <= WaitForSender;
                 when WaitForSender =>
                     if snd_buff_rd_in(i) = '1' then
                         if snd_buff_out(i).empty = '1' then
@@ -162,9 +160,6 @@ begin
                 when StartRead =>
                     continue_send(i) <= '1';
                     out_buff_rd_reqs(i) <= '1';
-                --when Sending =>
-                --    continue_send(i) <= '1';
-                --    out_buff_rd_reqs(i) <= '0';
                 when others =>
                     continue_send(i) <= '0';
                     out_buff_rd_reqs(i) <= '0';

router/router_components.vhdl

@@ -6,9 +6,9 @@ use work.router_types.all;
 package router_components is
     component fifo is
         generic (
-            WIDTH       : integer;
+            WIDTH       : positive;
-            DEPTH       : integer;
+            DEPTH       : positive;
-            F_PTR_SIZE  : integer
+            F_PTR_SIZE  : positive
         );
         port(   
             arstN, clk, wr_req, rd_req  : in std_logic;
@@ -38,11 +38,14 @@ package router_components is
 
     component arbiter is
         generic(
-            level               :   integer := 1;
+            level               :   positive := 1;
-            num_paths_up        :   integer := 1;
+            num_paths_up        :   positive := 1;
-            num_paths_down      :   integer := 1
+            num_paths_down      :   positive := 1;
+            lsb_size_up         :   positive := 2;
+            lsb_size_down       :   positive := 1
         );
         port (
+            clk, arstN        : in std_logic;
             chip_pos          : in t_chip_addr;
             core_pos          : in t_core_addr;
             packets           : in t_DATA(num_paths_up+num_paths_down*4-1 downto 0);
@@ -59,9 +62,11 @@ package router_components is
 
     component parent_arbiter is
     generic(
-        level               :   integer := 5;
+        level               :   positive := 5;
-        num_paths_up        :   integer := 32;
+        num_paths_up        :   positive := 32;
-        num_paths_down      :   integer := 16
+        num_paths_down      :   positive := 16;
+        lsb_size_up         :   positive := 5;
+        lsb_size_down       :   positive := 4
     );
     port (
         clk, arstN      : in std_logic;

router/router_types.vhdl

@@ -3,37 +3,24 @@ use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
 
 package router_types is
-    constant BUFF_SIZE_IN       :   integer  :=  8;
+    constant BUFF_SIZE_IN       :   positive  :=  8;
-    constant BUFF_SIZE_OUT      :   integer  :=  4;
+    constant BUFF_SIZE_OUT      :   positive  :=  4;
-    constant AV_POS_SIZE        :   integer  :=  6;
+    constant AV_POS_SIZE        :   positive  :=  6;
-    constant NUM_DIRS           :   integer  :=  5;
+    constant NUM_DIRS           :   positive  :=  5;
-    constant NUM_DIRS_PARENT    :   integer  :=  8;
+    constant NUM_DIRS_PARENT    :   positive  :=  8;
-    constant DEST_ADDR_SIZE     :   integer  :=  5;
+    constant DEST_ADDR_SIZE     :   positive  :=  5;
-    constant CHIP_ADDR_SIZE     :   integer  :=  5; -- *
+    constant CHIP_ADDR_SIZE     :   positive  :=  5; -- *
-    constant MAX_PATHS_SIZE     :   integer  :=  96;
+    constant MAX_PATHS_SIZE     :   positive  :=  96;
-    constant MAX_EX_PATHS_SIZE  :   integer  :=  256;
+    constant MAX_EX_PATHS_SIZE  :   positive  :=  256;
-    constant TOP_LEVEL          :   integer  :=  5;
+    constant TOP_LEVEL          :   positive  :=  5;
 
     subtype WORD is std_logic_vector(63 downto 0);
     subtype H_WORD is std_logic_vector(31 downto 0);
     type t_PACKET_STATE is (Idle, Arbitration, InArbQueue, WritingFifo);
-    type t_PACKET_STATES is array (integer range <>) of t_PACKET_STATE;
+    type t_PACKET_STATES is array (natural range <>) of t_PACKET_STATE;
     type t_OUT_BUFF_RD_STATE is (EmptyFifo, StartRead, Sending, WaitForSender);
-    type t_OUT_BUFF_RD_STATES is array (integer range <>) of t_OUT_BUFF_RD_STATE;
+    type t_OUT_BUFF_RD_STATES is array (natural range <>) of t_OUT_BUFF_RD_STATE;
     type t_ARBITER_STATE is (DirDecoding, PathSelect, ArbComplete);
-    type t_PATHS is array (integer range <>) of 
-                            std_logic_vector(NUM_DIRS-1 downto 0);
-    type t_AVAI_POS is array(integer range <>) of 
-                            integer range 0 to MAX_PATHS_SIZE;
-    type t_AVAI_POS_SIZES is array(NUM_DIRS-1 downto 0) of 
-                            integer range 0 to MAX_PATHS_SIZE;
-    type t_EX_AVAI_POS is array(integer range <>) of 
-                            integer range 0 to MAX_EX_PATHS_SIZE;
-    type t_EX_AVAI_POS_SIZES is array(NUM_DIRS_PARENT-1 downto 0) of 
-                            integer range 0 to MAX_EX_PATHS_SIZE;
-    type t_PATH_RANGES is array(integer range <>) of 
-                            integer range 0 to MAX_EX_PATHS_SIZE;
-    type t_PATH_INDEXES is array (natural range<>) of integer;
 
     type t_fifo_wr_in is record
         data        :   WORD;
@@ -67,14 +54,14 @@ package router_types is
         copy_pos :   t_addr;
     end record;
 
-    type t_FIFO_WR_INS   is array (integer range <>) of t_fifo_wr_in;
+    type t_FIFO_WR_INS   is array (natural range <>) of t_fifo_wr_in;
-    type t_FIFO_RD_INS   is array (integer range <>) of std_logic; -- rd_req
+    type t_FIFO_RD_INS   is array (natural range <>) of std_logic; -- rd_req
-    type t_FIFO_OUTS     is array (integer range <>) of t_fifo_out;
+    type t_FIFO_OUTS     is array (natural range <>) of t_fifo_out;
-    type t_DATA          is array (integer range <>) of WORD;
+    type t_DATA          is array (natural range <>) of WORD;
-    type t_DATA_EXT      is array (integer range <>) of WORD;--H_WORD;
+    type t_DATA_EXT      is array (natural range <>) of WORD;--H_WORD;
-    type t_DATA_DIRS     is array (integer range <>) of
+    type t_DATA_DIRS     is array (natural range <>) of
                             std_logic_vector(NUM_DIRS-1 downto 0);
-    type t_DATA_DIRS_EXT is array (integer range <>) of
+    type t_DATA_DIRS_EXT is array (natural range <>) of
                             std_logic_vector(NUM_DIRS_PARENT-1 downto 0);
 
     constant DEF_FIFO_WR_IN : t_fifo_wr_in := (

router/routing_functions.vhdl

@@ -19,21 +19,6 @@ package routing_functions is
         chip_pos      :   in t_chip_addr;
         core_pos      :   in t_core_addr
     ) return std_logic_vector;
-
-    function retrieve_avai_path_index (
-        dir             : in integer;
-        path_index      : in integer;
-        num_paths_down  : in integer;
-        avai_pos        : in t_AVAI_POS
-    ) return integer;
-
-    --function retrieve_ex_avai_path_index (
-    --    dir             : in integer;
-    --    path_index      : in integer;
-    --    num_paths_up    : in integer;
-    --    num_paths_down  : in integer;
-    --    avai_pos        : in t_EX_AVAI_POS
-    --) return integer;
 end package;
 
 package body routing_functions is
@@ -131,51 +116,4 @@ package body routing_functions is
             return "01111";
         end if;
     end function;
-
-    function retrieve_avai_path_index (
-        dir             : in integer;
-        path_index      : in integer;
-        constant num_paths_down  : in integer;
-        avai_pos        : in t_AVAI_POS
-    ) return integer is
-    begin
-        if dir = 0 then
-            return avai_pos(path_index);
-        elsif dir = 1 then
-            return avai_pos(path_index+num_paths_down);
-        elsif dir = 2 then
-            return avai_pos(path_index+num_paths_down*2);
-        elsif dir = 3 then
-            return avai_pos(path_index+num_paths_down*3);
-        else
-            return avai_pos(path_index+num_paths_down*4);
-        end if;
-    end retrieve_avai_path_index;
-
-    --function retrieve_ex_avai_path_index (
-    --    dir             : in integer;
-    --    path_index      : in integer;
-    --    num_paths_up    : in integer;
-    --    num_paths_down  : in integer;
-    --    avai_pos        : in t_EX_AVAI_POS
-    --) return integer is
-    --begin
-    --    if dir = 0 then
-    --        return avai_pos(path_index);
-    --    elsif dir = 1 then
-    --        return avai_pos(path_index+num_paths_down);
-    --    elsif dir = 2 then
-    --        return avai_pos(path_index+num_paths_down*2);
-    --    elsif dir = 3 then
-    --        return avai_pos(path_index+num_paths_down*3);
-    --    elsif dir = 4 then
-    --        return avai_pos(path_index+num_paths_down*4);
-    --    elsif dir = 5 then
-    --        return avai_pos(path_index+num_paths_down*4+num_paths_up);
-    --    elsif dir = 6 then
-    --        return avai_pos(path_index+num_paths_down*4+num_paths_up*2);
-    --    else
-    --        return avai_pos(path_index+num_paths_down*4+num_paths_up*3);
-    --    end if;
-    --end retrieve_ex_avai_path_index;
 end package body;

synthesis/cmd/do_synth_all_arbiters.sh

@@ -1,5 +1,5 @@
-LEVEL=1 NPU=2 NPD=1 dc_shell -x "source cmd/do_synth_arbiter.tcl; quit" | tee -a log/synthesis.log
+LEVEL=1 NPU=2 NPD=1 dc_shell -x "source cmd/do_synth_arbiter.tcl; quit" | tee -a log/synthesis_a1.log
-LEVEL=2 NPU=4 NPD=2 dc_shell -x "source cmd/do_synth_arbiter.tcl; quit" | tee -a log/synthesis.log
+LEVEL=2 NPU=4 NPD=2 dc_shell -x "source cmd/do_synth_arbiter.tcl; quit" | tee -a log/synthesis_a2.log
-LEVEL=3 NPU=8 NPD=4 dc_shell -x "source cmd/do_synth_arbiter.tcl; quit" | tee -a log/synthesis.log
+LEVEL=3 NPU=8 NPD=4 dc_shell -x "source cmd/do_synth_arbiter.tcl; quit" | tee -a log/synthesis_a3.log
-LEVEL=4 NPU=16 NPD=8 dc_shell -x "source cmd/do_synth_arbiter.tcl; quit" | tee -a log/synthesis.log
+LEVEL=4 NPU=16 NPD=8 dc_shell -x "source cmd/do_synth_arbiter.tcl; quit" | tee -a log/synthesis_a4.log
-LEVEL=5 NPU=32 NPD=16 dc_shell -x "source cmd/do_synth_parent_arbiter.tcl; quit" | tee -a log/synthesis.log
+LEVEL=5 NPU=32 NPD=16 dc_shell -x "source cmd/do_synth_parent_arbiter.tcl; quit" | tee -a log/synthesis_a5.log

synthesis/cmd/do_synth_all_routers.sh

@@ -0,0 +1,5 @@
+LEVEL=1 NPU=2 NPD=1 CHIP_X=00001 CHIP_Y=00001 dc_shell -x "source cmd/do_synth_router.tcl; quit" | tee -a log/synthesis_r1.log
+LEVEL=2 NPU=2 NPD=1 CHIP_X=00001 CHIP_Y=00001 dc_shell -x "source cmd/do_synth_router.tcl; quit" | tee -a log/synthesis_r2.log
+LEVEL=3 NPU=2 NPD=1 CHIP_X=00001 CHIP_Y=00001 dc_shell -x "source cmd/do_synth_router.tcl; quit" | tee -a log/synthesis_r3.log
+LEVEL=4 NPU=2 NPD=1 CHIP_X=00001 CHIP_Y=00001 dc_shell -x "source cmd/do_synth_router.tcl; quit" | tee -a log/synthesis_r4.log
+LEVEL=5 NPU=2 NPD=1 CHIP_X=00001 CHIP_Y=00001 dc_shell -x "source cmd/do_synth_router.tcl; quit" | tee -a log/synthesis_r5.log

synthesis/cmd/do_synth_arbiter.tcl

@@ -3,6 +3,12 @@ set npu [getenv NPU]
 set npd [getenv NPD]
 
 analyze -library WORK -format vhdl {../router/router_types.vhdl}
+analyze -library WORK -format vhdl {../router/NthLsbDetector.vhdl}
+analyze -library WORK -format vhdl {../encoders/encoder_components.vhdl}
+analyze -library WORK -format vhdl {../encoders/encoder8to3.vhdl}
+analyze -library WORK -format vhdl {../encoders/encoder16to4.vhdl}
+analyze -library WORK -format vhdl {../encoders/encoder32to5.vhdl}
+analyze -library WORK -format vhdl {../router/arbiter_unit.vhdl}
 analyze -library WORK -format vhdl {../router/routing_functions.vhdl}
 analyze -library WORK -format vhdl {../router/arbiter.vhdl}
 elaborate arbiter -library WORK -parameters "level = $level, num_paths_up = $npu, num_paths_down = $npd"

synthesis/cmd/do_synth_noc.sh

@@ -0,0 +1 @@
+dc_shell -x "source cmd/do_synth_noc.tcl; quit" | tee -a log/synthesis_noc.log

synthesis/cmd/do_synth_noc.tcl

@@ -1,6 +1,12 @@
 analyze -library WORK -format vhdl {../router/fifo.vhdl}
 analyze -library WORK -format vhdl {../router/router_types.vhdl}
 analyze -library WORK -format vhdl {../router/routing_functions.vhdl}
+analyze -library WORK -format vhdl {../router/NthLsbDetector.vhdl}
+analyze -library WORK -format vhdl {../encoders/encoder_components.vhdl}
+analyze -library WORK -format vhdl {../encoders/encoder8to3.vhdl}
+analyze -library WORK -format vhdl {../encoders/encoder16to4.vhdl}
+analyze -library WORK -format vhdl {../encoders/encoder32to5.vhdl}
+analyze -library WORK -format vhdl {../router/arbiter_unit.vhdl}
 analyze -library WORK -format vhdl {../router/receiver.vhdl}
 analyze -library WORK -format vhdl {../router/sender.vhdl}
 analyze -library WORK -format vhdl {../router/arbiter.vhdl}

synthesis/cmd/do_synth_router.tcl

@@ -6,6 +6,12 @@ set chip_y [getenv CHIP_Y]
 
 analyze -library WORK -format vhdl {../router/fifo.vhdl}
 analyze -library WORK -format vhdl {../router/router_types.vhdl}
+analyze -library WORK -format vhdl {../router/NthLsbDetector.vhdl}
+analyze -library WORK -format vhdl {../encoders/encoder_components.vhdl}
+analyze -library WORK -format vhdl {../encoders/encoder8to3.vhdl}
+analyze -library WORK -format vhdl {../encoders/encoder16to4.vhdl}
+analyze -library WORK -format vhdl {../encoders/encoder32to5.vhdl}
+analyze -library WORK -format vhdl {../router/arbiter_unit.vhdl}
 analyze -library WORK -format vhdl {../router/routing_functions.vhdl}
 analyze -library WORK -format vhdl {../router/receiver.vhdl}
 analyze -library WORK -format vhdl {../router/sender.vhdl}

synthesis/cmd/do_synth_router_lvl1.sh

@@ -1 +0,0 @@
-LEVEL=1 NPU=2 NPD=1 CHIP_X=00001 CHIP_Y=00001 dc_shell -x "source cmd/do_synth_router.tcl; quit" | tee -a log/synthesis.log