From 977951d080228af09d365f29bd1b7da5c484fe36 Mon Sep 17 00:00:00 2001 From: Retrocamara42 Date: Thu, 3 Jul 2025 08:47:28 -0500 Subject: [PATCH 1/2] fix: core_pos size corrected --- noc/quadtree_components.vhdl | 4 ++-- router/router.vhdl | 10 +++++----- router/router_components.vhdl | 4 ++-- synthesis/cmd/do_synth_router.tcl | 1 + 4 files changed, 10 insertions(+), 9 deletions(-) diff --git a/noc/quadtree_components.vhdl b/noc/quadtree_components.vhdl index 789725e..b4c16cc 100644 --- a/noc/quadtree_components.vhdl +++ b/noc/quadtree_components.vhdl @@ -18,8 +18,8 @@ package quadtree_components is port ( clk : in std_logic; arstN : in std_logic; - core_x : in std_logic_vector(4 downto 0); - core_y : in std_logic_vector(4 downto 0); + core_x : in std_logic_vector(4 downto 1); + core_y : in std_logic_vector(4 downto 1); data_in : in t_DATA(num_paths_up+num_paths_down*4-1 downto 0); rcv_reqs : in std_logic_vector(num_paths_up+num_paths_down*4-1 downto 0); send_ack : in std_logic_vector(num_paths_up+num_paths_down*4-1 downto 0); diff --git a/router/router.vhdl b/router/router.vhdl index a7f3f46..72625b3 100644 --- a/router/router.vhdl +++ b/router/router.vhdl @@ -13,8 +13,8 @@ generic ( buffer_width : integer := 64; buffer_depth : integer := 4; fifo_ptr_size : integer := 3; - chip_x : std_logic_vector(4 downto 0) := "00000"; - chip_y : std_logic_vector(4 downto 0) := "00000" + chip_x : std_logic_vector(DEST_ADDR_SIZE-1 downto 0) := "00000"; + chip_y : std_logic_vector(DEST_ADDR_SIZE-1 downto 0) := "00000" ); port ( clk : in std_logic; @@ -34,7 +34,7 @@ architecture impl of router is constant TOT_NUM_PATHS : integer := num_paths_up + num_paths_down*4; constant chip_pos : t_chip_addr := (x => chip_x, y=> chip_y); - signal core_pos : t_addr; + signal core_pos : t_core_addr; signal rcv_buff_out : t_FIFO_OUTS(TOT_NUM_PATHS-1 downto 0); signal snd_buff_wr_in : t_FIFO_WR_INS(TOT_NUM_PATHS-1 downto 0); signal snd_buff_out : t_FIFO_OUTS(num_paths_up+num_paths_down*4-1 downto 0); @@ -241,6 +241,6 @@ begin end if; end process; - core_pos.x <= core_x; - core_pos.y <= core_y; + core_pos.x <= core_x(DEST_ADDR_SIZE-1 downto 1); + core_pos.y <= core_y(DEST_ADDR_SIZE-1 downto 1); end impl; \ No newline at end of file diff --git a/router/router_components.vhdl b/router/router_components.vhdl index e51e492..d427997 100644 --- a/router/router_components.vhdl +++ b/router/router_components.vhdl @@ -44,7 +44,7 @@ package router_components is ); port ( chip_pos : in t_chip_addr; - core_pos : in t_addr; + core_pos : in t_core_addr; packets : in t_DATA(num_paths_up+num_paths_down*4-1 downto 0); valid_data : in std_logic_vector( num_paths_up+num_paths_down*4-1 downto 0); @@ -65,7 +65,7 @@ package router_components is ); port ( chip_pos : in t_chip_addr; - core_pos : in t_addr; + core_pos : in t_core_addr; packets : in t_DATA(num_paths_up*4+num_paths_down*4-1 downto 0); valid_data : in std_logic_vector(num_paths_up*4+num_paths_down*4-1 downto 0); avai_paths : in std_logic_vector(num_paths_up*4+num_paths_down*4-1 downto 0); diff --git a/synthesis/cmd/do_synth_router.tcl b/synthesis/cmd/do_synth_router.tcl index 9087dc1..49b7d7a 100644 --- a/synthesis/cmd/do_synth_router.tcl +++ b/synthesis/cmd/do_synth_router.tcl @@ -11,6 +11,7 @@ analyze -library WORK -format vhdl {../router/receiver.vhdl} analyze -library WORK -format vhdl {../router/sender.vhdl} analyze -library WORK -format vhdl {../router/arbiter.vhdl} link +analyze -library WORK -format vhdl {../router/router_components.vhdl} analyze -library WORK -format vhdl {../router/router.vhdl} elaborate router -library WORK -parameters "level = $level, num_paths_up = $npu, num_paths_down = $npd, From f3cbca90d10c33c2163c8bbd6ba8a148d65bf60d Mon Sep 17 00:00:00 2001 From: Retrocamara42 Date: Thu, 3 Jul 2025 08:47:38 -0500 Subject: [PATCH 2/2] fix: core_pos size corrected --- noc/quadtree_components.vhdl | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/noc/quadtree_components.vhdl b/noc/quadtree_components.vhdl index b4c16cc..789725e 100644 --- a/noc/quadtree_components.vhdl +++ b/noc/quadtree_components.vhdl @@ -18,8 +18,8 @@ package quadtree_components is port ( clk : in std_logic; arstN : in std_logic; - core_x : in std_logic_vector(4 downto 1); - core_y : in std_logic_vector(4 downto 1); + core_x : in std_logic_vector(4 downto 0); + core_y : in std_logic_vector(4 downto 0); data_in : in t_DATA(num_paths_up+num_paths_down*4-1 downto 0); rcv_reqs : in std_logic_vector(num_paths_up+num_paths_down*4-1 downto 0); send_ack : in std_logic_vector(num_paths_up+num_paths_down*4-1 downto 0);