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12 changed files with 63 additions and 293 deletions
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14
noc/noc.vhdl
View file

@ -13,13 +13,11 @@ generic (
buffer_depth : integer := 4; buffer_depth : integer := 4;
fifo_ptr_size : integer := 3; fifo_ptr_size : integer := 3;
level : integer := 5; level : integer := 5;
top_level : integer := 5;
chip_x : std_logic_vector(4 downto 0) := "00000"; chip_x : std_logic_vector(4 downto 0) := "00000";
chip_y : std_logic_vector(4 downto 0) := "00000" chip_y : std_logic_vector(4 downto 0) := "00000"
); );
port ( port (
clks : in std_logic_vector( clk : in std_logic;
calculate_num_routers(top_level)-1 downto 0);
arstN : in std_logic; arstN : in std_logic;
data_chip_in : in t_DATA_EXT(4*num_paths_ext-1 downto 0); data_chip_in : in t_DATA_EXT(4*num_paths_ext-1 downto 0);
@ -45,7 +43,6 @@ architecture impl of noc is
constant l5_core_y : std_logic_vector(4 downto 0) := "-----"; constant l5_core_y : std_logic_vector(4 downto 0) := "-----";
constant num_paths_up : integer := 32; constant num_paths_up : integer := 32;
constant num_paths_down : integer := 16; constant num_paths_down : integer := 16;
constant num_routers : integer := calculate_num_routers(top_level);
signal r_data_ds_in : t_DATA(4*num_paths_down-1 downto 0); signal r_data_ds_in : t_DATA(4*num_paths_down-1 downto 0);
signal r_data_ds_out : t_DATA(4*num_paths_down-1 downto 0); signal r_data_ds_out : t_DATA(4*num_paths_down-1 downto 0);
@ -82,19 +79,18 @@ begin
generic map(num_paths_up => num_paths_up, num_paths_down => num_paths_down, generic map(num_paths_up => num_paths_up, num_paths_down => num_paths_down,
level => level, buffer_width => buffer_width, buffer_depth => buffer_depth, level => level, buffer_width => buffer_width, buffer_depth => buffer_depth,
fifo_ptr_size => fifo_ptr_size, chip_x => chip_x, chip_y => chip_y) fifo_ptr_size => fifo_ptr_size, chip_x => chip_x, chip_y => chip_y)
port map(clk => clks(num_routers-1), arstN => arstN, core_x => l5_core_x, core_y => l5_core_y, port map(clk => clk, arstN => arstN, core_x => l5_core_x, core_y => l5_core_y,
data_in_ds => r_data_ds_in, data_in_us => data_chip_in, data_in_ds => r_data_ds_in, data_in_us => data_chip_in,
rcv_reqs => r_rcv_reqs, send_ack => r_snd_ack, rcv_acks => r_rcv_ack, rcv_reqs => r_rcv_reqs, send_ack => r_snd_ack, rcv_acks => r_rcv_ack,
send_reqs => r_snd_reqs, data_out_ds => r_data_ds_out, send_reqs => r_snd_reqs, data_out_ds => r_data_ds_out,
data_out_us => s_data_chip_out); data_out_us => s_data_chip_out);
quadtree_inst: quadtree quadtree_inst: quadtree
generic map(num_paths_up => num_paths_up, num_paths_down => num_paths_down, generic map(num_paths_up => num_paths_up,
level => level, top_level => top_level, num_paths_down => num_paths_down, level => level,
buffer_width => buffer_width, buffer_depth => buffer_depth, buffer_width => buffer_width, buffer_depth => buffer_depth,
fifo_ptr_size => fifo_ptr_size, chip_x => chip_x, chip_y => chip_y) fifo_ptr_size => fifo_ptr_size, chip_x => chip_x, chip_y => chip_y)
port map(clks => clks(num_routers-2 downto 0), port map(clk => clk, arstN => arstN, core_x => l5_core_x,
arstN => arstN, core_x => l5_core_x,
core_y => l5_core_y, data_in_us => r_data_ds_out, core_y => l5_core_y, data_in_us => r_data_ds_out,
rcv_reqs_us => r_snd_reqs_ds, send_ack_us => r_rcv_ack_ds, rcv_reqs_us => r_snd_reqs_ds, send_ack_us => r_rcv_ack_ds,
pe_data_in => pe_data_in, pe_rcv_reqs => pe_rcv_reqs, pe_data_in => pe_data_in, pe_rcv_reqs => pe_rcv_reqs,

5
noc/noc_conf.vhdl
View file

@ -2,7 +2,6 @@ library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;
use ieee.numeric_std.all; use ieee.numeric_std.all;
use work.router_types.all; use work.router_types.all;
use work.quadtree_components.all;
package noc_conf is package noc_conf is
component parent_router is component parent_router is
@ -40,13 +39,11 @@ package noc_conf is
buffer_depth : integer := 4; buffer_depth : integer := 4;
fifo_ptr_size : integer := 3; fifo_ptr_size : integer := 3;
level : integer := 5; level : integer := 5;
top_level : integer := 5;
chip_x : std_logic_vector(4 downto 0) := "00000"; chip_x : std_logic_vector(4 downto 0) := "00000";
chip_y : std_logic_vector(4 downto 0) := "00000" chip_y : std_logic_vector(4 downto 0) := "00000"
); );
port ( port (
clks : in std_logic_vector( clk : in std_logic;
calculate_num_routers_qt(level, top_level)-1 downto 0);
arstN : in std_logic; arstN : in std_logic;
core_x : in std_logic_vector(4 downto 0); core_x : in std_logic_vector(4 downto 0);

14
noc/quadtree.vhdl
View file

@ -13,13 +13,11 @@ generic (
buffer_depth : integer := 4; buffer_depth : integer := 4;
fifo_ptr_size : integer := 3; fifo_ptr_size : integer := 3;
level : integer := 5; level : integer := 5;
top_level : integer := 5;
chip_x : std_logic_vector(4 downto 0) := "00000"; chip_x : std_logic_vector(4 downto 0) := "00000";
chip_y : std_logic_vector(4 downto 0) := "00000" chip_y : std_logic_vector(4 downto 0) := "00000"
); );
port ( port (
clks : in std_logic_vector( clk : in std_logic;
calculate_num_routers_qt(level, top_level)-1 downto 0);
arstN : in std_logic; arstN : in std_logic;
core_x : in std_logic_vector(4 downto 0); core_x : in std_logic_vector(4 downto 0);
@ -44,7 +42,6 @@ port (
end quadtree; end quadtree;
architecture impl of quadtree is architecture impl of quadtree is
constant num_routers : integer := calculate_num_routers_qt(level, top_level);
signal r_core_x : std_logic_vector(19 downto 0) := (others => '0'); signal r_core_x : std_logic_vector(19 downto 0) := (others => '0');
signal r_core_y : std_logic_vector(19 downto 0) := (others => '0'); signal r_core_y : std_logic_vector(19 downto 0) := (others => '0');
begin begin
@ -150,7 +147,7 @@ begin
level => level-1, buffer_width => buffer_width, level => level-1, buffer_width => buffer_width,
buffer_depth => buffer_depth, fifo_ptr_size => fifo_ptr_size, buffer_depth => buffer_depth, fifo_ptr_size => fifo_ptr_size,
chip_x => chip_x, chip_y => chip_y) chip_x => chip_x, chip_y => chip_y)
port map(clk => clks(num_routers-1-i), arstN => arstN, port map(clk => clk, arstN => arstN,
core_x => r_core_x(5*(i+1)-1 downto 5*i), core_x => r_core_x(5*(i+1)-1 downto 5*i),
core_y => r_core_y(5*(i+1)-1 downto 5*i), core_y => r_core_y(5*(i+1)-1 downto 5*i),
data_in => r_data_in((4*npd+npu)*(i+1)-1 downto (4*npd+npu)*i), data_in => r_data_in((4*npd+npu)*(i+1)-1 downto (4*npd+npu)*i),
@ -162,13 +159,10 @@ begin
router_subtree: entity work.quadtree router_subtree: entity work.quadtree
generic map(num_paths_up => npu, num_paths_down => npd, generic map(num_paths_up => npu, num_paths_down => npd,
level => level-1, top_level => top_level, level => level-1, buffer_width => buffer_width,
buffer_width => buffer_width,
buffer_depth => buffer_depth, fifo_ptr_size => fifo_ptr_size, buffer_depth => buffer_depth, fifo_ptr_size => fifo_ptr_size,
chip_x => chip_x, chip_y => chip_y) chip_x => chip_x, chip_y => chip_y)
port map( port map(clk => clk, arstN => arstN,
clks => clks((num_routers-4)*(i+1)/4-1 downto (num_routers-4)*i/4),
arstN => arstN,
core_x => r_core_x(5*(i+1)-1 downto 5*i), core_x => r_core_x(5*(i+1)-1 downto 5*i),
core_y => r_core_y(5*(i+1)-1 downto 5*i), core_y => r_core_y(5*(i+1)-1 downto 5*i),
data_in_us => r_data_ds_out(4*npd*(i+1)-1 downto 4*npd*i), data_in_us => r_data_ds_out(4*npd*(i+1)-1 downto 4*npd*i),

38
noc/quadtree_components.vhdl
View file

@ -28,40 +28,4 @@ package quadtree_components is
data_out : out t_DATA(num_paths_up+num_paths_down*4-1 downto 0) data_out : out t_DATA(num_paths_up+num_paths_down*4-1 downto 0)
); );
end component Router; end component Router;
end package;
function calculate_num_routers (
top_level : in integer
) return integer;
function calculate_num_routers_qt (
level : in integer;
top_level : in integer
) return integer;
end package;
package body quadtree_components is
function calculate_num_routers(
top_level : in integer
) return integer is
variable num_routers : integer;
begin
num_routers := 0;
for i in 0 to top_level-1 loop
num_routers := num_routers + 4**i;
end loop;
return num_routers;
end function;
function calculate_num_routers_qt(
level : in integer;
top_level : in integer
) return integer is
variable num_routers : integer;
begin
num_routers := calculate_num_routers(top_level) - 1;
for i in 0 to top_level-level-1 loop
num_routers := (num_routers-4)/4;
end loop;
return num_routers;
end function;
end package body;

48
router/arbiter.vhdl
View file

@ -25,6 +25,8 @@ architecture impl of arbiter is
constant TOT_NUM_PATHS : integer := num_paths_up + num_paths_down*4; constant TOT_NUM_PATHS : integer := num_paths_up + num_paths_down*4;
signal dirs : t_DATA_DIRS(TOT_NUM_PATHS-1 downto 0); signal dirs : t_DATA_DIRS(TOT_NUM_PATHS-1 downto 0);
signal ps_dirs : t_DATA_DIRS(TOT_NUM_PATHS-1 downto 0);
signal avai_pos : t_AVAI_POS(TOT_NUM_PATHS-1 downto 0);
begin begin
get_rout_dir: process(rout_pos, valid_data, packets) get_rout_dir: process(rout_pos, valid_data, packets)
variable pack_dest : t_pos_addr; variable pack_dest : t_pos_addr;
@ -54,44 +56,39 @@ begin
variable avai_path : std_logic; variable avai_path : std_logic;
variable avai_pos_sizes : t_AVAI_POS_SIZES; variable avai_pos_sizes : t_AVAI_POS_SIZES;
variable avai_index : integer; variable avai_index : integer;
variable ps_dirs : t_DATA_DIRS(TOT_NUM_PATHS-1 downto 0);
variable avai_pos : t_AVAI_POS(TOT_NUM_PATHS-1 downto 0);
variable path_index : integer;
variable out_index : integer;
begin begin
avai_pos_sizes := (others => 0); avai_pos_sizes := (others => 0);
avai_pos := (others => 0);
-- find available paths and n_j (avai pos sizes) -- find available paths and n_j (avai pos sizes)
for i in 0 to TOT_NUM_PATHS-1 loop for i in 0 to TOT_NUM_PATHS-1 loop
avai_path := avai_paths(i); avai_path := avai_paths(i);
if i < num_paths_down then if i < num_paths_down then
if avai_path = '1' then if avai_path = '1' then
avai_index := avai_pos_sizes(0); avai_index := avai_pos_sizes(0);
avai_pos(avai_index) := i; avai_pos(avai_index) <= i;
avai_pos_sizes(0) := avai_pos_sizes(0) + 1; avai_pos_sizes(0) := avai_pos_sizes(0) + 1;
end if; end if;
elsif i < num_paths_down*2 then elsif i < num_paths_down*2 then
if avai_path = '1' then if avai_path = '1' then
avai_index := avai_pos_sizes(1) + num_paths_down; avai_index := avai_pos_sizes(1) + num_paths_down;
avai_pos(avai_index) := i; avai_pos(avai_index) <= i;
avai_pos_sizes(1) := avai_pos_sizes(1) + 1; avai_pos_sizes(1) := avai_pos_sizes(1) + 1;
end if; end if;
elsif i < num_paths_down*3 then elsif i < num_paths_down*3 then
if avai_path = '1' then if avai_path = '1' then
avai_index := avai_pos_sizes(2) + num_paths_down*2; avai_index := avai_pos_sizes(2) + num_paths_down*2;
avai_pos(avai_index) := i; avai_pos(avai_index) <= i;
avai_pos_sizes(2) := avai_pos_sizes(2) + 1; avai_pos_sizes(2) := avai_pos_sizes(2) + 1;
end if; end if;
elsif i < num_paths_down*4 then elsif i < num_paths_down*4 then
if avai_path = '1' then if avai_path = '1' then
avai_index := avai_pos_sizes(3) + num_paths_down*3; avai_index := avai_pos_sizes(3) + num_paths_down*3;
avai_pos(avai_index) := i; avai_pos(avai_index) <= i;
avai_pos_sizes(3) := avai_pos_sizes(3) + 1; avai_pos_sizes(3) := avai_pos_sizes(3) + 1;
end if; end if;
else else
if avai_path = '1' then if avai_path = '1' then
avai_index := avai_pos_sizes(4) + num_paths_down*4; avai_index := avai_pos_sizes(4) + num_paths_down*4;
avai_pos(avai_index) := i; avai_pos(avai_index) <= i;
avai_pos_sizes(4) := avai_pos_sizes(4) + 1; avai_pos_sizes(4) := avai_pos_sizes(4) + 1;
end if; end if;
end if; end if;
@ -117,43 +114,43 @@ begin
j := 4; j := 4;
end if; end if;
if avai_pos_sizes(j) <= 0 then if avai_pos_sizes(j) <= 0 then
ps_dirs(i) := (others => '0'); ps_dirs(i) <= (others => '0');
else else
ps_dirs(i) := dirs(i); ps_dirs(i) <= dirs(i);
avai_pos_sizes(j) := avai_pos_sizes(j)-1; avai_pos_sizes(j) := avai_pos_sizes(j)-1;
end if; end if;
-- 1 to 2 multicast -- 1 to 2 multicast
elsif sum_dirs = 2 then elsif sum_dirs = 2 then
if dirs(i)(1) = '1' and dirs(i)(3) = '1' then if dirs(i)(1) = '1' and dirs(i)(3) = '1' then
if avai_pos_sizes(1) <= 0 or avai_pos_sizes(3) <= 0 then if avai_pos_sizes(1) <= 0 or avai_pos_sizes(3) <= 0 then
ps_dirs(i) := (others => '0'); ps_dirs(i) <= (others => '0');
else else
ps_dirs(i) := dirs(i); ps_dirs(i) <= dirs(i);
avai_pos_sizes(1) := avai_pos_sizes(1)-1; avai_pos_sizes(1) := avai_pos_sizes(1)-1;
avai_pos_sizes(3) := avai_pos_sizes(3)-1; avai_pos_sizes(3) := avai_pos_sizes(3)-1;
end if; end if;
elsif dirs(i)(0) = '1' and dirs(i)(2) = '1' then elsif dirs(i)(0) = '1' and dirs(i)(2) = '1' then
if avai_pos_sizes(0) <= 0 or avai_pos_sizes(2) <= 0 then if avai_pos_sizes(0) <= 0 or avai_pos_sizes(2) <= 0 then
ps_dirs(i) := (others => '0'); ps_dirs(i) <= (others => '0');
else else
ps_dirs(i) := dirs(i); ps_dirs(i) <= dirs(i);
avai_pos_sizes(0) := avai_pos_sizes(0)-1; avai_pos_sizes(0) := avai_pos_sizes(0)-1;
avai_pos_sizes(2) := avai_pos_sizes(2)-1; avai_pos_sizes(2) := avai_pos_sizes(2)-1;
end if; end if;
elsif dirs(i)(2) = '1' and dirs(i)(3) = '1' then elsif dirs(i)(2) = '1' and dirs(i)(3) = '1' then
if avai_pos_sizes(2) <= 0 or avai_pos_sizes(3) <= 0 then if avai_pos_sizes(2) <= 0 or avai_pos_sizes(3) <= 0 then
ps_dirs(i) := (others => '0'); ps_dirs(i) <= (others => '0');
else else
ps_dirs(i) := dirs(i); ps_dirs(i) <= dirs(i);
avai_pos_sizes(2) := avai_pos_sizes(2)-1; avai_pos_sizes(2) := avai_pos_sizes(2)-1;
avai_pos_sizes(3) := avai_pos_sizes(3)-1; avai_pos_sizes(3) := avai_pos_sizes(3)-1;
end if; end if;
--elsif dirs(i)(1) = '1' and dirs(i)(2) = '1' then --elsif dirs(i)(1) = '1' and dirs(i)(2) = '1' then
else else
if avai_pos_sizes(0) <= 0 or avai_pos_sizes(1) <= 0 then if avai_pos_sizes(0) <= 0 or avai_pos_sizes(1) <= 0 then
ps_dirs(i) := (others => '0'); ps_dirs(i) <= (others => '0');
else else
ps_dirs(i) := dirs(i); ps_dirs(i) <= dirs(i);
avai_pos_sizes(0) := avai_pos_sizes(0)-1; avai_pos_sizes(0) := avai_pos_sizes(0)-1;
avai_pos_sizes(1) := avai_pos_sizes(1)-1; avai_pos_sizes(1) := avai_pos_sizes(1)-1;
end if; end if;
@ -162,20 +159,23 @@ begin
elsif sum_dirs = 4 then elsif sum_dirs = 4 then
if avai_pos_sizes(0) <= 0 or avai_pos_sizes(1) <= 0 or if avai_pos_sizes(0) <= 0 or avai_pos_sizes(1) <= 0 or
avai_pos_sizes(2) <= 0 or avai_pos_sizes(3) <= 0 then avai_pos_sizes(2) <= 0 or avai_pos_sizes(3) <= 0 then
ps_dirs(i) := (others => '0'); ps_dirs(i) <= (others => '0');
else else
ps_dirs(i) := dirs(i); ps_dirs(i) <= dirs(i);
avai_pos_sizes(0) := avai_pos_sizes(0)-1; avai_pos_sizes(0) := avai_pos_sizes(0)-1;
avai_pos_sizes(1) := avai_pos_sizes(1)-1; avai_pos_sizes(1) := avai_pos_sizes(1)-1;
avai_pos_sizes(2) := avai_pos_sizes(2)-1; avai_pos_sizes(2) := avai_pos_sizes(2)-1;
avai_pos_sizes(3) := avai_pos_sizes(3)-1; avai_pos_sizes(3) := avai_pos_sizes(3)-1;
end if; end if;
else else
ps_dirs(i) := (others => '0'); ps_dirs(i) <= (others => '0');
end if; end if;
end loop; end loop;
end process;
-- set out buffer set_out_buffer: process(ps_dirs, packets, avai_pos)
variable path_index, out_index : integer;
begin
for i in 0 to TOT_NUM_PATHS-1 loop for i in 0 to TOT_NUM_PATHS-1 loop
buff_wr_in(i).data <= (others => '0'); buff_wr_in(i).data <= (others => '0');
buff_wr_in(i).wr_req <= '0'; buff_wr_in(i).wr_req <= '0';

54
router/parent_arbiter.vhdl
View file

@ -25,6 +25,8 @@ architecture impl of parent_arbiter is
constant TOT_NUM_PATHS : integer := num_paths_up*4 + num_paths_down*4; constant TOT_NUM_PATHS : integer := num_paths_up*4 + num_paths_down*4;
signal dirs : t_DATA_DIRS_EXT(TOT_NUM_PATHS-1 downto 0); signal dirs : t_DATA_DIRS_EXT(TOT_NUM_PATHS-1 downto 0);
signal ps_dirs : t_DATA_DIRS_EXT(TOT_NUM_PATHS-1 downto 0);
signal avai_pos : t_EX_AVAI_POS(TOT_NUM_PATHS-1 downto 0);
begin begin
L5_get_rout_dir: process(rout_pos, valid_data, packets) L5_get_rout_dir: process(rout_pos, valid_data, packets)
variable pack_dest : t_pos_addr; variable pack_dest : t_pos_addr;
@ -53,62 +55,57 @@ begin
variable avai_path : std_logic; variable avai_path : std_logic;
variable avai_pos_sizes : t_EX_AVAI_POS_SIZES; variable avai_pos_sizes : t_EX_AVAI_POS_SIZES;
variable avai_index : integer; variable avai_index : integer;
variable ps_dirs : t_DATA_DIRS_EXT(TOT_NUM_PATHS-1 downto 0);
variable avai_pos : t_EX_AVAI_POS(TOT_NUM_PATHS-1 downto 0);
variable path_index : integer;
variable out_index : integer;
begin begin
avai_pos_sizes := (others => 0); avai_pos_sizes := (others => 0);
avai_pos := (others => 0);
-- find available paths and n_j (avai pos sizes) -- find available paths and n_j (avai pos sizes)
for i in 0 to TOT_NUM_PATHS-1 loop for i in 0 to TOT_NUM_PATHS-1 loop
avai_path := avai_paths(i); avai_path := avai_paths(i);
if i < num_paths_down then if i < num_paths_down then
if avai_path = '1' then if avai_path = '1' then
avai_index := avai_pos_sizes(0); avai_index := avai_pos_sizes(0);
avai_pos(avai_index) := i; avai_pos(avai_index) <= i;
avai_pos_sizes(0) := avai_pos_sizes(0) + 1; avai_pos_sizes(0) := avai_pos_sizes(0) + 1;
end if; end if;
elsif i < num_paths_down*2 then elsif i < num_paths_down*2 then
if avai_path = '1' then if avai_path = '1' then
avai_index := avai_pos_sizes(1) + num_paths_down; avai_index := avai_pos_sizes(1) + num_paths_down;
avai_pos(avai_index) := i; avai_pos(avai_index) <= i;
avai_pos_sizes(1) := avai_pos_sizes(1) + 1; avai_pos_sizes(1) := avai_pos_sizes(1) + 1;
end if; end if;
elsif i < num_paths_down*3 then elsif i < num_paths_down*3 then
if avai_path = '1' then if avai_path = '1' then
avai_index := avai_pos_sizes(2) + num_paths_down*2; avai_index := avai_pos_sizes(2) + num_paths_down*2;
avai_pos(avai_index) := i; avai_pos(avai_index) <= i;
avai_pos_sizes(2) := avai_pos_sizes(2) + 1; avai_pos_sizes(2) := avai_pos_sizes(2) + 1;
end if; end if;
elsif i < num_paths_down*4 then elsif i < num_paths_down*4 then
if avai_path = '1' then if avai_path = '1' then
avai_index := avai_pos_sizes(3) + num_paths_down*3; avai_index := avai_pos_sizes(3) + num_paths_down*3;
avai_pos(avai_index) := i; avai_pos(avai_index) <= i;
avai_pos_sizes(3) := avai_pos_sizes(3) + 1; avai_pos_sizes(3) := avai_pos_sizes(3) + 1;
end if; end if;
elsif i < num_paths_down*4 + num_paths_up then elsif i < num_paths_down*4 + num_paths_up then
if avai_path = '1' then if avai_path = '1' then
avai_index := avai_pos_sizes(4) + num_paths_down*4; avai_index := avai_pos_sizes(4) + num_paths_down*4;
avai_pos(avai_index) := i; avai_pos(avai_index) <= i;
avai_pos_sizes(4) := avai_pos_sizes(4) + 1; avai_pos_sizes(4) := avai_pos_sizes(4) + 1;
end if; end if;
elsif i < num_paths_down*4 + num_paths_up*2 then elsif i < num_paths_down*4 + num_paths_up*2 then
if avai_path = '1' then if avai_path = '1' then
avai_index := avai_pos_sizes(5)+num_paths_down*4+num_paths_up; avai_index := avai_pos_sizes(5)+num_paths_down*4+num_paths_up;
avai_pos(avai_index) := i; avai_pos(avai_index) <= i;
avai_pos_sizes(5) := avai_pos_sizes(5) + 1; avai_pos_sizes(5) := avai_pos_sizes(5) + 1;
end if; end if;
elsif i < num_paths_down*4 + num_paths_up*3 then elsif i < num_paths_down*4 + num_paths_up*3 then
if avai_path = '1' then if avai_path = '1' then
avai_index:=avai_pos_sizes(6)+num_paths_down*4+num_paths_up*2; avai_index:=avai_pos_sizes(6)+num_paths_down*4+num_paths_up*2;
avai_pos(avai_index) := i; avai_pos(avai_index) <= i;
avai_pos_sizes(6) := avai_pos_sizes(6) + 1; avai_pos_sizes(6) := avai_pos_sizes(6) + 1;
end if; end if;
else else
if avai_path = '1' then if avai_path = '1' then
avai_index:=avai_pos_sizes(7)+num_paths_down*4+num_paths_up*3; avai_index:=avai_pos_sizes(7)+num_paths_down*4+num_paths_up*3;
avai_pos(avai_index) := i; avai_pos(avai_index) <= i;
avai_pos_sizes(7) := avai_pos_sizes(7) + 1; avai_pos_sizes(7) := avai_pos_sizes(7) + 1;
end if; end if;
end if; end if;
@ -140,43 +137,43 @@ begin
j := 7; j := 7;
end if; end if;
if avai_pos_sizes(j) <= 0 then if avai_pos_sizes(j) <= 0 then
ps_dirs(i) := (others => '0'); ps_dirs(i) <= (others => '0');
else else
ps_dirs(i) := dirs(i); ps_dirs(i) <= dirs(i);
avai_pos_sizes(j) := avai_pos_sizes(j)-1; avai_pos_sizes(j) := avai_pos_sizes(j)-1;
end if; end if;
-- 1 to 2 multicast -- 1 to 2 multicast
elsif sum_dirs = 2 then elsif sum_dirs = 2 then
if dirs(i)(1) = '1' and dirs(i)(3) = '1' then if dirs(i)(1) = '1' and dirs(i)(3) = '1' then
if avai_pos_sizes(1) <= 0 or avai_pos_sizes(3) <= 0 then if avai_pos_sizes(1) <= 0 or avai_pos_sizes(3) <= 0 then
ps_dirs(i) := (others => '0'); ps_dirs(i) <= (others => '0');
else else
ps_dirs(i) := dirs(i); ps_dirs(i) <= dirs(i);
avai_pos_sizes(1) := avai_pos_sizes(1)-1; avai_pos_sizes(1) := avai_pos_sizes(1)-1;
avai_pos_sizes(3) := avai_pos_sizes(3)-1; avai_pos_sizes(3) := avai_pos_sizes(3)-1;
end if; end if;
elsif dirs(i)(0) = '1' and dirs(i)(2) = '1' then elsif dirs(i)(0) = '1' and dirs(i)(2) = '1' then
if avai_pos_sizes(0) <= 0 or avai_pos_sizes(2) <= 0 then if avai_pos_sizes(0) <= 0 or avai_pos_sizes(2) <= 0 then
ps_dirs(i) := (others => '0'); ps_dirs(i) <= (others => '0');
else else
ps_dirs(i) := dirs(i); ps_dirs(i) <= dirs(i);
avai_pos_sizes(0) := avai_pos_sizes(0)-1; avai_pos_sizes(0) := avai_pos_sizes(0)-1;
avai_pos_sizes(2) := avai_pos_sizes(2)-1; avai_pos_sizes(2) := avai_pos_sizes(2)-1;
end if; end if;
elsif dirs(i)(2) = '1' and dirs(i)(3) = '1' then elsif dirs(i)(2) = '1' and dirs(i)(3) = '1' then
if avai_pos_sizes(2) <= 0 or avai_pos_sizes(3) <= 0 then if avai_pos_sizes(2) <= 0 or avai_pos_sizes(3) <= 0 then
ps_dirs(i) := (others => '0'); ps_dirs(i) <= (others => '0');
else else
ps_dirs(i) := dirs(i); ps_dirs(i) <= dirs(i);
avai_pos_sizes(2) := avai_pos_sizes(2)-1; avai_pos_sizes(2) := avai_pos_sizes(2)-1;
avai_pos_sizes(3) := avai_pos_sizes(3)-1; avai_pos_sizes(3) := avai_pos_sizes(3)-1;
end if; end if;
--elsif dirs(i)(1) = '1' and dirs(i)(2) = '1' then --elsif dirs(i)(1) = '1' and dirs(i)(2) = '1' then
else else
if avai_pos_sizes(0) <= 0 or avai_pos_sizes(1) <= 0 then if avai_pos_sizes(0) <= 0 or avai_pos_sizes(1) <= 0 then
ps_dirs(i) := (others => '0'); ps_dirs(i) <= (others => '0');
else else
ps_dirs(i) := dirs(i); ps_dirs(i) <= dirs(i);
avai_pos_sizes(0) := avai_pos_sizes(0)-1; avai_pos_sizes(0) := avai_pos_sizes(0)-1;
avai_pos_sizes(1) := avai_pos_sizes(1)-1; avai_pos_sizes(1) := avai_pos_sizes(1)-1;
end if; end if;
@ -185,20 +182,23 @@ begin
elsif sum_dirs = 4 then elsif sum_dirs = 4 then
if avai_pos_sizes(0) <= 0 or avai_pos_sizes(1) <= 0 or if avai_pos_sizes(0) <= 0 or avai_pos_sizes(1) <= 0 or
avai_pos_sizes(2) <= 0 or avai_pos_sizes(3) <= 0 then avai_pos_sizes(2) <= 0 or avai_pos_sizes(3) <= 0 then
ps_dirs(i) := (others => '0'); ps_dirs(i) <= (others => '0');
else else
ps_dirs(i) := dirs(i); ps_dirs(i) <= dirs(i);
avai_pos_sizes(0) := avai_pos_sizes(0)-1; avai_pos_sizes(0) := avai_pos_sizes(0)-1;
avai_pos_sizes(1) := avai_pos_sizes(1)-1; avai_pos_sizes(1) := avai_pos_sizes(1)-1;
avai_pos_sizes(2) := avai_pos_sizes(2)-1; avai_pos_sizes(2) := avai_pos_sizes(2)-1;
avai_pos_sizes(3) := avai_pos_sizes(3)-1; avai_pos_sizes(3) := avai_pos_sizes(3)-1;
end if; end if;
else else
ps_dirs(i) := (others => '0'); ps_dirs(i) <= (others => '0');
end if; end if;
end loop; end loop;
end process;
-- set out buffer set_out_buffer: process(ps_dirs, packets, avai_pos)
variable path_index, out_index : integer;
begin
for i in 0 to TOT_NUM_PATHS-1 loop for i in 0 to TOT_NUM_PATHS-1 loop
buff_wr_in(i).data <= (others => '0'); buff_wr_in(i).data <= (others => '0');
buff_wr_in(i).wr_req <= '0'; buff_wr_in(i).wr_req <= '0';

5
synthesis/cmd/do_synth_all_arbiters.sh
View file

@ -1,5 +0,0 @@
LEVEL=1 NPU=2 NPD=1 dc_shell -f cmd/do_synth_arbiter.tcl | tee log/synthesis.log
LEVEL=2 NPU=4 NPD=2 dc_shell -f cmd/do_synth_arbiter.tcl | tee log/synthesis.log
LEVEL=3 NPU=8 NPD=4 dc_shell -f cmd/do_synth_arbiter.tcl | tee log/synthesis.log
LEVEL=4 NPU=16 NPD=8 dc_shell -f cmd/do_synth_arbiter.tcl | tee log/synthesis.log
LEVEL=5 NPU=32 NPD=16 dc_shell -f cmd/do_synth_parent_arbiter.tcl | tee log/synthesis.log

39
synthesis/cmd/do_synth_arbiter.tcl
View file

@ -1,39 +0,0 @@
set level [getenv LEVEL]
set npu [getenv NPU]
set npd [getenv NPD]
analyze -library WORK -format vhdl {../router/fifo.vhdl}
analyze -library WORK -format vhdl {../router/router_types.vhdl}
analyze -library WORK -format vhdl {../router/routing_functions.vhdl}
analyze -library WORK -format vhdl {../router/receiver.vhdl}
analyze -library WORK -format vhdl {../router/sender.vhdl}
analyze -library WORK -format vhdl {../router/arbiter.vhdl}
elaborate arbiter -library WORK -parameters "level = $level, num_paths_up = $npu, num_paths_down = $npd"
create_clock [get_ports clk] -period 8.0 -waveform {0 4} -name clk
set_clock_uncertainty 0.025 -setup [get_clocks clk]
set_clock_uncertainty 0.025 -hold [get_clocks clk]
set_clock_transition -fall 0.04 [get_clocks clk]
set_clock_transition -rise 0.04 [get_clocks clk]
set_dont_touch clk
set_dont_touch arstN
set_clock_latency -max -source 0.1 [get_clocks clk]
set_input_delay -max -clock clk 0.05 [get_ports {rout_pos packets valid_data avai_paths arb_complete buff_wr_in}]
set_output_delay -max -clock clk 0.05 [all_outputs]
set_false_path -from [get_ports arstN]
check_timing
compile
report_area > reports/arbiter-$level-spl_synth.area
report_power > reports/arbiter-$level-spl_synth.power
change_names -hier -rules vhdl
change_names -hier -rules verilog
write_file -hierarchy -f vhdl -output "./results/arbiter-$level.vhd"
write_file -hierarchy -f verilog -output "./results/arbiter-$level.v"
write_sdf "./results/arbiter-$level.sdf"
write -hierarchy -f ddc -output "./results/arbiter-$level.ddc"

42
synthesis/cmd/do_synth_noc.tcl
View file

@ -1,42 +0,0 @@
analyze -library WORK -format vhdl {../router/fifo.vhdl}
analyze -library WORK -format vhdl {../router/router_types.vhdl}
analyze -library WORK -format vhdl {../router/routing_functions.vhdl}
analyze -library WORK -format vhdl {../router/receiver.vhdl}
analyze -library WORK -format vhdl {../router/sender.vhdl}
analyze -library WORK -format vhdl {../router/arbiter.vhdl}
analyze -library WORK -format vhdl {../router/parent_arbiter.vhdl}
analyze -library WORK -format vhdl {../router/router_components.vhdl}
analyze -library WORK -format vhdl {../router/router.vhdl}
analyze -library WORK -format vhdl {../router/parent_router.vhdl}
analyze -library WORK -format vhdl {../noc/quadtree_components.vhdl}
analyze -library WORK -format vhdl {../noc/quadtree.vhdl}
analyze -library WORK -format vhdl {../noc/noc_conf.vhdl}
read_file -format vhdl {../noc/noc.vhdl}
create_clock [get_ports clk] -period 8.0 -waveform {0 4} -name clk
set_clock_uncertainty 0.025 -setup [get_clocks clk]
set_clock_uncertainty 0.025 -hold [get_clocks clk]
set_clock_transition -fall 0.04 [get_clocks clk]
set_clock_transition -rise 0.04 [get_clocks clk]
set_dont_touch clk
set_dont_touch arstN
set_clock_latency -max -source 0.1 [get_clocks clk]
set_input_delay -max -clock clk 0.05 [get_ports {data_chip_in c_rcv_reqs c_send_ack pe_data_in pe_rcv_reqs pe_send_ack}]
set_output_delay -max -clock clk 0.05 [all_outputs]
set_false_path -from [get_ports arstN]
check_timing
compile
report_area > reports/paicore_noc-spl_synth.area
report_power > reports/paicore_noc-spl_synth.power
change_names -hier -rules vhdl
change_names -hier -rules verilog
write_file -hierarchy -f vhdl -output "./results/paicore_noc.vhd"
write_file -hierarchy -f verilog -output "./results/paicore_noc.v"
write_sdf "./results/paicore_noc.sdf"
write -hierarchy -f ddc -output "./results/paicore_noc.ddc"

39
synthesis/cmd/do_synth_parent_arbiter.tcl
View file

@ -1,39 +0,0 @@
set level [getenv LEVEL]
set npu [getenv NPU]
set npd [getenv NPD]
analyze -library WORK -format vhdl {../router/fifo.vhdl}
analyze -library WORK -format vhdl {../router/router_types.vhdl}
analyze -library WORK -format vhdl {../router/routing_functions.vhdl}
analyze -library WORK -format vhdl {../router/receiver.vhdl}
analyze -library WORK -format vhdl {../router/sender.vhdl}
analyze -library WORK -format vhdl {../router/parent_arbiter.vhdl}
elaborate parent_arbiter -library WORK -parameters "level = $level, num_paths_up = $npu, num_paths_down = $npd"
create_clock [get_ports clk] -period 8.0 -waveform {0 4} -name clk
set_clock_uncertainty 0.025 -setup [get_clocks clk]
set_clock_uncertainty 0.025 -hold [get_clocks clk]
set_clock_transition -fall 0.04 [get_clocks clk]
set_clock_transition -rise 0.04 [get_clocks clk]
set_dont_touch clk
set_dont_touch arstN
set_clock_latency -max -source 0.1 [get_clocks clk]
set_input_delay -max -clock clk 0.05 [get_ports {rout_pos packets valid_data avai_paths arb_complete buff_wr_in}]
set_output_delay -max -clock clk 0.05 [all_outputs]
set_false_path -from [get_ports arstN]
check_timing
compile
report_area > reports/parent-arbiter-$level-spl_synth.area
report_power > reports/parent-arbiter-$level-spl_synth.power
change_names -hier -rules vhdl
change_names -hier -rules verilog
write_file -hierarchy -f vhdl -output "./results/parent-arbiter-$level.vhd"
write_file -hierarchy -f verilog -output "./results/parent-arbiter-$level.v"
write_sdf "./results/parent-arbiter-$level.sdf"
write -hierarchy -f ddc -output "./results/parent-arbiter-$level.ddc"

45
synthesis/cmd/do_synth_router.tcl
View file

@ -1,45 +0,0 @@
set level [getenv LEVEL]
set npu [getenv NPU]
set npd [getenv NPD]
set chip_x [getenv CHIP_X]
set chip_y [getenv CHIP_Y]
analyze -library WORK -format vhdl {../router/fifo.vhdl}
analyze -library WORK -format vhdl {../router/router_types.vhdl}
analyze -library WORK -format vhdl {../router/routing_functions.vhdl}
analyze -library WORK -format vhdl {../router/receiver.vhdl}
analyze -library WORK -format vhdl {../router/sender.vhdl}
analyze -library WORK -format vhdl {../router/arbiter.vhdl}
analyze -library WORK -format vhdl {../router/router.vhdl}
elaborate router -library WORK -parameters
"level = $level, num_paths_up = $npu, num_paths_down = $npd,
buffer_width = 64, buffer_depth = 4, fifo_ptr_size = 3,
chip_x = $chip_x, chip_y = $chip_y"
create_clock [get_ports clk] -period 8.0 -waveform {0 4} -name clk
set_clock_uncertainty 0.025 -setup [get_clocks clk]
set_clock_uncertainty 0.025 -hold [get_clocks clk]
set_clock_transition -fall 0.04 [get_clocks clk]
set_clock_transition -rise 0.04 [get_clocks clk]
set_dont_touch clk
set_dont_touch arstN
set_clock_latency -max -source 0.1 [get_clocks clk]
set_input_delay -max -clock clk 0.05 [get_ports {rout_pos packets valid_data avai_paths arb_complete buff_wr_in}]
set_output_delay -max -clock clk 0.05 [all_outputs]
set_false_path -from [get_ports arstN]
check_timing
compile
report_area > reports/arbiter-$level-spl_synth.area
report_power > reports/arbiter-$level-spl_synth.power
change_names -hier -rules vhdl
change_names -hier -rules verilog
write_file -hierarchy -f vhdl -output "./results/arbiter-$level.vhd"
write_file -hierarchy -f verilog -output "./results/arbiter-$level.v"
write_sdf "./results/arbiter-$level.sdf"
write -hierarchy -f ddc -output "./results/arbiter-$level.ddc"

13
test/noc_tb.vhdl
View file

@ -6,7 +6,6 @@ use ieee.std_logic_textio.all;
use std.textio.all; use std.textio.all;
use work.router_types.all; use work.router_types.all;
use work.quadtree_components.all;
entity noc_tb is entity noc_tb is
end; end;
@ -20,12 +19,10 @@ architecture bench of noc_tb is
constant buffer_depth : integer := 4; constant buffer_depth : integer := 4;
constant fifo_ptr_size : integer := 3; constant fifo_ptr_size : integer := 3;
constant level : integer := 5; constant level : integer := 5;
constant top_level : integer := 5;
constant chip_x : std_logic_vector(4 downto 0) := "00001"; constant chip_x : std_logic_vector(4 downto 0) := "00001";
constant chip_y : std_logic_vector(4 downto 0) := "00001"; constant chip_y : std_logic_vector(4 downto 0) := "00001";
-- Ports -- Ports
signal clk : std_logic; signal clk : std_logic;
signal clks : std_logic_vector(calculate_num_routers(top_level)-1 downto 0);
signal arstN : std_logic; signal arstN : std_logic;
signal data_chip_in : t_DATA_EXT(4*num_paths_ext-1 downto 0); signal data_chip_in : t_DATA_EXT(4*num_paths_ext-1 downto 0);
signal c_rcv_reqs : std_logic_vector(4*num_paths_ext-1 downto 0); signal c_rcv_reqs : std_logic_vector(4*num_paths_ext-1 downto 0);
@ -72,12 +69,11 @@ begin
buffer_depth => buffer_depth, buffer_depth => buffer_depth,
fifo_ptr_size => fifo_ptr_size, fifo_ptr_size => fifo_ptr_size,
level => level, level => level,
top_level => top_level,
chip_x => chip_x, chip_x => chip_x,
chip_y => chip_y chip_y => chip_y
) )
port map ( port map (
clks => clks, clk => clk,
arstN => arstN, arstN => arstN,
data_chip_in => data_chip_in, data_chip_in => data_chip_in,
c_rcv_reqs => c_rcv_reqs, c_rcv_reqs => c_rcv_reqs,
@ -93,13 +89,6 @@ begin
pe_send_reqs => pe_send_reqs pe_send_reqs => pe_send_reqs
); );
map_clocks: process(clk)
begin
for i in calculate_num_routers(top_level)-1 downto 0 loop
clks(i) <= clk;
end loop;
end process;
clock_gen: process clock_gen: process
begin begin
clk <= '0'; clk <= '0';