diff --git a/Readme.md b/Readme.md index 1cd447d..23560e0 100644 --- a/Readme.md +++ b/Readme.md @@ -38,4 +38,5 @@ FIFO5 -> U -> Upstream ### Router ![alt text](./drawings/router.png) --- TODO: Testing Multicast X, Unicast other routers, Broadcast \ No newline at end of file +-- TODO: Sender and receiver +-- TODO: interchip communication \ No newline at end of file diff --git a/arbiter.vhdl b/arbiter.vhdl index 205a287..7b4f10e 100644 --- a/arbiter.vhdl +++ b/arbiter.vhdl @@ -16,7 +16,7 @@ port ( packets : in t_DATA(num_paths_up+num_paths_down*4-1 downto 0); avai_paths : in std_logic_vector(num_paths_up+num_paths_down*4-1 downto 0); arb_complete : out std_logic_vector(num_paths_up+num_paths_down*4-1 downto 0); - buff_wr_in : out t_PORT_WR_IN(num_paths_up+num_paths_down*4-1 downto 0) + buff_wr_in : out t_FIFO_WR_INS(num_paths_up+num_paths_down*4-1 downto 0) --data_out : out t_DATA(num_paths_up+num_paths_down*4-1 downto 0); --wr_req : out std_logic_vector(num_paths_up+num_paths_down*4-1 downto 0) ); @@ -188,7 +188,7 @@ begin end loop; end process; - update_signals: process(clk, arstN) + update_regs: process(clk, arstN) begin if arstN = '0' then avai_pos <= (others => 0); diff --git a/receiver.vhdl b/receiver.vhdl new file mode 100644 index 0000000..78b358e --- /dev/null +++ b/receiver.vhdl @@ -0,0 +1,42 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity Receiver is +port ( + clk, req, accept_ack : in std_logic; + data : in std_logic_vector(63 downto 0); + req_flag, ack : out std_logic; + data_out : out std_logic_vector(63 downto 0) +); +end Receiver; + +architecture impl of Receiver is + signal req1, req2, req3, req_nxt : std_logic; + signal req_mux, upd_req, upd_req_nxt : std_logic; + signal req_edge, ack_nxt, upd_ack : std_logic; + signal req_flag1, req_flag2, req_flag3 : std_logic; + signal data_nxt : std_logic_vector(63 downto 0); +begin + req_edge <= req2 xor req3; + upd_ack <= accept_ack and req_flag2; + req_flag1 <= '1' when req_edge = '1' else '0' + when upd_ack = '1' else req_flag2; + ack_nxt <= not ack when (upd_ack) = '1' else ack; + + req_flag <= req_flag3 and (not req_flag2); + data_nxt <= data when req_edge = '1' else data_out; + + update_regs: process(clk) + begin + if rising_edge(clk) then + req1 <= req; + req2 <= req1; + req3 <= req2; + req_flag2 <= req_flag1; + req_flag3 <= req_flag2; + ack <= ack_nxt; + data_out <= data_nxt; + end if; + end process; +end impl; \ No newline at end of file diff --git a/router.vhdl b/router.vhdl index a797879..b7ac37b 100644 --- a/router.vhdl +++ b/router.vhdl @@ -3,7 +3,6 @@ use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.router_types.all; -use work.routing_functions.all; use work.router_components.all; entity router is @@ -22,21 +21,28 @@ generic ( port ( clk : in std_logic; arstN : in std_logic; - rcv_buff_wr_in : in t_PORT_WR_IN(num_paths_up+num_paths_down*4-1 downto 0); - snd_buff_rd_in : in std_logic_vector(num_paths_up+num_paths_down*4-1 downto 0); - snd_buff_out : out t_PORT_OUT(num_paths_up+num_paths_down*4-1 downto 0) + data_in : in t_DATA(num_paths_up+num_paths_down*4-1 downto 0); + rcv_reqs : in std_logic_vector(num_paths_up+num_paths_down*4-1 downto 0); + send_ack : in std_logic_vector(num_paths_up+num_paths_down*4-1 downto 0); + rcv_acks : out std_logic_vector(num_paths_up+num_paths_down*4-1 downto 0); + send_reqs : out std_logic_vector(num_paths_up+num_paths_down*4-1 downto 0); + data_out : out t_DATA(num_paths_up+num_paths_down*4-1 downto 0) ); end router; architecture impl of router is - constant TOT_NUM_PATHS : positive := num_paths_up + num_paths_down*4; + constant TOT_NUM_PATHS : positive := num_paths_up + num_paths_down*4; signal rout_pos : t_pos_addr; - signal rcv_buff_out : t_PORT_OUT(TOT_NUM_PATHS-1 downto 0); - signal snd_buff_wr_in : t_PORT_WR_IN(TOT_NUM_PATHS-1 downto 0); - signal snd_buff_out_nxt : t_PORT_OUT(TOT_NUM_PATHS-1 downto 0); + signal rcv_buff_wr_in : t_FIFO_WR_INS(num_paths_up+num_paths_down*4-1 downto 0); + signal rcv_buff_out : t_FIFO_OUTS(TOT_NUM_PATHS-1 downto 0); + signal snd_buff_wr_in : t_FIFO_WR_INS(TOT_NUM_PATHS-1 downto 0); + signal snd_buff_out : t_FIFO_OUTS(num_paths_up+num_paths_down*4-1 downto 0); + signal snd_buff_rd_in : std_logic_vector(num_paths_up+num_paths_down*4-1 downto 0); + signal rcv_accept_ack : std_logic_vector(num_paths_up+num_paths_down*4-1 downto 0); signal rd_data, rd_data_nxt : t_DATA(TOT_NUM_PATHS-1 downto 0); signal rd_reqs : std_logic_vector(TOT_NUM_PATHS-1 downto 0); + signal snd_data_rd_reqs : std_logic_vector(TOT_NUM_PATHS-1 downto 0); signal avai_paths : std_logic_vector(TOT_NUM_PATHS-1 downto 0); signal arb_complete : std_logic_vector(TOT_NUM_PATHS-1 downto 0); signal packet_states : t_PACKET_STATES(TOT_NUM_PATHS-1 downto 0); @@ -58,8 +64,23 @@ begin F_PTR_SIZE => fifo_ptr_size) port map(arstN => arstN, clk => clk, wr_req => snd_buff_wr_in(i).wr_req, rd_req => snd_buff_rd_in(i), data_in => snd_buff_wr_in(i).data, - data_out => snd_buff_out_nxt(i).data, - full => snd_buff_out_nxt(i).full, empty => snd_buff_out_nxt(i).empty); + data_out => snd_buff_out(i).data, + full => snd_buff_out(i).full, empty => snd_buff_out(i).empty); + end generate; + + g_SENDER_GEN: for i in 0 to TOT_NUM_PATHS-1 generate + output_sender: sender + port map(clk => clk, send_req => snd_data_rd_reqs(i), + ack => send_ack(i), data_in => snd_buff_out(i).data, + req => send_reqs(i), rd_req => snd_buff_rd_in(i), + data => data_out(i)); + end generate; + + g_RECEIVER_GEN: for i in 0 to TOT_NUM_PATHS-1 generate + output_receiver: receiver + port map(clk => clk, req => rcv_reqs(i), accept_ack => rcv_accept_ack(i), + data => data_in(i), req_flag => rcv_buff_wr_in(i).wr_req, + ack => rcv_acks(i), data_out => rcv_buff_wr_in(i).data); end generate; arbiter0: arbiter @@ -78,10 +99,18 @@ begin buff_wr_in => snd_buff_wr_in ); - set_avai_paths: process(snd_buff_out_nxt) + set_rcv_accept_ack: process(rcv_buff_wr_in) begin for i in 0 to TOT_NUM_PATHS-1 loop - avai_paths(i) <= not snd_buff_out_nxt(i).full; + rcv_accept_ack(i) <= not rcv_buff_out(i).full; + end loop; + end process; + + set_avai_paths: process(snd_buff_out) + begin + for i in 0 to TOT_NUM_PATHS-1 loop + avai_paths(i) <= not snd_buff_out(i).full; + snd_data_rd_reqs(i) <= not snd_buff_out(i).empty; end loop; end process; @@ -136,7 +165,7 @@ begin end loop; end process; - update_signals: process(arstN, clk) + update_regs: process(arstN, clk) begin if arstN = '0' then rout_pos.chip_x <= chip_x; @@ -148,7 +177,6 @@ begin packet_states <= (others => Idle); rd_data <= (others => (others => '0')); elsif rising_edge(clk) then - snd_buff_out <= snd_buff_out_nxt; packet_states <= packet_states_nxt; rd_data <= rd_data_nxt; end if; diff --git a/router_components.vhdl b/router_components.vhdl index 5e8fd26..e9fbd6b 100644 --- a/router_components.vhdl +++ b/router_components.vhdl @@ -18,6 +18,24 @@ package router_components is ); end component fifo; + component Sender is + port ( + clk, send_req, ack : in std_logic; + data_in : in std_logic_vector(63 downto 0); + req, rd_req : out std_logic; + data : out std_logic_vector(63 downto 0) + ); + end component Sender; + + component Receiver is + port ( + clk, req, accept_ack : in std_logic; + data : in std_logic_vector(63 downto 0); + req_flag, ack : out std_logic; + data_out : out std_logic_vector(63 downto 0) + ); + end component Receiver; + component arbiter is generic( level : integer := 1; @@ -32,7 +50,7 @@ package router_components is num_paths_up+num_paths_down*4-1 downto 0); arb_complete : out std_logic_vector( num_paths_up+num_paths_down*4-1 downto 0); - buff_wr_in : out t_PORT_WR_IN( + buff_wr_in : out t_FIFO_WR_INS( num_paths_up+num_paths_down*4-1 downto 0) ); end component arbiter; diff --git a/router_types.vhdl b/router_types.vhdl index 00d02a7..e7ce4c2 100644 --- a/router_types.vhdl +++ b/router_types.vhdl @@ -9,7 +9,7 @@ package router_types is constant NUM_DIRS : integer := 5; constant DEST_ADDR_SIZE : integer := 5; constant CHIP_ADDR_SIZE : integer := 5; -- * - constant MAX_PATHS_SIZE : integer := 48; + constant MAX_PATHS_SIZE : integer := 96; subtype WORD is std_logic_vector(63 downto 0); type t_PACKET_STATE is (Idle, Arbitration, InArbQueue); @@ -41,11 +41,11 @@ package router_types is copy_y : std_logic_vector(DEST_ADDR_SIZE-1 downto 0); end record; - type t_PORT_WR_IN is array (integer range <>) of t_fifo_wr_in; - type t_PORT_RD_IN is array (integer range <>) of std_logic; -- rd_req - type t_PORT_OUT is array (integer range <>) of t_fifo_out; - type t_DATA is array (integer range <>) of WORD; - type t_DATA_DIRS is array (integer range <>) of + type t_FIFO_WR_INS is array (integer range <>) of t_fifo_wr_in; + type t_FIFO_RD_INS is array (integer range <>) of std_logic; -- rd_req + type t_FIFO_OUTS is array (integer range <>) of t_fifo_out; + type t_DATA is array (integer range <>) of WORD; + type t_DATA_DIRS is array (integer range <>) of std_logic_vector(NUM_DIRS-1 downto 0); end package; diff --git a/routing_functions.vhdl b/routing_functions.vhdl index 1280563..be056de 100644 --- a/routing_functions.vhdl +++ b/routing_functions.vhdl @@ -39,18 +39,23 @@ package body routing_functions is copy_y := pack_dest.copy_y(level-1); is_other_chip := pack_dest.chip_x /= rout_pos.chip_x or pack_dest.chip_y /= rout_pos.chip_y; - is_cousin_core := (pack_dest.core_x(DEST_ADDR_SIZE-1 downto level) /= - rout_pos.core_x(DEST_ADDR_SIZE-1 downto level)) or - (pack_dest.core_y(DEST_ADDR_SIZE-1 downto level) /= - rout_pos.core_y(DEST_ADDR_SIZE-1 downto level)); - --pack_dest.core_x(DEST_ADDR_SIZE-1 downto level) /= rout_pos.core_x or - --pack_dest.core_y(DEST_ADDR_SIZE-1 downto level) /= rout_pos.core_y; + if level /=5 then + is_cousin_core := (pack_dest.core_x(DEST_ADDR_SIZE-1 downto level) /= + rout_pos.core_x(DEST_ADDR_SIZE-1 downto level)) or + (pack_dest.core_y(DEST_ADDR_SIZE-1 downto level) /= + rout_pos.core_y(DEST_ADDR_SIZE-1 downto level)); + --pack_dest.core_x(DEST_ADDR_SIZE-1 downto level) /= rout_pos.core_x or + --pack_dest.core_y(DEST_ADDR_SIZE-1 downto level) /= rout_pos.core_y; + else + is_cousin_core := FALSE; + end if; needs_multicast := FALSE; for i in level to DEST_ADDR_SIZE-1 loop needs_multicast := needs_multicast or (pack_dest.copy_x(i) = '1') or (pack_dest.copy_y(i) = '1'); end loop; + -- if it comes from upstream, it shouldn't go back to upstream if (not is_upstream) and (is_other_chip or is_cousin_core or needs_multicast) then return "10000"; elsif copy_x = '0' and copy_y = '0' then --unicast diff --git a/sender.vhdl b/sender.vhdl new file mode 100644 index 0000000..0590881 --- /dev/null +++ b/sender.vhdl @@ -0,0 +1,39 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity Sender is +port ( + clk, send_req, ack : in std_logic; + data_in : in std_logic_vector(63 downto 0); + req, rd_req : out std_logic; + data : out std_logic_vector(63 downto 0) +); +end Sender; + +architecture impl of Sender is + signal ack1, ack2, ack3, req_nxt : std_logic; + signal req_mux, upd_req, upd_req_nxt : std_logic; + signal ack_edge, data_nxt_mux : std_logic; + signal data_nxt : std_logic_vector(63 downto 0); +begin + upd_req_nxt <= '0' when upd_req = '1' else '1' + when ack_edge = '1' else upd_req; + data_nxt_mux <= '1' when upd_req = '1' and send_req = '1' else '0'; + req_nxt <= not req when data_nxt_mux else req; + rd_req <= data_nxt_mux; + ack_edge <= ack2 xor ack3; + data_nxt <= data_in when data_nxt_mux = '1' else data; + + update_regs: process(clk) + begin + if rising_edge(clk) then + ack1 <= ack; + ack2 <= ack1; + ack3 <= ack2; + upd_req <= upd_req_nxt; + req <= req_nxt; + data <= data_nxt; + end if; + end process; +end impl; \ No newline at end of file diff --git a/test/input/L1_multicastY/config.txt b/test/input/L1_multicastY/config.txt new file mode 100644 index 0000000..211ac2f --- /dev/null +++ b/test/input/L1_multicastY/config.txt @@ -0,0 +1,4 @@ +0000000000 # corex|corey +1 # level +1 # num path down +2 # num path up \ No newline at end of file diff --git a/test/input/L1_multicastY/stimuli.txt b/test/input/L1_multicastY/stimuli.txt index 5a96c89..b523861 100644 --- a/test/input/L1_multicastY/stimuli.txt +++ b/test/input/L1_multicastY/stimuli.txt @@ -1,11 +1,11 @@ +10001000000000010101101011001010001000000000000000000000000000011 # U +00000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000 10001000000000010101101011001010001000000000000000000000000000011 # copy Y, dest 1- -> DS3, DS4 00000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000 -10001000000000010101101011001010001000000000000000000000000000011 -00000000000000000000000000000000000000000000000000000000000000000 -00001000000000010101101011001010001000000000000000000000000000011 -00000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000 diff --git a/test/input/L1_unicast/config.txt b/test/input/L1_unicast/config.txt new file mode 100644 index 0000000..211ac2f --- /dev/null +++ b/test/input/L1_unicast/config.txt @@ -0,0 +1,4 @@ +0000000000 # corex|corey +1 # level +1 # num path down +2 # num path up \ No newline at end of file diff --git a/test/input/L1_unicast/result.ref b/test/input/L1_unicast/result.ref index cb438cb..c4837e3 100644 --- a/test/input/L1_unicast/result.ref +++ b/test/input/L1_unicast/result.ref @@ -4,5 +4,5 @@ 0001000000000000000000000000000000000000000000000000000000000111 0001000001000010001000010000000000000000000000000000000000000100 0001000001000010001000010000000000000000000000000000000000001000 -0001000001000010001000010000000000000000000000000000000000000110 -0001000001000010001000010000000000000000000000000000000000001010 \ No newline at end of file +0001000001000010001000010000000000000000000000000000000000001010 +0001000001000010001000010000000000000000000000000000000000000110 \ No newline at end of file diff --git a/test/input/L1_unicast/stimuli.txt b/test/input/L1_unicast/stimuli.txt index effebf5..9c60a84 100644 --- a/test/input/L1_unicast/stimuli.txt +++ b/test/input/L1_unicast/stimuli.txt @@ -1,16 +1,16 @@ -10001000000000000001000010000000000000000000000000000000000000011 # DS1 +10001000000000000001000010000000000000000000000000000000000000011 # DS4 00000000000000000000000000000000000000000000000000000000000000000 10001000001000010001000010000000000000000000000000000000000000100 # U -00000000000000000000000000000000000000000000000000000000000000000 -10001000000000000000000010000000000000000000000000000000000000101 # DS3 10001000001000010001000010000000000000000000000000000000000000110 # U -10001000000000000000000000000000000000000000000000000000000000111 # DS4 00000000000000000000000000000000000000000000000000000000000000000 +10001000000000000000000010000000000000000000000000000000000000101 # DS2 +10001000000000000000000000000000000000000000000000000000000000111 # DS1 10001000001000010001000010000000000000000000000000000000000001000 # U 00000000000000000000000000000000000000000000000000000000000000000 -10001000000000000001000000000000000000000000000000000000000001001 # DS2 10001000001000010001000010000000000000000000000000000000000001010 # U 00000000000000000000000000000000000000000000000000000000000000000 +10001000000000000001000000000000000000000000000000000000000001001 # DS3 +00000000000000000000000000000000000000000000000000000000000000000 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diff --git a/test/input/L2_multicastX/stimuli.txt b/test/input/L2_multicastX/stimuli.txt new file mode 100644 index 0000000..500568d --- /dev/null +++ b/test/input/L2_multicastX/stimuli.txt @@ -0,0 +1,24 @@ +10001000001000010001000010000000000000000000000000000000000000111 # U +00000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000 +10001000001000010001000010000000000000000000000000000000000000101 # U +00000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000 +10001000000000010101101011001010001000000000000000000000000000011 # copy X, dest -0 -> DS1, DS3 +00000000000000000000000000000000000000000000000000000000000000000 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b/test/input/L2_unicast/config.txt new file mode 100644 index 0000000..02108cc --- /dev/null +++ b/test/input/L2_unicast/config.txt @@ -0,0 +1,4 @@ +000--000-- # corex|corey +2 # level +2 # num path down +4 # num path up \ No newline at end of file diff --git a/test/input/L2_unicast/result.ref b/test/input/L2_unicast/result.ref new file mode 100644 index 0000000..1b55edf --- /dev/null +++ b/test/input/L2_unicast/result.ref @@ -0,0 +1,14 @@ +0001000000000000011000110000000000000000000000000000000000000011 +0001000000000000011000110000000000000000000000000000000000001010 +0001000000000000011000000000000000000000000000000000000000001001 +0001000000000000011000000000000000000000000000000000000000010000 +0001000000000000000000110000000000000000000000000000000000001000 +0001000000000000000000110000000000000000000000000000000000001111 +0001000000000000000000000000000000000000000000000000000000000110 +0001000000000000000000000000000000000000000000000000000000001101 +0001000001000010001000010000000000000000000000000000000000000100 +0001000001000010001000010000000000000000000000000000000000001011 +0001000001000010001000010000000000000000000000000000000000001110 +0001000001000010001000010000000000000000000000000000000000000101 +0001000001000010001000010000000000000000000000000000000000001100 +0001000001000010001000010000000000000000000000000000000000000111 \ No newline at end of file diff --git a/test/input/L2_unicast/stimuli.txt b/test/input/L2_unicast/stimuli.txt new file mode 100644 index 0000000..c86c5d1 --- /dev/null +++ b/test/input/L2_unicast/stimuli.txt @@ -0,0 +1,36 @@ +10001000000000000011000110000000000000000000000000000000000000011 # DS4 +00000000000000000000000000000000000000000000000000000000000000000 +10001000001000010001000010000000000000000000000000000000000000100 # U +00000000000000000000000000000000000000000000000000000000000000000 +10001000001000010001000010000000000000000000000000000000000000101 # U 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+00000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000 # Router L2 000--,000-- \ No newline at end of file diff --git a/test/input/L5_multicast4/config.txt b/test/input/L5_multicast4/config.txt new file mode 100644 index 0000000..cb03505 --- /dev/null +++ b/test/input/L5_multicast4/config.txt @@ -0,0 +1,4 @@ +---------- # corex|corey +5 # level +16 # num path down +32 # num path up \ No newline at end of file diff --git a/test/input/L5_multicast4/result.ref b/test/input/L5_multicast4/result.ref new file mode 100644 index 0000000..9175abc --- /dev/null +++ b/test/input/L5_multicast4/result.ref @@ -0,0 +1,4 @@ +0001000000000010101101011001010001000000000000000000000000000011 +0001000000000010101101011001010001000000000000000000000000000011 +0001000000000010101101011001010001000000000000000000000000000011 +0001000000000010101101011001010001000000000000000000000000000011 \ No newline at end of file diff --git a/test/input/L5_multicast4/stimuli.txt b/test/input/L5_multicast4/stimuli.txt new file mode 100644 index 0000000..ab9e1d4 --- /dev/null +++ b/test/input/L5_multicast4/stimuli.txt @@ -0,0 +1,192 @@ +00000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000 +10001000000000010101101011001010001000000000000000000000000000011 # copy 4x, dest -- -> DS1, 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b/test/router_tb.vhdl index 279be0e..2bd9d54 100644 --- a/test/router_tb.vhdl +++ b/test/router_tb.vhdl @@ -5,6 +5,11 @@ use work.router_types.all; use ieee.std_logic_textio.all; use std.textio.all; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + entity router_tb is end; @@ -17,18 +22,23 @@ architecture bench of router_tb is constant level : integer := 1; constant buffer_width : integer := 64; constant buffer_depth : integer := 4; - constant fifo_ptr_size: integer := 3; + constant fifo_ptr_size : integer := 3; constant chip_x : std_logic_vector(4 downto 0) := (others => '0'); constant chip_y : std_logic_vector(4 downto 0) := (others => '0'); - constant core_x : std_logic_vector(4 downto 0) := "0010-"; - constant core_y : std_logic_vector(4 downto 0) := "0010-"; + constant core_x : std_logic_vector(4 downto 0) := (others => '0'); + constant core_y : std_logic_vector(4 downto 0) := (others => '0'); -- Ports - signal clk : std_logic; - signal arstN : std_logic; - signal rcv_buff_wr_in : t_PORT_WR_IN(num_paths_up+num_paths_down*4-1 downto 0); - signal snd_buff_rd_in : std_logic_vector(num_paths_up+num_paths_down*4-1 downto 0); - signal snd_buff_out : t_PORT_OUT(num_paths_up+num_paths_down*4-1 downto 0); + signal clk : std_logic; + signal arstN : std_logic; + signal data_in : t_DATA(num_paths_up+num_paths_down*4-1 downto 0); + signal rcv_reqs : std_logic_vector(num_paths_up+num_paths_down*4-1 downto 0); + signal send_ack : std_logic_vector(num_paths_up+num_paths_down*4-1 downto 0); + signal send_ack_nxt : std_logic_vector(num_paths_up+num_paths_down*4-1 downto 0); + signal rcv_acks : std_logic_vector(num_paths_up+num_paths_down*4-1 downto 0); + signal send_reqs : std_logic_vector(num_paths_up+num_paths_down*4-1 downto 0); + signal data_out : t_DATA(num_paths_up+num_paths_down*4-1 downto 0); + file conf_file : text open read_mode is "config.txt"; file stimuli_file : text open read_mode is "stimuli.txt"; file reference_file : text open read_mode is "result.ref"; file log_file : text open write_mode is "simulation.log"; @@ -50,11 +60,13 @@ begin port map ( clk => clk, arstN => arstN, - rcv_buff_wr_in => rcv_buff_wr_in, - snd_buff_rd_in => snd_buff_rd_in, - snd_buff_out => snd_buff_out + data_in => data_in, + rcv_reqs => rcv_reqs, + send_ack => send_ack, + rcv_acks => rcv_acks, + send_reqs => send_reqs, + data_out => data_out ); --- clk <= not clk after clk_period/2; clock_gen: process begin @@ -68,13 +80,10 @@ begin variable input_line, rowOut : line; variable valid_data : boolean; variable stimuli : std_logic_vector(64 downto 0); - variable istwert, sollwert : WORD; variable index_path : integer; - variable test_passed : boolean; begin - test_passed := TRUE; arstN <= '0'; - snd_buff_rd_in <= (others => '0'); + rcv_reqs <= (others => '0'); wait until rising_edge(clk); -- writing and arbitration arstN <= '1'; @@ -84,29 +93,33 @@ begin read(input_line, stimuli, valid_data); assert valid_data report "Invalid data in file" severity error; - rcv_buff_wr_in(index_path).data <= stimuli(63 downto 0); - rcv_buff_wr_in(index_path).wr_req <= stimuli(64); + data_in(index_path) <= stimuli(63 downto 0); + rcv_reqs(index_path) <= stimuli(64); index_path := index_path + 1; if index_path = num_paths_down*4 + num_paths_up then - wait until rising_edge(clk); + wait until rcv_acks(index_path-1)='1'; index_path := 0; end if; exit when endfile(stimuli_file); end loop; wait until rising_edge(clk); - wait for clk_period*5; + wait; + end process; - -- reading from send fifo and validating - wait until rising_edge(clk); + validate_routed_data: process(send_reqs, data_out, send_ack) + variable input_line, rowOut : line; + variable valid_data : boolean; + variable confi : std_logic_vector(9 downto 0); + variable istwert, sollwert : WORD; + variable test_passed : boolean; + begin + test_passed := TRUE; for i in 0 to num_paths_down*4+num_paths_up-1 loop - while snd_buff_out(i).empty = '0' loop - istwert := snd_buff_out(i).data; - snd_buff_rd_in(i) <= '1'; - wait until rising_edge(clk); - snd_buff_rd_in(i) <= '0'; - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); + if send_ack(i) = '1' then + send_ack_nxt(i) <= '0'; + elsif send_reqs(i) = '1' then + istwert := data_out(i); + send_ack_nxt(i) <= '1'; readline(reference_file, input_line); read(input_line, sollwert, valid_data); assert valid_data report "Invalid data in file" severity error; @@ -133,21 +146,26 @@ begin WRITELINE(log_file, rowOut); test_passed := test_passed and FALSE; end if; - exit when endfile(reference_file); - end loop; + else + send_ack_nxt(i) <= '0'; + end if; exit when endfile(reference_file); end loop; - wait until rising_edge(clk); - if not endfile(reference_file) then - test_passed := FALSE; + if endfile(reference_file) then + if test_passed then + write(rowOut, string'("All tests passed successfully!")); + WRITELINE(log_file, rowOut); + else + write(rowOut, string'("One or more tests failed")); + WRITELINE(log_file, rowOut); + end if; end if; - if test_passed then - write(rowOut, string'("All tests passed successfully!")); - WRITELINE(log_file, rowOut); - else - write(rowOut, string'("One or more tests failed")); - WRITELINE(log_file, rowOut); - end if; - wait; end process; -end architecture; \ No newline at end of file + + update_signals: process(clk) + begin + if rising_edge(clk) then + send_ack <= send_ack_nxt; + end if; + end process; +end;