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Author SHA1 Message Date
Retrocamara42
658a95604f fix: tcl scripts updated 2025-07-18 05:17:52 -05:00
Retrocamara42
534abb2757 fix: compilation and runtime bugs fixed 2025-07-18 05:09:06 -05:00
31 changed files with 2143032 additions and 1357319 deletions
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28
arbiter/arbiter.vhdl
View file

@ -6,7 +6,7 @@ use work.arbiter_functions.all;
entity arbiter is entity arbiter is
generic( generic(
level : positive := 1; level : natural := 1;
num_paths_up : positive := 2; num_paths_up : positive := 2;
num_paths_down : positive := 1; num_paths_down : positive := 1;
lsb_size_up : positive := 2; lsb_size_up : positive := 2;
@ -47,12 +47,12 @@ architecture impl of arbiter is
type t_PORT_DIRS is array (natural range <>) of type t_PORT_DIRS is array (natural range <>) of
std_logic_vector(TOT_NUM_PATHS-1 downto 0); std_logic_vector(TOT_NUM_PATHS-1 downto 0);
signal dirs : t_DATA_DIRS_EXT(TOT_NUM_PATHS-1 downto 0); signal dirs : t_DATA_DIRS(TOT_NUM_PATHS-1 downto 0);
signal port_dirs : t_PORT_DIRS(NUM_DIRS_PARENT-1 downto 0); signal port_dirs : t_PORT_DIRS(NUM_DIRS-1 downto 0);
signal updated_dirs : t_DATA_DIRS_EXT(TOT_NUM_PATHS-1 downto 0); signal updated_dirs : t_DATA_DIRS(TOT_NUM_PATHS-1 downto 0);
signal updated_port_dirs : t_PORT_DIRS(NUM_DIRS_PARENT-1 downto 0); signal updated_port_dirs : t_PORT_DIRS(NUM_DIRS-1 downto 0);
signal ps_dirs : t_DATA_DIRS_EXT(TOT_NUM_PATHS-1 downto 0); signal ps_dirs : t_DATA_DIRS(TOT_NUM_PATHS-1 downto 0);
signal ps_dirs_nxt : t_DATA_DIRS_EXT(TOT_NUM_PATHS-1 downto 0); signal ps_dirs_nxt : t_DATA_DIRS(TOT_NUM_PATHS-1 downto 0);
signal out_packets : t_DATA(TOT_NUM_PATHS-1 downto 0); signal out_packets : t_DATA(TOT_NUM_PATHS-1 downto 0);
signal packets_1d : t_DATA(TOT_NUM_PATHS-1 downto 0); signal packets_1d : t_DATA(TOT_NUM_PATHS-1 downto 0);
signal packets_1d_nxt : t_DATA(TOT_NUM_PATHS-1 downto 0); signal packets_1d_nxt : t_DATA(TOT_NUM_PATHS-1 downto 0);
@ -87,7 +87,7 @@ begin
port_dirs(i)(p) <= ps_dirs(p)(i); port_dirs(i)(p) <= ps_dirs(p)(i);
end generate; end generate;
ds_port_arbiter_unit: arbiter_unit ds_arbiter_unit: arbiter_unit
generic map( generic map(
num_paths_in => TOT_NUM_PATHS, num_paths_in => TOT_NUM_PATHS,
num_paths_out => num_paths_down, num_paths_out => num_paths_down,
@ -107,7 +107,7 @@ begin
port_dirs(NUM_DIRS-1)(p) <= ps_dirs(p)(NUM_DIRS-1); port_dirs(NUM_DIRS-1)(p) <= ps_dirs(p)(NUM_DIRS-1);
end generate; end generate;
u_port_arbiter_unit: arbiter_unit u_arbiter_unit: arbiter_unit
generic map( generic map(
num_paths_in => TOT_NUM_PATHS, num_paths_in => TOT_NUM_PATHS,
num_paths_out => num_paths_up, num_paths_out => num_paths_up,
@ -128,28 +128,28 @@ begin
end generate; end generate;
g_updated_dirs: for p in 0 to TOT_NUM_PATHS-1 generate g_updated_dirs: for p in 0 to TOT_NUM_PATHS-1 generate
g_updated_dir: for i in 0 to NUM_DIRS_PARENT-1 generate g_updated_dir: for i in 0 to NUM_DIRS-1 generate
updated_dirs(p)(i) <= updated_port_dirs(i)(p); updated_dirs(p)(i) <= updated_port_dirs(i)(p);
end generate; end generate;
end generate; end generate;
set_ps_dirs_nxt: process(dirs, updated_dirs, packets_1d, packets) set_ps_dirs_nxt: process(dirs, updated_dirs, packets_1d, packets)
type t_OR_DIRS is array(natural range<>) of std_logic_vector(NUM_DIRS_PARENT-1 downto 0); type t_OR_DIRS is array(natural range<>) of std_logic_vector(NUM_DIRS-1 downto 0);
variable or_dirs : t_OR_DIRS(TOT_NUM_PATHS-1 downto 0); variable or_dirs : t_OR_DIRS(TOT_NUM_PATHS-1 downto 0);
begin begin
for i in 0 to TOT_NUM_PATHS-1 loop for i in 0 to TOT_NUM_PATHS-1 loop
or_dirs(i)(0) := updated_dirs(i)(0); or_dirs(i)(0) := updated_dirs(i)(0);
for j in 1 to NUM_DIRS_PARENT-1 loop for j in 1 to NUM_DIRS-1 loop
or_dirs(i)(j) := or_dirs(i)(j-1) or updated_dirs(i)(j); or_dirs(i)(j) := or_dirs(i)(j-1) or updated_dirs(i)(j);
end loop; end loop;
if or_dirs(i)(NUM_DIRS_PARENT-1) = '0' then if or_dirs(i)(NUM_DIRS-1) = '0' then
ps_dirs_nxt(i) <= dirs(i); ps_dirs_nxt(i) <= dirs(i);
packets_1d_nxt(i) <= packets(i); packets_1d_nxt(i) <= packets(i);
else else
ps_dirs_nxt(i) <= updated_dirs(i); ps_dirs_nxt(i) <= updated_dirs(i);
packets_1d_nxt(i) <= packets_1d(i); packets_1d_nxt(i) <= packets_1d(i);
end if; end if;
arb_complete(i) <= not or_dirs(i)(NUM_DIRS_PARENT-1); arb_complete(i) <= not or_dirs(i)(NUM_DIRS-1);
end loop; end loop;
end process; end process;

261
arbiter/arbiter_unit.vhdl
View file

@ -6,9 +6,9 @@ use work.encoder_components.all;
entity arbiter_unit is entity arbiter_unit is
generic( generic(
num_paths_in : positive := 2; num_paths_in : positive := 6;
num_paths_out : positive := 1; num_paths_out : positive := 1;
lsb_sels_size : positive := 4 lsb_sels_size : positive := 3
); );
port ( port (
dirs : in std_logic_vector(num_paths_in-1 downto 0); dirs : in std_logic_vector(num_paths_in-1 downto 0);
@ -21,6 +21,15 @@ port (
end arbiter_unit; end arbiter_unit;
architecture rtl of arbiter_unit is architecture rtl of arbiter_unit is
constant NPI : integer := num_paths_in;
constant NPO : positive := num_paths_out;
constant NUM_ENCODERS : integer := get_num_encoders(NPI);
constant ENC_SIZE : positive := get_encoder_size(NPI);
type t_N_LSB_SELS is array(natural range<>) of std_logic_vector(lsb_sels_size-1 downto 0); -- size depends on num_paths_out
type t_GRANT_DIRS is array(natural range<>) of std_logic_vector(NPI-1 downto 0);
type t_SELECTORS is array(natural range<>) of std_logic_vector(get_dout_size(ENC_SIZE)-1 downto 0);
component NthLsbDetector is component NthLsbDetector is
generic( generic(
num_dirs : positive := 1; num_dirs : positive := 1;
@ -32,21 +41,21 @@ architecture rtl of arbiter_unit is
); );
end component NthLsbDetector; end component NthLsbDetector;
type t_N_LSB_SELS is array(natural range<>) of std_logic_vector(lsb_sels_size-1 downto 0); -- size depends on num_paths_out signal selectors : t_SELECTORS(NUM_ENCODERS*NPO-1 downto 0);
type t_GRANT_DIRS is array(natural range<>) of std_logic_vector(num_paths_in-1 downto 0); signal valids : std_logic_vector(NUM_ENCODERS*NPO-1 downto 0);
signal packet_index : integer range 0 to NPI;
signal n_lsb_sels : t_N_LSB_SELS(num_paths_out-1 downto 0); signal n_lsb_sels : t_N_LSB_SELS(NPO-1 downto 0);
signal nlsb_grant_dirs : t_GRANT_DIRS(num_paths_out-1 downto 0); signal nlsb_grant_dirs : t_GRANT_DIRS(NPO-1 downto 0);
signal grant_dirs : t_GRANT_DIRS(num_paths_out-1 downto 0); signal grant_dirs : t_GRANT_DIRS(NPO-1 downto 0);
begin begin
set_n_lsb_sel: process(avai_paths) set_n_lsb_sel: process(avai_paths)
type t_SUM_AVAI_PATHS is array(natural range<>) of integer range 0 to num_paths_out; type t_SUM_AVAI_PATHS is array(natural range<>) of integer range 0 to NPO;
variable sum_avai_paths : t_SUM_AVAI_PATHS(num_paths_out-1 downto 0); variable sum_avai_paths : t_SUM_AVAI_PATHS(NPO-1 downto 0);
begin begin
sum_avai_paths(0) := 0; sum_avai_paths(0) := 0;
n_lsb_sels(0) <= (others => '0'); n_lsb_sels(0) <= (others => '0');
for i in 1 to num_paths_out-1 loop for i in 1 to NPO-1 loop
if avai_paths(0) = '1' then if avai_paths(0) = '1' then
sum_avai_paths(i) := sum_avai_paths(i-1)+1; sum_avai_paths(i) := sum_avai_paths(i-1)+1;
else else
@ -56,218 +65,66 @@ begin
end loop; end loop;
end process; end process;
g_NLSB_UNIT: for i in 0 to num_paths_out-1 generate g_NLSB_UNIT: for i in 0 to NPO-1 generate
nlsb_detector: NthLsbDetector nlsb_detector: NthLsbDetector
generic map(num_dirs => num_paths_in, n => i+1) generic map(num_dirs => NPI, n => i+1)
port map(dirs => dirs, grant_dirs => nlsb_grant_dirs(i)); port map(dirs => dirs, grant_dirs => nlsb_grant_dirs(i));
end generate; end generate;
g_grant_dirs: for i in 0 to num_paths_out-1 generate g_grant_dirs: for i in 0 to NPO-1 generate
grant_dirs(i) <= nlsb_grant_dirs(to_integer(unsigned(n_lsb_sels(i)))); grant_dirs(i) <= nlsb_grant_dirs(to_integer(unsigned(n_lsb_sels(i))));
end generate; end generate;
g_encoders: for i in 0 to NPO-1 generate
g_L5_Encoders: if num_paths_in = 192 generate
constant MUX_SIZE : positive := 5;
constant NUM_ENCODERS : positive := 6;
type t_SELECTORS is array(natural range<>) of std_logic_vector(MUX_SIZE-1 downto 0);
signal selectors : t_SELECTORS(NUM_ENCODERS*num_paths_out-1 downto 0);
signal valids : std_logic_vector(NUM_ENCODERS*num_paths_out-1 downto 0);
signal packet_index : integer range 0 to 192;
begin
g_encoders: for i in 0 to num_paths_out-1 generate
begin begin
g_encoder: for e in 0 to NUM_ENCODERS-1 generate g_encoder: for e in 0 to NUM_ENCODERS-1 generate
encoder32: encoder32to5 signal enc_din : std_logic_vector(ENC_SIZE-1 downto 0);
port map (din => grant_dirs(i)((e+1)*32-1 downto e*32), begin
dout => selectors(i+num_paths_out*(e+1)), set_enc_din: process(grant_dirs)
valid => valids(i+num_paths_out*(e+1))); begin
if e < NUM_ENCODERS-1 then
enc_din <= grant_dirs(i)(ENC_SIZE*(e+1)-1 downto ENC_SIZE*e);
else
enc_din(ENC_SIZE-1 downto NPI-ENC_SIZE*(NUM_ENCODERS-1)) <= (others => '0');
enc_din(NPI-(ENC_SIZE*(NUM_ENCODERS-1))-1 downto 0) <= grant_dirs(i)(NPI-1 downto ENC_SIZE*(NUM_ENCODERS-1));
end if;
end process;
encoder: encoder_generic
generic map (din_size => ENC_SIZE)
port map (din => enc_din, dout => selectors(i+NPO*e),
valid => valids(i+NPO*e));
end generate; end generate;
packet_index <= set_outputs: process(selectors, valids, packets, avai_paths)
to_integer(unsigned(selectors(i))) when valids(i) = '1' else variable packet_index : integer range 0 to NPI;
to_integer(unsigned(selectors(i+num_paths_out)))+32 variable valid_sel : std_logic;
when valids(i+num_paths_out) = '1' else begin
to_integer(unsigned(selectors(i+num_paths_out*2)))+64 packet_index := 0;
when valids(i+num_paths_out*2) = '1' else valid_sel := '0';
to_integer(unsigned(selectors(i+num_paths_out*3)))+96 for e in 0 to NUM_ENCODERS-1 loop
when valids(i+num_paths_out*3) = '1' else if valids(i+NPO*e) = '1' then
to_integer(unsigned(selectors(i+num_paths_out*4)))+128 packet_index := to_integer(unsigned(selectors(i+NPO*e)))+32*e;
when valids(i+num_paths_out*4) = '1' else valid_sel := '1';
to_integer(unsigned(selectors(i+num_paths_out*5)))+160 end if;
when valids(i+num_paths_out*5) = '1' else 0; end loop;
out_paths(i) <= packets(packet_index); out_paths(i) <= packets(packet_index);
valids_out(i) <= avai_paths(i) and (valids(i) or valids(i+num_paths_out) valids_out(i) <= avai_paths(i) and valid_sel;
or valids(i+num_paths_out*2) or valids(i+num_paths_out*3) end process;
or valids(i+num_paths_out*4) or valids(i+num_paths_out*5));
end generate; end generate;
set_updated_dirs: process(dirs, selectors, valids, avai_paths) set_updated_dirs: process(dirs, selectors, valids, avai_paths)
variable updated_dirs_index : integer range 0 to 192; variable updated_dirs_index : integer range 0 to NPI;
begin begin
updated_dirs <= dirs; updated_dirs <= dirs;
for i in 0 to num_paths_out-1 loop for i in 0 to num_paths_out-1 loop
if avai_paths(i) = '1' then for j in 0 to NUM_ENCODERS-1 loop
if valids(i) = '1' then if avai_paths(i) = '1' and valids(i+num_paths_out*j) = '1' then
updated_dirs_index := to_integer(unsigned(selectors(i))); updated_dirs_index := to_integer(unsigned(selectors(i+num_paths_out*j)));
updated_dirs(updated_dirs_index) <= '0'; updated_dirs(updated_dirs_index+32*j) <= '0';
elsif valids(i+num_paths_out) = '1' then
updated_dirs_index := to_integer(unsigned(selectors(i+num_paths_out)));
updated_dirs(updated_dirs_index+32) <= '0';
elsif valids(i+num_paths_out*2) = '1' then
updated_dirs_index := to_integer(unsigned(selectors(i+num_paths_out*2)));
updated_dirs(updated_dirs_index+64) <= '0';
elsif valids(i+num_paths_out*3) = '1' then
updated_dirs_index := to_integer(unsigned(selectors(i+num_paths_out*3)));
updated_dirs(updated_dirs_index+96) <= '0';
elsif valids(i+num_paths_out*4) = '1' then
updated_dirs_index := to_integer(unsigned(selectors(i+num_paths_out*4)));
updated_dirs(updated_dirs_index+128) <= '0';
elsif valids(i+num_paths_out*5) = '1' then
updated_dirs_index := to_integer(unsigned(selectors(i+num_paths_out*5)));
updated_dirs(updated_dirs_index+160) <= '0';
end if;
end if; end if;
end loop; end loop;
end process;
end generate;
g_L4_Encoders: if num_paths_in < 64 generate
constant MUX_SIZE : positive := 5;
type t_SELECTORS is array(natural range<>) of std_logic_vector(MUX_SIZE-1 downto 0);
signal selectors0 : t_SELECTORS(num_paths_out-1 downto 0);
signal selectors1 : t_SELECTORS(num_paths_out-1 downto 0);
signal valids0 : std_logic_vector(num_paths_out-1 downto 0);
signal valids1 : std_logic_vector(num_paths_out-1 downto 0);
begin
g_encoders: for i in 0 to num_paths_out-1 generate
type t_GRANT_DIRS32 is array(natural range<>) of std_logic_vector(31 downto 0);
signal grant_dirs0 : t_GRANT_DIRS32(num_paths_out-1 downto 0);
signal grant_dirs1 : t_GRANT_DIRS32(num_paths_out-1 downto 0);
signal packet_index : integer range 0 to num_paths_in;
begin
grant_dirs0(i) <= grant_dirs(i)(31 downto 0);
grant_dirs1(i)(num_paths_out-33 downto 0) <= grant_dirs(i)(num_paths_out-1 downto 32);
grant_dirs1(i)(31 downto num_paths_out-32) <= (others => '0');
encoder32_0: encoder32to5
port map (din => grant_dirs0(i), dout => selectors0(i),
valid => valids0(i));
encoder32_1: encoder32to5
port map (din => grant_dirs1(i), dout => selectors1(i),
valid => valids1(i));
packet_index <= to_integer(unsigned(selectors0(i)))
when valids0(i) = '1' else
to_integer(unsigned(selectors1(i)))+32
when valids1(i) = '1' else 0;
valids_out(i) <= valids0(i) or valids1(i);
out_paths(i) <= packets(packet_index);
end generate;
set_updated_dirs: process(dirs, selectors0, selectors1, valids0, valids1, avai_paths)
variable updated_dirs_index : integer range 0 to num_paths_in;
begin
updated_dirs <= dirs;
for i in 0 to num_paths_out-1 loop
if avai_paths(i) = '1' then
if valids0(i) = '1' then
updated_dirs_index := to_integer(unsigned(selectors0(i)));
updated_dirs(updated_dirs_index) <= '0';
elsif valids1(i) = '1' then
updated_dirs_index := to_integer(unsigned(selectors1(i)));
updated_dirs(updated_dirs_index+32) <= '0';
end if;
end if;
end loop; end loop;
end process; end process;
end generate;
g_L3_Encoders: if num_paths_in < 32 generate
constant PATH_MUX_SIZE : positive := 5;
type t_SELECTORS is array(natural range<>) of std_logic_vector(PATH_MUX_SIZE-1 downto 0);
signal selectors : t_SELECTORS(num_paths_out-1 downto 0);
begin
g_encoders: for i in 0 to num_paths_out-1 generate
signal packet_index : integer range 0 to num_paths_in;
begin
encoder32: encoder32to5
port map (din => grant_dirs(i), dout => selectors(i),
valid => valids_out(i));
packet_index <= to_integer(unsigned(selectors(i)));
out_paths(i) <= packets(packet_index) when avai_paths(i) = '1' else
(others => '0');
end generate;
set_updated_dirs: process(dirs, selectors, avai_paths, valids_out)
begin
updated_dirs <= dirs;
for i in 0 to num_paths_out-1 loop
if avai_paths(i) = '1' and valids_out(i) = '1' then
updated_dirs(to_integer(unsigned(selectors(i)))) <= '0';
end if;
end loop;
end process;
end generate;
g_L2_Encoders: if num_paths_in < 16 generate
constant PATH_MUX_SIZE : positive := 4;
type t_SELECTORS is array(natural range<>) of std_logic_vector(PATH_MUX_SIZE-1 downto 0);
signal selectors : t_SELECTORS(num_paths_out-1 downto 0);
begin
g_encoders: for i in 0 to num_paths_out-1 generate
signal packet_index : integer range 0 to num_paths_in;
begin
encoder16: encoder16to4
port map (din => grant_dirs(i), dout => selectors(i),
valid => valids_out(i));
packet_index <= to_integer(unsigned(selectors(i)));
out_paths(i) <= packets(packet_index) when avai_paths(i) = '1' else
(others => '0');
end generate;
set_updated_dirs: process(dirs, selectors, avai_paths, valids_out)
begin
updated_dirs <= dirs;
for i in 0 to num_paths_out-1 loop
if avai_paths(i) = '1' and valids_out(i) = '1' then
updated_dirs(to_integer(unsigned(selectors(i)))) <= '0';
end if;
end loop;
end process;
end generate;
g_L1_Encoders: if num_paths_in < 8 generate
constant PATH_MUX_SIZE : positive := 3;
type t_SELECTORS is array(natural range<>) of std_logic_vector(PATH_MUX_SIZE-1 downto 0);
signal selectors : t_SELECTORS(6*num_paths_out-1 downto 0);
begin
g_encoders: for i in 0 to num_paths_out-1 generate
signal packet_index : integer range 0 to num_paths_in;
begin
encoder8: encoder8to3
port map(din=>grant_dirs(i), dout=>selectors(i),valid=>valids_out(i));
packet_index <= to_integer(unsigned(selectors(i)))
when avai_paths(i) = '1' and valids_out(i) = '1' else 0;
out_paths(i) <= packets(packet_index);
end generate;
set_updated_dirs: process(dirs, selectors, avai_paths, valids_out)
begin
updated_dirs <= dirs;
for i in 0 to num_paths_out-1 loop
if avai_paths(i) = '1' and valids_out(i) = '1' then
updated_dirs(to_integer(unsigned(selectors(i)))) <= '0';
end if;
end loop;
end process;
end generate;
end rtl; end rtl;

6
arbiter/parent_arbiter.vhdl
View file

@ -6,7 +6,7 @@ use work.arbiter_functions.all;
entity parent_arbiter is entity parent_arbiter is
generic( generic(
level : positive := 5; level : natural := 5;
num_paths_up : positive := 32; num_paths_up : positive := 32;
num_paths_down : positive := 16; num_paths_down : positive := 16;
lsb_size_up : positive := 5; lsb_size_up : positive := 5;
@ -86,7 +86,7 @@ begin
port_dirs(i)(p) <= ps_dirs(p)(i); port_dirs(i)(p) <= ps_dirs(p)(i);
end generate; end generate;
ds_port_arbiter_unit: arbiter_unit ds_arbiter_unit: arbiter_unit
generic map( generic map(
num_paths_in => TOT_NUM_PATHS, num_paths_in => TOT_NUM_PATHS,
num_paths_out => num_paths_down, num_paths_out => num_paths_down,
@ -109,7 +109,7 @@ begin
port_dirs(i+NPOD)(p) <= ps_dirs(p)(i+NPOD); port_dirs(i+NPOD)(p) <= ps_dirs(p)(i+NPOD);
end generate; end generate;
u_port_arbiter_unit: arbiter_unit u_arbiter_unit: arbiter_unit
generic map( generic map(
num_paths_in => TOT_NUM_PATHS, num_paths_in => TOT_NUM_PATHS,
num_paths_out => num_paths_up, num_paths_out => num_paths_up,

34
encoders/encoder16to4.vhdl
View file

@ -16,39 +16,39 @@ begin
begin begin
valid <= '1'; valid <= '1';
if din(15) = '1' then if din(15) = '1' then
dout <= "01111"; dout <= "1111";
elsif din(14) = '1' then elsif din(14) = '1' then
dout <= "01110"; dout <= "1110";
elsif din(13) = '1' then elsif din(13) = '1' then
dout <= "01101"; dout <= "1101";
elsif din(12) = '1' then elsif din(12) = '1' then
dout <= "01100"; dout <= "1100";
elsif din(11) = '1' then elsif din(11) = '1' then
dout <= "01011"; dout <= "1011";
elsif din(10) = '1' then elsif din(10) = '1' then
dout <= "01010"; dout <= "1010";
elsif din(9) = '1' then elsif din(9) = '1' then
dout <= "01001"; dout <= "1001";
elsif din(8) = '1' then elsif din(8) = '1' then
dout <= "01000"; dout <= "1000";
elsif din(7) = '1' then elsif din(7) = '1' then
dout <= "00111"; dout <= "0111";
elsif din(6) = '1' then elsif din(6) = '1' then
dout <= "00110"; dout <= "0110";
elsif din(5) = '1' then elsif din(5) = '1' then
dout <= "00101"; dout <= "0101";
elsif din(4) = '1' then elsif din(4) = '1' then
dout <= "00100"; dout <= "0100";
elsif din(3) = '1' then elsif din(3) = '1' then
dout <= "00011"; dout <= "0011";
elsif din(2) = '1' then elsif din(2) = '1' then
dout <= "00010"; dout <= "0010";
elsif din(1) = '1' then elsif din(1) = '1' then
dout <= "00001"; dout <= "0001";
elsif din(0) = '1' then elsif din(0) = '1' then
dout <= "00000"; dout <= "0000";
else else
dout <= "00000"; dout <= "0000";
valid <= '0'; valid <= '0';
end if; end if;
end process; end process;

10
encoders/encoder4to2.vhdl
View file

@ -16,15 +16,15 @@ begin
begin begin
valid <= '1'; valid <= '1';
if din(3) = '1' then if din(3) = '1' then
dout <= "00011"; dout <= "11";
elsif din(2) = '1' then elsif din(2) = '1' then
dout <= "00010"; dout <= "10";
elsif din(1) = '1' then elsif din(1) = '1' then
dout <= "00001"; dout <= "01";
elsif din(0) = '1' then elsif din(0) = '1' then
dout <= "00000"; dout <= "00";
else else
dout <= "00000"; dout <= "00";
valid <= '0'; valid <= '0';
end if; end if;
end process; end process;

18
encoders/encoder8to3.vhdl
View file

@ -16,23 +16,23 @@ begin
begin begin
valid <= '1'; valid <= '1';
if din(7) = '1' then if din(7) = '1' then
dout <= "00111"; dout <= "111";
elsif din(6) = '1' then elsif din(6) = '1' then
dout <= "00110"; dout <= "110";
elsif din(5) = '1' then elsif din(5) = '1' then
dout <= "00101"; dout <= "101";
elsif din(4) = '1' then elsif din(4) = '1' then
dout <= "00100"; dout <= "100";
elsif din(3) = '1' then elsif din(3) = '1' then
dout <= "00011"; dout <= "011";
elsif din(2) = '1' then elsif din(2) = '1' then
dout <= "00010"; dout <= "010";
elsif din(1) = '1' then elsif din(1) = '1' then
dout <= "00001"; dout <= "001";
elsif din(0) = '1' then elsif din(0) = '1' then
dout <= "00000"; dout <= "000";
else else
dout <= "00000"; dout <= "000";
valid <= '0'; valid <= '0';
end if; end if;
end process; end process;

54
encoders/encoder_components.vhdl
View file

@ -3,6 +3,26 @@ use ieee.std_logic_1164.all;
use ieee.numeric_std.all; use ieee.numeric_std.all;
package encoder_components is package encoder_components is
function get_encoder_size(din_size: in natural)
return natural;
function get_dout_size(din_size: in natural)
return natural;
function get_num_encoders(num_paths_in: in integer)
return integer;
component encoder_generic is
generic(
din_size : natural
);
port (
din : in STD_LOGIC_VECTOR(din_size-1 downto 0);
dout : out STD_LOGIC_VECTOR(get_dout_size(din_size)-1 downto 0);
valid : out STD_LOGIC -- '1' if any input is high, '0' if all zero
);
end component encoder_generic;
component encoder4to2 is component encoder4to2 is
port ( port (
din : in STD_LOGIC_VECTOR(3 downto 0); din : in STD_LOGIC_VECTOR(3 downto 0);
@ -35,3 +55,37 @@ package encoder_components is
); );
end component encoder32to5; end component encoder32to5;
end package; end package;
package body encoder_components is
function get_encoder_size(din_size: in natural)
return natural is
begin
if din_size >= 16 then
return 32;
elsif din_size >= 8 then
return 16;
else
return 8;
end if;
end function;
function get_dout_size(din_size: in natural)
return natural is
begin
if din_size = 32 then
return 5;
elsif din_size = 16 then
return 4;
elsif din_size = 8 then
return 3;
else
return 0;
end if;
end function;
function get_num_encoders(num_paths_in: integer)
return integer is
begin
return (num_paths_in+32-1)/32;
end function;
end package body;

33
encoders/encoder_generic.vhdl Normal file
View file

@ -0,0 +1,33 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.encoder_components.all;
entity encoder_generic is
generic(
din_size : natural
);
port (
din : in STD_LOGIC_VECTOR(din_size-1 downto 0);
dout : out STD_LOGIC_VECTOR(get_dout_size(din_size)-1 downto 0);
valid : out STD_LOGIC -- '1' if any input is high, '0' if all zero
);
end encoder_generic;
architecture impl of encoder_generic is
begin
g_32_encoder: if din_size = 32 generate
encoder32: encoder32to5
port map (din => din, dout => dout, valid => valid);
end generate;
g_16_encoder: if din_size = 16 generate
encoder16: encoder16to4
port map (din => din, dout => dout, valid => valid);
end generate;
g_8_encoder: if din_size = 8 generate
encoder8: encoder8to3
port map (din => din, dout => dout, valid => valid);
end generate;
end impl;

6
noc/noc.vhdl
View file

@ -45,9 +45,9 @@ architecture impl of noc is
constant l5_core_y : std_logic_vector(4 downto 0) := "00000"; constant l5_core_y : std_logic_vector(4 downto 0) := "00000";
constant num_paths_up : positive := 32; constant num_paths_up : positive := 32;
constant num_paths_down : positive := 16; constant num_paths_down : positive := 16;
constant npu_bit_size : positive := 5; constant npu_bit_size : positive := 6;
constant npd_bit_size : positive := 4; constant npd_bit_size : positive := 5;
constant num_routers : positive := calculate_num_routers(top_level); constant num_routers : integer := calculate_num_routers(top_level);
signal r_data_ds_in : t_DATA(4*num_paths_down-1 downto 0); signal r_data_ds_in : t_DATA(4*num_paths_down-1 downto 0);
signal r_data_ds_out : t_DATA(4*num_paths_down-1 downto 0); signal r_data_ds_out : t_DATA(4*num_paths_down-1 downto 0);

4
noc/noc_conf.vhdl
View file

@ -11,7 +11,7 @@ package noc_conf is
num_paths_down : positive := 16; num_paths_down : positive := 16;
npu_bit_size : positive := 5; npu_bit_size : positive := 5;
npd_bit_size : positive := 4; npd_bit_size : positive := 4;
level : positive := 5; level : natural := 5;
buffer_width : positive := 64; buffer_width : positive := 64;
buffer_depth : positive := 4; buffer_depth : positive := 4;
fifo_ptr_size : positive := 3; fifo_ptr_size : positive := 3;
@ -43,7 +43,7 @@ package noc_conf is
buffer_width : positive := 64; buffer_width : positive := 64;
buffer_depth : positive := 4; buffer_depth : positive := 4;
fifo_ptr_size : positive := 3; fifo_ptr_size : positive := 3;
level : positive := 5; level : natural := 5;
top_level : positive := 5; top_level : positive := 5;
chip_x : std_logic_vector(4 downto 0) := "00000"; chip_x : std_logic_vector(4 downto 0) := "00000";
chip_y : std_logic_vector(4 downto 0) := "00000" chip_y : std_logic_vector(4 downto 0) := "00000"

8
noc/quadtree.vhdl
View file

@ -9,12 +9,12 @@ entity quadtree is
generic ( generic (
num_paths_up : positive := 32; num_paths_up : positive := 32;
num_paths_down : positive := 16; num_paths_down : positive := 16;
npu_bit_size : positive := 5; npu_bit_size : positive := 6;
npd_bit_size : positive := 4; npd_bit_size : positive := 5;
buffer_width : positive := 64; buffer_width : positive := 64;
buffer_depth : positive := 4; buffer_depth : positive := 4;
fifo_ptr_size : positive := 3; fifo_ptr_size : positive := 3;
level : positive := 5; level : natural := 5;
top_level : positive := 5; top_level : positive := 5;
chip_x : std_logic_vector(4 downto 0) := "00000"; chip_x : std_logic_vector(4 downto 0) := "00000";
chip_y : std_logic_vector(4 downto 0) := "00000" chip_y : std_logic_vector(4 downto 0) := "00000"
@ -46,7 +46,7 @@ port (
end quadtree; end quadtree;
architecture impl of quadtree is architecture impl of quadtree is
constant num_routers : positive := calculate_num_routers_qt(level, top_level); constant num_routers : natural := calculate_num_routers_qt(level, top_level);
signal r_core_x : std_logic_vector(19 downto 0); signal r_core_x : std_logic_vector(19 downto 0);
signal r_core_y : std_logic_vector(19 downto 0); signal r_core_y : std_logic_vector(19 downto 0);
begin begin

6
noc/quadtree_components.vhdl
View file

@ -8,9 +8,9 @@ package quadtree_components is
generic ( generic (
num_paths_up : positive := 1; num_paths_up : positive := 1;
num_paths_down : positive := 1; num_paths_down : positive := 1;
npu_bit_size : positive := 2; npu_bit_size : natural := 2;
npd_bit_size : positive := 1; npd_bit_size : natural := 1;
level : positive := 1; level : natural := 1;
buffer_width : positive := 64; buffer_width : positive := 64;
buffer_depth : positive := 4; buffer_depth : positive := 4;
fifo_ptr_size : positive := 3; fifo_ptr_size : positive := 3;

2
router/parent_router.vhdl
View file

@ -11,7 +11,7 @@ generic (
num_paths_down : positive := 16; num_paths_down : positive := 16;
npu_bit_size : positive := 5; npu_bit_size : positive := 5;
npd_bit_size : positive := 4; npd_bit_size : positive := 4;
level : positive := 5; level : natural := 5;
buffer_width : positive := 64; buffer_width : positive := 64;
buffer_depth : positive := 4; buffer_depth : positive := 4;
fifo_ptr_size : positive := 3; fifo_ptr_size : positive := 3;

2
router/router.vhdl
View file

@ -11,7 +11,7 @@ generic (
num_paths_down : positive := 1; num_paths_down : positive := 1;
npu_bit_size : positive := 2; npu_bit_size : positive := 2;
npd_bit_size : positive := 1; npd_bit_size : positive := 1;
level : positive := 1; level : natural := 1;
buffer_width : positive := 64; buffer_width : positive := 64;
buffer_depth : positive := 4; buffer_depth : positive := 4;
fifo_ptr_size : positive := 3; fifo_ptr_size : positive := 3;

4
router/router_components.vhdl
View file

@ -38,7 +38,7 @@ package router_components is
component arbiter is component arbiter is
generic( generic(
level : positive := 1; level : natural := 1;
num_paths_up : positive := 1; num_paths_up : positive := 1;
num_paths_down : positive := 1; num_paths_down : positive := 1;
lsb_size_up : positive := 2; lsb_size_up : positive := 2;
@ -62,7 +62,7 @@ package router_components is
component parent_arbiter is component parent_arbiter is
generic( generic(
level : positive := 5; level : natural := 5;
num_paths_up : positive := 32; num_paths_up : positive := 32;
num_paths_down : positive := 16; num_paths_down : positive := 16;
lsb_size_up : positive := 5; lsb_size_up : positive := 5;

2
synthesis/cmd/do_synth_all_routers.sh
View file

@ -2,4 +2,4 @@ LEVEL=1 NPU=2 NPD=1 CHIP_X=00001 CHIP_Y=00001 dc_shell -x "source cmd/do_synth_r
LEVEL=2 NPU=2 NPD=1 CHIP_X=00001 CHIP_Y=00001 dc_shell -x "source cmd/do_synth_router.tcl; quit" | tee -a log/synthesis_r2.log LEVEL=2 NPU=2 NPD=1 CHIP_X=00001 CHIP_Y=00001 dc_shell -x "source cmd/do_synth_router.tcl; quit" | tee -a log/synthesis_r2.log
LEVEL=3 NPU=2 NPD=1 CHIP_X=00001 CHIP_Y=00001 dc_shell -x "source cmd/do_synth_router.tcl; quit" | tee -a log/synthesis_r3.log LEVEL=3 NPU=2 NPD=1 CHIP_X=00001 CHIP_Y=00001 dc_shell -x "source cmd/do_synth_router.tcl; quit" | tee -a log/synthesis_r3.log
LEVEL=4 NPU=2 NPD=1 CHIP_X=00001 CHIP_Y=00001 dc_shell -x "source cmd/do_synth_router.tcl; quit" | tee -a log/synthesis_r4.log LEVEL=4 NPU=2 NPD=1 CHIP_X=00001 CHIP_Y=00001 dc_shell -x "source cmd/do_synth_router.tcl; quit" | tee -a log/synthesis_r4.log
LEVEL=5 NPU=2 NPD=1 CHIP_X=00001 CHIP_Y=00001 dc_shell -x "source cmd/do_synth_router.tcl; quit" | tee -a log/synthesis_r5.log LEVEL=5 NPU=2 NPD=1 CHIP_X=00001 CHIP_Y=00001 dc_shell -x "source cmd/do_synth_parent_router.tcl; quit" | tee -a log/synthesis_r5.log

21
synthesis/cmd/do_synth_arbiter.tcl
View file

@ -3,23 +3,24 @@ set npu [getenv NPU]
set npd [getenv NPD] set npd [getenv NPD]
analyze -library WORK -format vhdl {../router/router_types.vhdl} analyze -library WORK -format vhdl {../router/router_types.vhdl}
analyze -library WORK -format vhdl {../router/NthLsbDetector.vhdl} analyze -library WORK -format vhdl {../arbiter/NthLsbDetector.vhdl}
analyze -library WORK -format vhdl {../encoders/encoder_components.vhdl} analyze -library WORK -format vhdl {../encoders/encoder_components.vhdl}
analyze -library WORK -format vhdl {../encoders/encoder_generic.vhdl}
analyze -library WORK -format vhdl {../encoders/encoder8to3.vhdl} analyze -library WORK -format vhdl {../encoders/encoder8to3.vhdl}
analyze -library WORK -format vhdl {../encoders/encoder16to4.vhdl} analyze -library WORK -format vhdl {../encoders/encoder16to4.vhdl}
analyze -library WORK -format vhdl {../encoders/encoder32to5.vhdl} analyze -library WORK -format vhdl {../encoders/encoder32to5.vhdl}
analyze -library WORK -format vhdl {../router/arbiter_unit.vhdl} analyze -library WORK -format vhdl {../arbiter/arbiter_unit.vhdl}
analyze -library WORK -format vhdl {../router/routing_functions.vhdl} analyze -library WORK -format vhdl {../arbiter/arbiter_functions.vhdl}
analyze -library WORK -format vhdl {../router/arbiter.vhdl} analyze -library WORK -format vhdl {../arbiter/arbiter.vhdl}
elaborate arbiter -library WORK -parameters "level = $level, num_paths_up = $npu, num_paths_down = $npd" elaborate arbiter -library WORK -parameters "level = $level, num_paths_up = $npu, num_paths_down = $npd"
check_design check_design
check_timing check_timing
compile compile
report_area > reports/arbiter-$level-spl_synth.area report_area > reports/arbiter-$level-$npu-$npd-spl_synth.area
report_power > reports/arbiter-$level-spl_synth.power report_power > reports/arbiter-$level-$npu-$npd-spl_synth.power
change_names -hier -rules vhdl change_names -hier -rules vhdl
change_names -hier -rules verilog change_names -hier -rules verilog
write_file -hierarchy -f vhdl -output "./results/arbiter-$level.vhd" write_file -hierarchy -f vhdl -output "./results/arbiter-$level-$npu-$npd.vhd"
write_file -hierarchy -f verilog -output "./results/arbiter-$level.v" write_file -hierarchy -f verilog -output "./results/arbiter-$level-$npu-$npd.v"
write_sdf "./results/arbiter-$level.sdf" write_sdf "./results/arbiter-$level-$npu-$npd.sdf"
write -hierarchy -f ddc -output "./results/arbiter-$level.ddc" write -hierarchy -f ddc -output "./results/arbiter-$level-$npu-$npd.ddc"

11
synthesis/cmd/do_synth_noc.tcl
View file

@ -1,16 +1,17 @@
analyze -library WORK -format vhdl {../router/fifo.vhdl} analyze -library WORK -format vhdl {../router/fifo.vhdl}
analyze -library WORK -format vhdl {../router/router_types.vhdl} analyze -library WORK -format vhdl {../router/router_types.vhdl}
analyze -library WORK -format vhdl {../router/routing_functions.vhdl} analyze -library WORK -format vhdl {../arbiter/arbiter_functions.vhdl}
analyze -library WORK -format vhdl {../router/NthLsbDetector.vhdl} analyze -library WORK -format vhdl {../arbiter/NthLsbDetector.vhdl}
analyze -library WORK -format vhdl {../encoders/encoder_components.vhdl} analyze -library WORK -format vhdl {../encoders/encoder_components.vhdl}
analyze -library WORK -format vhdl {../encoders/encoder_generic.vhdl}
analyze -library WORK -format vhdl {../encoders/encoder8to3.vhdl} analyze -library WORK -format vhdl {../encoders/encoder8to3.vhdl}
analyze -library WORK -format vhdl {../encoders/encoder16to4.vhdl} analyze -library WORK -format vhdl {../encoders/encoder16to4.vhdl}
analyze -library WORK -format vhdl {../encoders/encoder32to5.vhdl} analyze -library WORK -format vhdl {../encoders/encoder32to5.vhdl}
analyze -library WORK -format vhdl {../router/arbiter_unit.vhdl} analyze -library WORK -format vhdl {../arbiter/arbiter_unit.vhdl}
analyze -library WORK -format vhdl {../router/receiver.vhdl} analyze -library WORK -format vhdl {../router/receiver.vhdl}
analyze -library WORK -format vhdl {../router/sender.vhdl} analyze -library WORK -format vhdl {../router/sender.vhdl}
analyze -library WORK -format vhdl {../router/arbiter.vhdl} analyze -library WORK -format vhdl {../arbiter/arbiter.vhdl}
analyze -library WORK -format vhdl {../router/parent_arbiter.vhdl} analyze -library WORK -format vhdl {../arbiter/parent_arbiter.vhdl}
analyze -library WORK -format vhdl {../router/router_components.vhdl} analyze -library WORK -format vhdl {../router/router_components.vhdl}
analyze -library WORK -format vhdl {../router/router.vhdl} analyze -library WORK -format vhdl {../router/router.vhdl}
analyze -library WORK -format vhdl {../router/parent_router.vhdl} analyze -library WORK -format vhdl {../router/parent_router.vhdl}

23
synthesis/cmd/do_synth_parent_arbiter.tcl
View file

@ -3,21 +3,24 @@ set npu [getenv NPU]
set npd [getenv NPD] set npd [getenv NPD]
analyze -library WORK -format vhdl {../router/router_types.vhdl} analyze -library WORK -format vhdl {../router/router_types.vhdl}
analyze -library WORK -format vhdl {../router/NthLsbDetector.vhdl} analyze -library WORK -format vhdl {../arbiter/NthLsbDetector.vhdl}
analyze -library WORK -format vhdl {../encoders/encoder_components.vhdl} analyze -library WORK -format vhdl {../encoders/encoder_components.vhdl}
analyze -library WORK -format vhdl {../encoders/encoder8to3.vhdl}
analyze -library WORK -format vhdl {../encoders/encoder16to4.vhdl}
analyze -library WORK -format vhdl {../encoders/encoder32to5.vhdl} analyze -library WORK -format vhdl {../encoders/encoder32to5.vhdl}
analyze -library WORK -format vhdl {../router/arbiter_unit.vhdl} analyze -library WORK -format vhdl {../encoders/encoder_generic.vhdl}
analyze -library WORK -format vhdl {../router/routing_functions.vhdl} analyze -library WORK -format vhdl {../arbiter/arbiter_unit.vhdl}
analyze -library WORK -format vhdl {../router/parent_arbiter.vhdl} analyze -library WORK -format vhdl {../arbiter/arbiter_functions.vhdl}
analyze -library WORK -format vhdl {../arbiter/parent_arbiter.vhdl}
elaborate parent_arbiter -library WORK -parameters "level = $level, num_paths_up = $npu, num_paths_down = $npd" elaborate parent_arbiter -library WORK -parameters "level = $level, num_paths_up = $npu, num_paths_down = $npd"
check_design check_design
check_timing check_timing
compile compile
report_area > reports/parent-arbiter-$level-spl_synth.area report_area > reports/parent-arbiter-$level-$npu-$npd-spl_synth.area
report_power > reports/parent-arbiter-$level-spl_synth.power report_power > reports/parent-arbiter-$level-$npu-$npd-spl_synth.power
change_names -hier -rules vhdl change_names -hier -rules vhdl
change_names -hier -rules verilog change_names -hier -rules verilog
write_file -hierarchy -f vhdl -output "./results/parent-arbiter-$level.vhd" write_file -hierarchy -f vhdl -output "./results/parent-arbiter-$level-$npu-$npd.vhd"
write_file -hierarchy -f verilog -output "./results/parent-arbiter-$level.v" write_file -hierarchy -f verilog -output "./results/parent-arbiter-$level-$npu-$npd.v"
write_sdf "./results/parent-arbiter-$level.sdf" write_sdf "./results/parent-arbiter-$level-$npu-$npd.sdf"
write -hierarchy -f ddc -output "./results/parent-arbiter-$level.ddc" write -hierarchy -f ddc -output "./results/parent-arbiter-$level-$npu-$npd.ddc"

52
synthesis/cmd/do_synth_parent_router.tcl Normal file
View file

@ -0,0 +1,52 @@
set level [getenv LEVEL]
set npu [getenv NPU]
set npd [getenv NPD]
set chip_x [getenv CHIP_X]
set chip_y [getenv CHIP_Y]
analyze -library WORK -format vhdl {../router/fifo.vhdl}
analyze -library WORK -format vhdl {../router/router_types.vhdl}
analyze -library WORK -format vhdl {../arbiter/NthLsbDetector.vhdl}
analyze -library WORK -format vhdl {../encoders/encoder_components.vhdl}
analyze -library WORK -format vhdl {../encoders/encoder8to3.vhdl}
analyze -library WORK -format vhdl {../encoders/encoder16to4.vhdl}
analyze -library WORK -format vhdl {../encoders/encoder32to5.vhdl}
analyze -library WORK -format vhdl {../encoders/encoder_generic.vhdl}
analyze -library WORK -format vhdl {../arbiter/arbiter_unit.vhdl}
analyze -library WORK -format vhdl {../arbiter/arbiter_functions.vhdl}
analyze -library WORK -format vhdl {../router/receiver.vhdl}
analyze -library WORK -format vhdl {../router/sender.vhdl}
analyze -library WORK -format vhdl {../arbiter/parent_arbiter.vhdl}
read_ddc ./results/parent-arbiter-$level-$npu-$npd.ddc
analyze -library WORK -format vhdl {../router/router_components.vhdl}
analyze -library WORK -format vhdl {../router/parent_router.vhdl}
elaborate router -library WORK -parameters "level = $level, num_paths_up = $npu, num_paths_down = $npd, buffer_width = 64, buffer_depth = 4, fifo_ptr_size = 3, chip_x = $chip_x, chip_y = $chip_y"
check_design
create_clock [get_ports clk] -period 8.0 -waveform {0 4} -name clk
set_clock_uncertainty 0.025 -setup [get_clocks clk]
set_clock_uncertainty 0.025 -hold [get_clocks clk]
set_clock_transition -fall 0.04 [get_clocks clk]
set_clock_transition -rise 0.04 [get_clocks clk]
set_dont_touch clk
set_dont_touch arstN
set_clock_latency -max -source 0.1 [get_clocks clk]
set_input_delay -max -clock clk 0.05 [get_ports {core_x core_y data_in rcv_reqs send_ack rcv_acks send_reqs data_out}]
set_output_delay -max -clock clk 0.05 [all_outputs]
set_false_path -from [get_ports arstN]
check_timing
compile
report_area > reports/parent-router-$level-$npu-$npd-spl_synth.area
report_power > reports/parent-router-$level-$npu-$npd-spl_synth.power
change_names -hier -rules vhdl
change_names -hier -rules verilog
write_file -hierarchy -f vhdl -output "./results/parent-router-$level-$npu-$npd.vhd"
write_file -hierarchy -f verilog -output "./results/parent-router-$level-$npu-$npd.v"
write_sdf "./results/parent-router-$level-$npu-$npd.sdf"
write -hierarchy -f ddc -output "./results/parent-router-$level-$npu-$npd.ddc"

14
synthesis/cmd/do_synth_router.tcl
View file

@ -16,7 +16,7 @@ analyze -library WORK -format vhdl {../router/routing_functions.vhdl}
analyze -library WORK -format vhdl {../router/receiver.vhdl} analyze -library WORK -format vhdl {../router/receiver.vhdl}
analyze -library WORK -format vhdl {../router/sender.vhdl} analyze -library WORK -format vhdl {../router/sender.vhdl}
analyze -library WORK -format vhdl {../router/arbiter.vhdl} analyze -library WORK -format vhdl {../router/arbiter.vhdl}
read_ddc ./results/arbiter-$level.ddc read_ddc ./results/arbiter-$level-$npu-$npd.ddc
analyze -library WORK -format vhdl {../router/router_components.vhdl} analyze -library WORK -format vhdl {../router/router_components.vhdl}
analyze -library WORK -format vhdl {../router/router.vhdl} analyze -library WORK -format vhdl {../router/router.vhdl}
elaborate router -library WORK -parameters "level = $level, num_paths_up = $npu, num_paths_down = $npd, buffer_width = 64, buffer_depth = 4, fifo_ptr_size = 3, chip_x = $chip_x, chip_y = $chip_y" elaborate router -library WORK -parameters "level = $level, num_paths_up = $npu, num_paths_down = $npd, buffer_width = 64, buffer_depth = 4, fifo_ptr_size = 3, chip_x = $chip_x, chip_y = $chip_y"
@ -41,11 +41,11 @@ set_false_path -from [get_ports arstN]
check_timing check_timing
compile compile
report_area > reports/arbiter-$level-spl_synth.area report_area > reports/router-$level-$npu-$npd-spl_synth.area
report_power > reports/arbiter-$level-spl_synth.power report_power > reports/router-$level-$npu-$npd-spl_synth.power
change_names -hier -rules vhdl change_names -hier -rules vhdl
change_names -hier -rules verilog change_names -hier -rules verilog
write_file -hierarchy -f vhdl -output "./results/arbiter-$level.vhd" write_file -hierarchy -f vhdl -output "./results/router-$level-$npu-$npd.vhd"
write_file -hierarchy -f verilog -output "./results/arbiter-$level.v" write_file -hierarchy -f verilog -output "./results/router-$level-$npu-$npd.v"
write_sdf "./results/arbiter-$level.sdf" write_sdf "./results/router-$level-$npu-$npd.sdf"
write -hierarchy -f ddc -output "./results/arbiter-$level.ddc" write -hierarchy -f ddc -output "./results/router-$level-$npu-$npd.ddc"

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test/noc_tb.vhdl
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@ -19,7 +19,7 @@ architecture bench of noc_tb is
constant buffer_width : integer := 64; constant buffer_width : integer := 64;
constant buffer_depth : integer := 4; constant buffer_depth : integer := 4;
constant fifo_ptr_size : integer := 3; constant fifo_ptr_size : integer := 3;
constant level : integer := 5; constant level : natural := 5;
constant top_level : integer := 5; constant top_level : integer := 5;
constant chip_x : std_logic_vector(4 downto 0) := "00001"; constant chip_x : std_logic_vector(4 downto 0) := "00001";
constant chip_y : std_logic_vector(4 downto 0) := "00001"; constant chip_y : std_logic_vector(4 downto 0) := "00001";

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