library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.encoder_components.all;

entity encoder_generic is
    generic(
        din_size    :   natural
    );
    port (
        din   : in STD_LOGIC_VECTOR(din_size-1 downto 0);
        dout  : out STD_LOGIC_VECTOR(get_dout_size(din_size)-1 downto 0);
        valid : out STD_LOGIC   -- '1' if any input is high, '0' if all zero
    );
end encoder_generic;

architecture impl of encoder_generic is
begin
    g_32_encoder: if din_size = 32 generate
        encoder32: encoder32to5
        port map (din => din, dout => dout, valid => valid);
    end generate;

    g_16_encoder: if din_size = 16 generate
        encoder16: encoder16to4
        port map (din => din, dout => dout, valid => valid);
    end generate;

    g_8_encoder: if din_size = 8 generate
        encoder8: encoder8to3
        port map (din => din, dout => dout, valid => valid);
    end generate;
end impl;