library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use work.router_types.all;
use work.quadtree_components.all;
use work.noc_conf.all;

entity noc is
generic ( 
    num_paths_ext     :   positive := 32;
    buffer_width      :   positive := 64;
    buffer_depth      :   positive := 4;
    fifo_ptr_size     :   positive := 3;
    level             :   positive := 5;
    top_level         :   positive := 5;
    chip_x            :   std_logic_vector(4 downto 0) := "00000";
    chip_y            :   std_logic_vector(4 downto 0) := "00000"
);
port (
    clks                : in std_logic_vector(
                            calculate_num_routers(top_level)-1 downto 0);
    arstN               : in std_logic;

    data_chip_in        : in t_DATA_EXT(4*num_paths_ext-1 downto 0);
    c_rcv_reqs          : in std_logic_vector(4*num_paths_ext-1 downto 0);
    c_send_ack          : in std_logic_vector(4*num_paths_ext-1 downto 0);

    pe_data_in          : in t_DATA(4**level-1 downto 0);
    pe_rcv_reqs         : in std_logic_vector(4**level-1 downto 0);
    pe_send_ack         : in std_logic_vector(4**level-1 downto 0);

    data_chip_out       : out t_DATA_EXT(4*num_paths_ext-1 downto 0);
    c_rcv_ack           : out std_logic_vector(4*num_paths_ext-1 downto 0);
    c_send_reqs         : out std_logic_vector(4*num_paths_ext-1 downto 0);

    pe_data_out         : out t_DATA(4**level-1 downto 0);
    pe_rcv_acks         : out std_logic_vector(4**level-1 downto 0);
    pe_send_reqs        : out std_logic_vector(4**level-1 downto 0)
);
end noc;

architecture impl of noc is
    constant l5_core_x       :   std_logic_vector(4 downto 0) := "00000";
    constant l5_core_y       :   std_logic_vector(4 downto 0) := "00000";
    constant num_paths_up    :   positive := 32;
    constant num_paths_down  :   positive := 16;
    constant npu_bit_size    :   positive := 6;
    constant npd_bit_size    :   positive := 5;
    constant num_routers     :   integer := calculate_num_routers(top_level);

    signal r_data_ds_in      :   t_DATA(4*num_paths_down-1 downto 0);
    signal r_data_ds_out     :   t_DATA(4*num_paths_down-1 downto 0);
    
    signal r_rcv_reqs        :   std_logic_vector(4*num_paths_up+4*num_paths_down-1 downto 0);
    signal r_rcv_reqs_ds     :   std_logic_vector(4*num_paths_down-1 downto 0);
    
    signal r_snd_ack         :   std_logic_vector(4*num_paths_up+4*num_paths_down-1 downto 0);
    signal r_snd_ack_ds      :   std_logic_vector(4*num_paths_down-1 downto 0);
    
    signal r_snd_reqs        :   std_logic_vector(4*num_paths_up+4*num_paths_down-1 downto 0);
    signal r_snd_reqs_ds     :   std_logic_vector(4*num_paths_down-1 downto 0);
    
    signal r_rcv_ack         :   std_logic_vector(4*num_paths_up+4*num_paths_down-1 downto 0);
    signal r_rcv_ack_ds      :   std_logic_vector(4*num_paths_down-1 downto 0);

    signal s_data_chip_out   :   t_DATA_EXT(4*num_paths_ext-1 downto 0);
    signal s_c_rcv_ack       :   std_logic_vector(4*num_paths_ext-1 downto 0);
    signal s_c_send_reqs     :   std_logic_vector(4*num_paths_ext-1 downto 0);
begin
    r_rcv_reqs <= c_rcv_reqs & r_rcv_reqs_ds;
    r_snd_ack  <= c_send_ack  & r_snd_ack_ds;
    
    s_c_send_reqs <= r_snd_reqs(4*num_paths_up+4*num_paths_down-1 downto 4*num_paths_down);
    r_snd_reqs_ds <= r_snd_reqs(4*num_paths_down-1 downto 0);
    s_c_rcv_ack   <= r_rcv_ack(4*num_paths_up+4*num_paths_down-1 downto 4*num_paths_down);
    r_rcv_ack_ds  <= r_rcv_ack(4*num_paths_down-1 downto 0);
 
    c_send_reqs    <= s_c_send_reqs;
    c_rcv_ack      <= s_c_rcv_ack;
    data_chip_out  <= s_data_chip_out;

    router_l5:  parent_router
    generic map(num_paths_up => num_paths_up, num_paths_down => num_paths_down, 
        npu_bit_size => npu_bit_size, npd_bit_size => npd_bit_size,
        level => level, buffer_width => buffer_width, buffer_depth => buffer_depth, 
        fifo_ptr_size => fifo_ptr_size, chip_x => chip_x, chip_y => chip_y)
    port map(clk => clks(num_routers-1), arstN => arstN, core_x => l5_core_x, core_y => l5_core_y,
        data_in_ds => r_data_ds_in, data_in_us => data_chip_in, 
        rcv_reqs => r_rcv_reqs, send_ack => r_snd_ack, rcv_acks => r_rcv_ack, 
        send_reqs => r_snd_reqs, data_out_ds => r_data_ds_out, 
        data_out_us => s_data_chip_out);

    quadtree_inst: quadtree
        generic map(num_paths_up => num_paths_up, num_paths_down => num_paths_down,
            npu_bit_size => npu_bit_size, npd_bit_size => npd_bit_size, 
            level => level, top_level => top_level,
            buffer_width => buffer_width, buffer_depth => buffer_depth, 
            fifo_ptr_size => fifo_ptr_size, chip_x => chip_x, chip_y => chip_y)
        port map(clks => clks(num_routers-2 downto 0), 
            arstN => arstN, core_x => l5_core_x, 
            core_y => l5_core_y, data_in_us => r_data_ds_out,
            rcv_reqs_us => r_snd_reqs_ds, send_ack_us => r_rcv_ack_ds,
            pe_data_in  => pe_data_in, pe_rcv_reqs => pe_rcv_reqs,
            pe_send_ack => pe_send_ack, data_out_us => r_data_ds_in, 
            rcv_acks_us => r_snd_ack_ds, send_reqs_us => r_rcv_reqs_ds,
            pe_rcv_acks => pe_rcv_acks, pe_send_reqs => pe_send_reqs,
            pe_data_out => pe_data_out);
end impl;