library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.router_types.all;
use work.quadtree_components.all;

package noc_conf is
    component parent_router is
    generic ( 
        num_paths_up      :   positive := 32;
        num_paths_down    :   positive := 16;
        npu_bit_size      :   positive := 5;
        npd_bit_size      :   positive := 4;
        level             :   natural := 5;
        buffer_width      :   positive := 64;
        buffer_depth      :   positive := 4;
        fifo_ptr_size     :   positive := 3;
        chip_x            :   std_logic_vector(4 downto 0);
        chip_y            :   std_logic_vector(4 downto 0)
    );
    port (
        clk            : in std_logic;
        arstN          : in std_logic;
        core_x         : in std_logic_vector(4 downto 0);
        core_y         : in std_logic_vector(4 downto 0);
        data_in_ds     : in t_DATA(num_paths_down*4-1 downto 0);
        data_in_us     : in t_DATA_EXT(num_paths_up*4-1 downto 0);
        rcv_reqs       : in std_logic_vector(num_paths_up*4+num_paths_down*4-1 downto 0);
        send_ack       : in std_logic_vector(num_paths_up*4+num_paths_down*4-1 downto 0);
        rcv_acks       : out std_logic_vector(num_paths_up*4+num_paths_down*4-1 downto 0);
        send_reqs      : out std_logic_vector(num_paths_up*4+num_paths_down*4-1 downto 0);
        data_out_ds    : out t_DATA(num_paths_down*4-1 downto 0);
        data_out_us    : out t_DATA_EXT(num_paths_up*4-1 downto 0)
    );
    end component parent_router;

    component quadtree is
    generic (
        num_paths_up      :   positive := 32;
        num_paths_down    :   positive := 16;
        npu_bit_size      :   positive := 5;
        npd_bit_size      :   positive := 4;
        buffer_width      :   positive := 64;
        buffer_depth      :   positive := 4;
        fifo_ptr_size     :   positive := 3;
        level             :   natural := 5;
        top_level         :   positive := 5;
        chip_x            :   std_logic_vector(4 downto 0) := "00000";
        chip_y            :   std_logic_vector(4 downto 0) := "00000"
    );
    port (
        clks              : in std_logic_vector(
                        calculate_num_routers_qt(level, top_level)-1 downto 0);
        arstN             : in std_logic;

        core_x            : in std_logic_vector(4 downto 0);
        core_y            : in std_logic_vector(4 downto 0);
        
        data_in_us        : in t_DATA(4*num_paths_up/2-1 downto 0);
        rcv_reqs_us       : in std_logic_vector(4*num_paths_up/2-1 downto 0);
        send_ack_us       : in std_logic_vector(4*num_paths_up/2-1 downto 0);
        
        pe_data_in        : in t_DATA(4**level-1 downto 0);
        pe_rcv_reqs       : in std_logic_vector(4**level-1 downto 0);
        pe_send_ack       : in std_logic_vector(4**level-1 downto 0);
        
        data_out_us       : out t_DATA(4*num_paths_up/2-1 downto 0);
        rcv_acks_us       : out std_logic_vector(4*num_paths_up/2-1 downto 0);
        send_reqs_us      : out std_logic_vector(4*num_paths_up/2-1 downto 0);
        
        pe_rcv_acks       : out std_logic_vector(4**level-1 downto 0);
        pe_send_reqs      : out std_logic_vector(4**level-1 downto 0);
        pe_data_out       : out t_DATA(4**level-1 downto 0)
    );
    end component;
end package;