library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity Receiver is
port (
    clk, req, arstN, accept_ack      : in std_logic;
    data                             : in std_logic_vector(63 downto 0);
    req_flag, ack                    : out std_logic;
    data_out                         : out std_logic_vector(63 downto 0)
);
end Receiver;

architecture impl of Receiver is
    signal req1, req2, req3                     :  std_logic;
    signal req_edge, upd_ack                    :  std_logic;
    signal ack_nxt, sgn_ack                     :  std_logic;
    signal req_flag1, req_flag2, req_flag3      :  std_logic;
    signal data_nxt, sgn_data                   :  std_logic_vector(63 downto 0);  
begin
    req_edge  <= req2 xor req3;
    upd_ack   <= accept_ack and req_flag2;
    req_flag1 <= '1' when req_edge = '1' else '0' 
                     when upd_ack = '1' else req_flag2; 
    ack_nxt   <= not sgn_ack when (upd_ack) = '1' else sgn_ack;
    
    req_flag  <= req_flag3 and (not req_flag2);
    data_nxt  <= data when req_edge = '1' else sgn_data;
    ack       <= sgn_ack;
    data_out  <= sgn_data;

    update_regs: process(clk)
    begin
        if arstN = '0' then
            sgn_ack  <= '0';
            sgn_data <= (others => '0');
        elsif rising_edge(clk) then
            req1        <= req;
            req2        <= req1;
            req3        <= req2;
            req_flag2   <= req_flag1;
            req_flag3   <= req_flag2;
            sgn_ack     <= ack_nxt;
            sgn_data    <= data_nxt;
        end if;
    end process;
end impl;