library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.router_types.all;

package router_components is
    component fifo is
        generic (
            WIDTH       : positive;
            DEPTH       : positive;
            F_PTR_SIZE  : positive
        );
        port(   
            arstN, clk, wr_req, rd_req  : in std_logic;
            full, empty                 : out std_logic;
            data_in  : in std_logic_vector(WIDTH-1 downto 0);
            data_out : out std_logic_vector(WIDTH-1 downto 0)
        );
    end component fifo;

    component Sender is
    port (
        clk, continue_send, ack, arstN      : in std_logic;
        data_in                             : in std_logic_vector(63 downto 0);
        req, rd_req                         : out std_logic;
        data                                : out std_logic_vector(63 downto 0)
    );
    end component Sender;

    component Receiver is
    port (
        clk, req, arstN, accept_ack      : in std_logic;
        data                             : in std_logic_vector(63 downto 0);
        req_flag, ack                    : out std_logic;
        data_out                         : out std_logic_vector(63 downto 0)
    );
    end component Receiver;

    component arbiter is
        generic(
            level               :   natural := 1;
            num_paths_up        :   positive := 1;
            num_paths_down      :   positive := 1;
            lsb_size_up         :   positive := 2;
            lsb_size_down       :   positive := 1
        );
        port (
            clk, arstN        : in std_logic;
            chip_pos          : in t_chip_addr;
            core_pos          : in t_core_addr;
            packets           : in t_DATA(num_paths_up+num_paths_down*4-1 downto 0);
            valid_data        : in std_logic_vector(
                                    num_paths_up+num_paths_down*4-1 downto 0);
            avai_paths        : in std_logic_vector(
                                    num_paths_up+num_paths_down*4-1 downto 0);
            arb_complete      : out std_logic_vector(
                                    num_paths_up+num_paths_down*4-1 downto 0);
            buff_wr_in        : out t_FIFO_WR_INS(
                                    num_paths_up+num_paths_down*4-1 downto 0)
        );
    end component arbiter;

    component parent_arbiter is
    generic(
        level               :   natural := 5;
        num_paths_up        :   positive := 32;
        num_paths_down      :   positive := 16;
        lsb_size_up         :   positive := 5;
        lsb_size_down       :   positive := 4
    );
    port (
        clk, arstN      : in std_logic;
        chip_pos        : in t_chip_addr;
        core_pos        : in t_core_addr;
        packets         : in t_DATA(num_paths_up*4+num_paths_down*4-1 downto 0);
        valid_data      : in std_logic_vector(num_paths_up*4+num_paths_down*4-1 downto 0);
        avai_paths      : in std_logic_vector(num_paths_up*4+num_paths_down*4-1 downto 0);
        arb_complete    : out std_logic_vector(num_paths_up*4+num_paths_down*4-1 downto 0);
        buff_wr_in      : out t_FIFO_WR_INS(num_paths_up*4+num_paths_down*4-1 downto 0)
    );
    end component parent_arbiter;
end package;