library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity Sender is
port (
    clk, continue_send, ack, arstN      : in std_logic;
    data_in                             : in std_logic_vector(63 downto 0);
    req, rd_req                         : out std_logic;
    data                                : out std_logic_vector(63 downto 0)
);
end Sender;

architecture impl of Sender is
    signal ack1, ack2, ack3, req_nxt        :  std_logic;
    signal upd_req, upd_req_nxt             :  std_logic;
    signal sgn_req                          :  std_logic;
    signal ack_edge, data_nxt_mux           :  std_logic;
    signal data_nxt, sgn_data               :  std_logic_vector(63 downto 0);  
begin
    upd_req_nxt  <= '0' when data_nxt_mux  = '1'  else '1' 
                        when ack_edge = '1'  else upd_req;
    data_nxt_mux <= '1' when upd_req = '1' and continue_send = '1' else '0';
    req_nxt      <= not sgn_req when data_nxt_mux = '1' else sgn_req;
    rd_req       <= ack_edge; -- means that the data has been received
    ack_edge     <= ack2 xor ack3;
    data_nxt     <= data_in when data_nxt_mux = '1' else sgn_data;
    req          <= sgn_req;
    data         <= sgn_data;

    update_regs: process(clk)
    begin
        if arstN = '0' then
            sgn_req  <= '0';
            upd_req  <= '1';
            sgn_data <= (others => '0');
        elsif rising_edge(clk) then
            ack1     <= ack;
            ack2     <= ack1;
            ack3     <= ack2;
            upd_req  <= upd_req_nxt;
            sgn_req  <= req_nxt;
            sgn_data <= data_nxt;
        end if;
    end process;
end impl;