library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity fifo_tb is
end;

architecture bench of fifo_tb is
  -- Clock period
  constant clk_period : time := 5 ns;
  -- Generics
  constant WIDTH : integer := 32;
  constant DEPTH : integer := 8;
  constant F_PTR_SIZE : integer := 4;
  -- Ports
  signal arstN : std_logic;
  signal clk : std_logic;
  signal wr_req : std_logic;
  signal rd_req : std_logic;
  signal full : std_logic;
  signal empty : std_logic;
  signal data_in : std_logic_vector(WIDTH-1 downto 0);
  signal data_out : std_logic_vector(WIDTH-1 downto 0);
begin

  fifo_inst : entity work.fifo
  generic map (
    WIDTH => WIDTH,
    DEPTH => DEPTH,
    F_PTR_SIZE => F_PTR_SIZE
  )
  port map (
    arstN => arstN,
    clk => clk,
    wr_req => wr_req,
    rd_req => rd_req,
    full => full,
    empty => empty,
    data_in => data_in,
    data_out => data_out
  );

  clock_gen: process
  begin
      clk <= '0';
      wait for clk_period/2;
      clk <= '1';
      wait for clk_period/2;
  end process;

  test: process
  begin
    arstN <= '0';
    wait for CLK_PERIOD;
    arstN <= '1';

    for value_sent in 10 downto 0 loop
        wr_req <= '1';
        data_in <= std_logic_vector(to_unsigned(value_sent, data_in'length));
        wait for clk_period;
        wr_req <= '0';
        wait for clk_period;
    end loop;

    for counter in 0 to 10 loop
        rd_req <= '1';
        wait for clk_period;
        --rd_req <= '0';
        --wait for clk_period;
    end loop;
    wait;
  end process;
end;