library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.router_types.all;
use ieee.std_logic_textio.all;
use std.textio.all;

entity router_tb is
end;

architecture bench of router_tb is
  -- Clock period
  constant clk_period : time := 5 ns;
  -- Generics
  constant num_paths_up : integer := 32;
  constant num_paths_down : integer := 16;
  constant level : integer := 5;
  constant buffer_width : integer := 64;
  constant buffer_depth : integer := 4;
  constant fifo_ptr_size : integer := 3;
  constant chip_x : std_logic_vector(4 downto 0) := (others => '0');
  constant chip_y : std_logic_vector(4 downto 0) := (others => '0');
  constant core_x : std_logic_vector(4 downto 0) := "-----";
  constant core_y : std_logic_vector(4 downto 0) := "-----";
  -- Ports
  signal clk : std_logic;
  signal arstN : std_logic;
  signal data_in : t_DATA(num_paths_up+num_paths_down*4-1 downto 0);
  signal rcv_reqs : std_logic_vector(num_paths_up+num_paths_down*4-1 downto 0);
  signal send_ack : std_logic_vector(num_paths_up+num_paths_down*4-1 downto 0);
  signal rcv_acks : std_logic_vector(num_paths_up+num_paths_down*4-1 downto 0);
  signal send_reqs : std_logic_vector(num_paths_up+num_paths_down*4-1 downto 0);
  signal data_out : t_DATA(num_paths_up+num_paths_down*4-1 downto 0);

  signal gen_data : t_DATA(num_paths_up+num_paths_down*4-1 downto 0);
  signal rcv_data : t_DATA(num_paths_up+num_paths_down*4-1 downto 0);
  signal req_flag : std_logic_vector(num_paths_up+num_paths_down*4-1 downto 0);
  signal rd_req_flag : std_logic_vector(num_paths_up+num_paths_down*4-1 downto 0);
  signal continue_send : std_logic_vector(num_paths_up+num_paths_down*4-1 downto 0);

  file conf_file            : text open read_mode is "config.txt";
  file stimuli_file         : text open read_mode is "stimuli.txt";
  file reference_file       : text open read_mode is "result.ref";
  file log_file             : text open write_mode is "simulation.log";
begin

  router_inst : entity work.router
  generic map (
    num_paths_up => num_paths_up,
    num_paths_down => num_paths_down,
    level => level,
    buffer_width => buffer_width,
    buffer_depth => buffer_depth,
    fifo_ptr_size => fifo_ptr_size,
    chip_x => chip_x,
    chip_y => chip_y
  )
  port map (
    clk => clk,
    arstN => arstN,
    core_x => core_x,
    core_y => core_y,
    data_in => data_in,
    rcv_reqs => rcv_reqs,
    send_ack => send_ack,
    rcv_acks => rcv_acks,
    send_reqs => send_reqs,
    data_out => data_out
  );

  g_SENDER_GEN: for i in 0 to num_paths_up+num_paths_down*4-1 generate
      sender_inst: entity work.sender
      port map(clk => clk, arstN => arstN,
              continue_send => continue_send(i),
              ack  => rcv_acks(i), data_in => gen_data(i),
              req  => rcv_reqs(i), rd_req => rd_req_flag(i),
              data => data_in(i));
  end generate;

  g_RECEIVER_GEN: for i in 0 to num_paths_up+num_paths_down*4-1 generate
    receiver_inst: entity work.Receiver
    port map(
      clk => clk, req => send_reqs(i), arstN => arstN, accept_ack => '1',
      data => data_out(i), req_flag => req_flag(i), ack => send_ack(i), 
      data_out => rcv_data(i)
    );
  end generate;

  clock_gen: process
  begin
      clk <= '0';
      wait for clk_period/2;
      clk <= '1';
      wait for clk_period/2;
  end process;

  gen_stimuli: process
    variable input_line, rowOut : line;
    variable valid_data         : boolean;
    variable stimuli            : std_logic_vector(64 downto 0);
    variable index_path         : integer;
  begin
    wait until rising_edge(clk);
    arstN <= '0';
    gen_data <= (others => (others => '0'));
    wait until rising_edge(clk);
    arstN <= '1';
    wait until rising_edge(clk);
    wait until rising_edge(clk);
    index_path := 0;
    while not(endfile(stimuli_file)) loop
      readline(stimuli_file, input_line);
      read(input_line, stimuli, valid_data);
      assert valid_data
      report "Invalid data in file" severity error;
      gen_data(index_path) <= stimuli(63 downto 0);
      continue_send(index_path) <= stimuli(64);
      index_path := index_path + 1;
      if index_path = num_paths_down*4 + num_paths_up then
        wait on rd_req_flag until rd_req_flag = 
            std_logic_vector(to_unsigned(0, num_paths_up+num_paths_down*4));
        wait on rd_req_flag;
        index_path := 0;
      end if;
      exit when endfile(stimuli_file);
    end loop;
    wait;
  end process;

  validate_routed_data: process(req_flag, rcv_data)
    variable input_line, rowOut : line;
    variable valid_data         : boolean;
    variable istwert, sollwert  : WORD;
    --variable test_passed        : boolean;
  begin
    for i in 0 to num_paths_down*4+num_paths_up-1 loop
      if req_flag(i) = '1' then
        istwert := rcv_data(i);
        readline(reference_file, input_line);
        read(input_line, sollwert, valid_data);
        assert valid_data report "Invalid data in file" severity error;
        assert istwert = sollwert report "Invalid result" severity warning;
        write(rowOut, i);
        write(rowOut, string'(" = loop (path/fifo)"));
        WRITELINE(log_file, rowOut);
        write(rowOut, sollwert);
        write(rowOut, string'(" = soll"));
        WRITELINE(log_file, rowOut);
        write(rowOut, istwert);
        write(rowOut, string'(" = ist"));
        WRITELINE(log_file, rowOut);
        if istwert = sollwert then
          write(rowOut, string'("-------------------------->pass"));
          WRITELINE(log_file, rowOut);
          write(rowOut, string'("******************************"));
          WRITELINE(log_file, rowOut);
          --test_passed := test_passed and TRUE;
        else
          write(rowOut, string'("-------------------------->fail"));
          WRITELINE(log_file, rowOut);
          write(rowOut, string'("******************************"));
          WRITELINE(log_file, rowOut);
          --test_passed := test_passed and FALSE;
        end if;
      end if;
    end loop;
  end process;
end;