87 lines
No EOL
2.4 KiB
VHDL
87 lines
No EOL
2.4 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity encoder32to5 is
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port (
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din : in STD_LOGIC_VECTOR(31 downto 0);
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dout : out STD_LOGIC_VECTOR(4 downto 0);
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valid : out STD_LOGIC -- '1' if any input is high, '0' if all zero
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);
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end encoder32to5;
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architecture impl of encoder32to5 is
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begin
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process(din)
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begin
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valid <= '1';
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if din(31) = '1' then
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dout <= "11111";
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elsif din(30) = '1' then
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dout <= "11110";
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elsif din(29) = '1' then
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dout <= "11101";
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elsif din(28) = '1' then
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dout <= "11100";
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elsif din(27) = '1' then
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dout <= "11011";
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elsif din(26) = '1' then
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dout <= "11010";
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elsif din(25) = '1' then
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dout <= "11001";
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elsif din(24) = '1' then
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dout <= "11000";
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elsif din(23) = '1' then
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dout <= "10111";
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elsif din(22) = '1' then
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dout <= "10110";
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elsif din(21) = '1' then
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dout <= "10101";
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elsif din(20) = '1' then
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dout <= "10100";
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elsif din(19) = '1' then
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dout <= "10011";
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elsif din(18) = '1' then
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dout <= "10010";
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elsif din(17) = '1' then
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dout <= "10001";
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elsif din(16) = '1' then
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dout <= "10000";
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elsif din(15) = '1' then
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dout <= "01111";
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elsif din(14) = '1' then
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dout <= "01110";
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elsif din(13) = '1' then
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dout <= "01101";
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elsif din(12) = '1' then
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dout <= "01100";
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elsif din(11) = '1' then
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dout <= "01011";
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elsif din(10) = '1' then
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dout <= "01010";
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elsif din(9) = '1' then
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dout <= "01001";
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elsif din(8) = '1' then
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dout <= "01000";
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elsif din(7) = '1' then
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dout <= "00111";
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elsif din(6) = '1' then
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dout <= "00110";
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elsif din(5) = '1' then
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dout <= "00101";
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elsif din(4) = '1' then
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dout <= "00100";
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elsif din(3) = '1' then
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dout <= "00011";
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elsif din(2) = '1' then
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dout <= "00010";
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elsif din(1) = '1' then
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dout <= "00001";
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elsif din(0) = '1' then
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dout <= "00000";
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else
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dout <= "00000";
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valid <= '0';
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end if;
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end process;
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end impl; |