31 lines
No EOL
731 B
VHDL
31 lines
No EOL
731 B
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity encoder4to2 is
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port (
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din : in STD_LOGIC_VECTOR(3 downto 0);
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dout : out STD_LOGIC_VECTOR(1 downto 0);
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valid : out STD_LOGIC -- '1' if any input is high, '0' if all zero
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);
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end encoder4to2;
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architecture impl of encoder4to2 is
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begin
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process(din)
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begin
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valid <= '1';
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if din(3) = '1' then
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dout <= "11";
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elsif din(2) = '1' then
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dout <= "10";
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elsif din(1) = '1' then
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dout <= "01";
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elsif din(0) = '1' then
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dout <= "00";
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else
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dout <= "00";
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valid <= '0';
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end if;
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end process;
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end impl; |