39 lines
No EOL
972 B
VHDL
39 lines
No EOL
972 B
VHDL
library ieee;
|
|
use ieee.std_logic_1164.all;
|
|
use ieee.numeric_std.all;
|
|
|
|
entity encoder8to3 is
|
|
port (
|
|
din : in STD_LOGIC_VECTOR(7 downto 0);
|
|
dout : out STD_LOGIC_VECTOR(2 downto 0);
|
|
valid : out STD_LOGIC -- '1' if any input is high, '0' if all zero
|
|
);
|
|
end encoder8to3;
|
|
|
|
architecture impl of encoder8to3 is
|
|
begin
|
|
process(din)
|
|
begin
|
|
valid <= '1';
|
|
if din(7) = '1' then
|
|
dout <= "111";
|
|
elsif din(6) = '1' then
|
|
dout <= "110";
|
|
elsif din(5) = '1' then
|
|
dout <= "101";
|
|
elsif din(4) = '1' then
|
|
dout <= "100";
|
|
elsif din(3) = '1' then
|
|
dout <= "011";
|
|
elsif din(2) = '1' then
|
|
dout <= "010";
|
|
elsif din(1) = '1' then
|
|
dout <= "001";
|
|
elsif din(0) = '1' then
|
|
dout <= "000";
|
|
else
|
|
dout <= "000";
|
|
valid <= '0';
|
|
end if;
|
|
end process;
|
|
end impl; |