91 lines
No EOL
2.5 KiB
VHDL
91 lines
No EOL
2.5 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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package encoder_components is
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function get_encoder_size(din_size: in natural)
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return natural;
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function get_dout_size(din_size: in natural)
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return natural;
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function get_num_encoders(num_paths_in: in integer)
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return integer;
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component encoder_generic is
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generic(
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din_size : natural
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);
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port (
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din : in STD_LOGIC_VECTOR(din_size-1 downto 0);
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dout : out STD_LOGIC_VECTOR(get_dout_size(din_size)-1 downto 0);
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valid : out STD_LOGIC -- '1' if any input is high, '0' if all zero
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);
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end component encoder_generic;
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component encoder4to2 is
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port (
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din : in STD_LOGIC_VECTOR(3 downto 0);
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dout : out STD_LOGIC_VECTOR(1 downto 0);
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valid : out STD_LOGIC -- '1' if any input is high, '0' if all zero
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);
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end component encoder4to2;
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component encoder8to3 is
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port (
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din : in STD_LOGIC_VECTOR(7 downto 0);
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dout : out STD_LOGIC_VECTOR(2 downto 0);
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valid : out STD_LOGIC -- '1' if any input is high, '0' if all zero
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);
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end component encoder8to3;
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component encoder16to4 is
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port (
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din : in STD_LOGIC_VECTOR(15 downto 0);
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dout : out STD_LOGIC_VECTOR(3 downto 0);
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valid : out STD_LOGIC -- '1' if any input is high, '0' if all zero
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);
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end component encoder16to4;
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component encoder32to5 is
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port (
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din : in STD_LOGIC_VECTOR(31 downto 0);
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dout : out STD_LOGIC_VECTOR(4 downto 0);
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valid : out STD_LOGIC -- '1' if any input is high, '0' if all zero
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);
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end component encoder32to5;
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end package;
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package body encoder_components is
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function get_encoder_size(din_size: in natural)
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return natural is
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begin
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if din_size >= 16 then
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return 32;
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elsif din_size >= 8 then
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return 16;
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else
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return 8;
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end if;
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end function;
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function get_dout_size(din_size: in natural)
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return natural is
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begin
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if din_size = 32 then
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return 5;
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elsif din_size = 16 then
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return 4;
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elsif din_size = 8 then
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return 3;
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else
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return 0;
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end if;
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end function;
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function get_num_encoders(num_paths_in: integer)
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return integer is
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begin
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return (num_paths_in+32-1)/32;
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end function;
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end package body; |