Adding subfolders for TutorialConfigs.scala
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package chipyard
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import freechips.rocketchip.config.{Config}
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import constellation.channel._
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import constellation.routing._
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import constellation.topology._
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import constellation.noc._
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import constellation.soc.{GlobalNoCParams}
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import scala.collection.immutable.ListMap
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// This file is designed to accompany a live tutorial, with slides.
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// For each of 4 phases, participants will customize and build a
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// small demonstration config.
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// This file is designed to be used after running chipyard/scripts/tutorial-setup.sh,
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// which removes the SHA3 accelerator RTL, and provides participants
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// the experience of integrating external RTL.
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// This file was originally developed for the cancelled ASPLOS-2020
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// Chipyard tutorial. While the configs here work, the corresponding
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// slideware has not yet been created.
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// NOTE: Configs should be read bottom-up, since they are applied bottom-up
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// NOTE: The TutorialConfigs build off of the AbstractConfig defined in AbstractConfig.scala
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// Users should try to understand the functionality of the AbstractConfig before proceeding
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// with the TutorialConfigs below
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// Tutorial Phase 1: Configure the cores, caches
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class TutorialStarterConfig extends Config(
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// CUSTOMIZE THE CORE
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// Uncomment out one (or multiple) of the lines below, and choose
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// how many cores you want.
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // Specify we want some number of Rocket cores
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// new boom.common.WithNSmallBooms(1) ++ // Specify we want some number of BOOM cores
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// CUSTOMIZE the L2
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// Uncomment this line, and specify a size if you want to have a L2
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// new freechips.rocketchip.subsystem.WithInclusiveCache(nBanks=1, nWays=4, capacityKB=128) ++
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// Use 2 banks of L2 cache
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new freechips.rocketchip.subsystem.WithNBanks(2) ++
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new chipyard.config.AbstractConfig
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)
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// Tutorial Phase 2: Integrate a TileLink or AXI4 MMIO device
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class TutorialMMIOConfig extends Config(
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// Attach either a TileLink or AXI4 version of GCD
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// Uncomment one of the below lines
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// new chipyard.example.WithGCD(useAXI4=false) ++ // Use TileLink version
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// new chipyard.example.WithGCD(useAXI4=true) ++ // Use AXI4 version
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// For this demonstration we assume the base system is a single-core Rocket, for fast elaboration
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++
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new chipyard.config.AbstractConfig
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)
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// Tutorial Phase 3: Integrate a SHA3 RoCC accelerator
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class TutorialSha3Config extends Config(
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// Uncomment this line once you added SHA3 to the build.sbt, and cloned the SHA3 repo
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// new sha3.WithSha3Accel ++
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// For this demonstration we assume the base system is a single-core Rocket, for fast elaboration
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++
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new chipyard.config.AbstractConfig
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)
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// Tutorial Phase 4: Integrate a Black-box verilog version of the SHA3 RoCC accelerator
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class TutorialSha3BlackBoxConfig extends Config(
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// Uncomment these lines once SHA3 is integrated
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// new sha3.WithSha3BlackBox ++ // Specify we want the Black-box verilog version of Sha3 Ctrl
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// new sha3.WithSha3Accel ++
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// For this demonstration we assume the base system is a single-core Rocket, for fast elaboration
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++
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new chipyard.config.AbstractConfig
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)
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// Tutorial Phase 5: Map a multicore heterogeneous SoC with multiple cores and memory-mapped accelerators
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class TutorialNoCConfig extends Config(
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// Try changing the dimensions of the Mesh topology
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new constellation.soc.WithGlobalNoC(constellation.soc.GlobalNoCParams(
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NoCParams(
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topology = TerminalRouter(Mesh2D(3, 4)),
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channelParamGen = (a, b) => UserChannelParams(Seq.fill(12) { UserVirtualChannelParams(4) }),
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routingRelation = NonblockingVirtualSubnetworksRouting(TerminalRouterRouting(
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Mesh2DEscapeRouting()), 10, 1)
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)
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)) ++
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// The inNodeMapping and outNodeMapping values are the physical identifiers of
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// routers on the topology to map the agents to. Try changing these to any
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// value within the range [0, topology.nNodes)
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new constellation.soc.WithPbusNoC(constellation.protocol.TLNoCParams(
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constellation.protocol.DiplomaticNetworkNodeMapping(
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inNodeMapping = ListMap("Core" -> 7),
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outNodeMapping = ListMap(
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"pbus" -> 8, "uart" -> 9, "control" -> 10, "gcd" -> 11,
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"writeQueue[0]" -> 0, "writeQueue[1]" -> 1, "tailChain[0]" -> 2))
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), true) ++
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new constellation.soc.WithSbusNoC(constellation.protocol.TLNoCParams(
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constellation.protocol.DiplomaticNetworkNodeMapping(
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inNodeMapping = ListMap(
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"Core 0" -> 0, "Core 1" -> 1,
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"serial-tl" -> 2),
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outNodeMapping = ListMap(
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"system[0]" -> 3, "system[1]" -> 4, "system[2]" -> 5, "system[3]" -> 6,
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"pbus" -> 7))
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), true) ++
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new chipyard.example.WithGCD ++
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new chipyard.harness.WithLoopbackNIC ++
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new icenet.WithIceNIC ++
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new fftgenerator.WithFFTGenerator(numPoints=8) ++
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new chipyard.example.WithStreamingFIR ++
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new chipyard.example.WithStreamingPassthrough ++
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new freechips.rocketchip.subsystem.WithNBanks(4) ++
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new freechips.rocketchip.subsystem.WithNBigCores(2) ++
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new chipyard.config.AbstractConfig
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)
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// Tutorial Phase 6: Gemmini Config
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class TutorialLeanGemminiConfig extends Config(
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// Step 1: Customize gemmini - set a config option for the accelerator: use_dedicated_tl_port=false
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new gemmini.DefaultGemminiConfig(gemmini.GemminiConfigs.leanConfig.copy(use_dedicated_tl_port=true )) ++
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// Step 2: Specify some number of Rocket + Boom cores
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// For this step, the total number of Rocket + Boom cores should <= 8
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new boom.common.WithNMediumBooms(1) ++
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new freechips.rocketchip.subsystem.WithNBigCores(3) ++
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// : Some number of L2 cache banks (keep this <= 4 as well)
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new freechips.rocketchip.subsystem.WithNBanks(4) ++
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new chipyard.config.AbstractConfig
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)
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// Tutorial Phase 6: Many Core SoC on a NoC
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class TutorialManyCoreNoCConfig extends Config(
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new constellation.soc.WithSbusNoC(constellation.protocol.TLNoCParams(
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constellation.protocol.DiplomaticNetworkNodeMapping(
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// inNodeMappings map master agents onto the NoC
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inNodeMapping = ListMap(
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"Core 0 " -> 1, "Core 1 " -> 2, "Core 2 " -> 3, "Core 3 " -> 4,
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"Core 4 " -> 7, "Core 5 " -> 7, "Core 6 " -> 8, "Core 7 " -> 8,
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"Core 8 " -> 9, "Core 9 " -> 9, "Core 10" -> 10, "Core 11" -> 10,
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"Core 12" -> 13, "Core 13" -> 13, "Core 14" -> 14, "Core 15" -> 14,
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"Core 16" -> 15, "Core 17" -> 15, "Core 18" -> 16, "Core 19" -> 16,
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"Core 20" -> 0, "Core 21" -> 6, "Core 22" -> 12, "Core 23" -> 18,
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"Core 24" -> 5, "Core 25" -> 11, "Core 26" -> 17, "Core 27" -> 23,
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"serial-tl" -> 0),
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// outNodeMappings map client agents (L2 banks) onto the NoC
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outNodeMapping = ListMap(
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"system[0]" -> 7, "system[1]" -> 8, "system[2]" -> 9, "system[3]" -> 10,
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"system[4]" -> 13, "system[5]" -> 14, "system[6]" -> 15, "system[7]" -> 16,
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"pbus" -> 5)),
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NoCParams(
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topology = TerminalRouter(Mesh2D(6, 4)),
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channelParamGen = (a, b) => UserChannelParams(Seq.fill(8) { UserVirtualChannelParams(4) }),
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routingRelation = BlockingVirtualSubnetworksRouting(TerminalRouterRouting(Mesh2DEscapeRouting()), 5, 1),
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skipValidationChecks = true
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)
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)) ++
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// ==========================================
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// DO NOT change below this line without |
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// carefully adjusting the NoC config above |
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// ==========================================
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// add LeanGemmini to Rocket-cores 0-3 (along the bottom edge of the topology)
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new chipyard.config.WithMultiRoCC ++
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new chipyard.config.WithMultiRoCCFromBuildRoCC(0, 1, 2, 3) ++
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new gemmini.DefaultGemminiConfig(gemmini.GemminiConfigs.leanConfig.copy(use_dedicated_tl_port=false)) ++
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// Add 8 duplicated 10-wide "Mega" SonicBoom cores along the left/right edges
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new boom.common.WithCloneBoomTiles(7, 20) ++
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new boom.common.WithNMegaBooms(1) ++
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// Add 16 duplicated simple RocketCores the the center region
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new freechips.rocketchip.subsystem.WithCloneRocketTiles(15, 4) ++
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++
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// Add 4 duplicated RocketCores along the bottom edge (these will hold the LeanGemmini accelerators)
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new freechips.rocketchip.subsystem.WithCloneRocketTiles(3, 0) ++
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++
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// Use 8 banks of L2 cache
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new freechips.rocketchip.subsystem.WithNBanks(8) ++
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new chipyard.config.AbstractConfig
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)
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class TutorialPhase9Config extends Config(
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new constellation.soc.WithSbusNoC(constellation.protocol.TLNoCParams(
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constellation.protocol.DiplomaticNetworkNodeMapping(
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// inNodeMappings map master agents onto the NoC
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inNodeMapping = ListMap(
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"Core 0" -> 0, // Rocket frontend + Gemmini
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"Core 1" -> 1, // Rocket frontend + Gemmini
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"Core 2" -> 2, // SonicBoom (no sonic Boom core was added)
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"serial-tl" -> 0),
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// outNodeMappings map client agents (L2 banks) onto the NoC
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outNodeMapping = ListMap(
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"system[0]" -> 3, "system[1]" -> 4,
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"pbus" -> 5)),
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NoCParams(
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topology = TerminalRouter(Mesh2D(3, 2)),
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channelParamGen = (a, b) => UserChannelParams(Seq.fill(8) { UserVirtualChannelParams(4) }),
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routingRelation = BlockingVirtualSubnetworksRouting(TerminalRouterRouting(Mesh2DEscapeRouting()), 5, 1),
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skipValidationChecks = true
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)
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)) ++
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// ==========================================
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// DO NOT change below this line without |
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// carefully adjusting the NoC config above |
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// ==========================================
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// add LeanGemmini to Rocket-core (as frontend)
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new chipyard.config.WithMultiRoCC ++
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new chipyard.config.WithMultiRoCCFromBuildRoCC(0,1) ++
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new gemmini.DefaultGemminiConfig(gemmini.GemminiConfigs.leanConfig.copy(use_dedicated_tl_port=false)) ++
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// Add 1 simple RocketCore+gemmini tile
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++
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// Add 1 simple RocketCore+gemmini tile
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++
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// Use 4 banks of L2 cache
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new freechips.rocketchip.subsystem.WithNBanks(2) ++
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new chipyard.config.AbstractConfig
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)
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class TutorialPhase9Config3dgemmini extends Config(
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new constellation.soc.WithSbusNoC(constellation.protocol.TLNoCParams(
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constellation.protocol.DiplomaticNetworkNodeMapping(
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// inNodeMappings map master agents onto the NoC
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inNodeMapping = ListMap(
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"Core 0" -> 0, // Rocket frontend + Gemmini
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"Core 1" -> 1, // Rocket frontend + Gemmini
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"Core 2" -> 2, // Rocket frontend + Gemmini
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"serial-tl" -> 0),
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// outNodeMappings map client agents (L2 banks) onto the NoC
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outNodeMapping = ListMap(
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"system[0]" -> 3, "system[1]" -> 4, "system[2]" -> 5, "system[3]" -> 6,
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"pbus" -> 7)),
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NoCParams(
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topology = TerminalRouter(BidirectionalTorus2D(4, 2)),
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//topology = TerminalRouter(BidirectionalTorus2D(4, 2)),
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channelParamGen = (a, b) => UserChannelParams(Seq.fill(8) { UserVirtualChannelParams(4) }),
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routingRelation = BlockingVirtualSubnetworksRouting(TerminalRouterRouting(Mesh2DEscapeRouting()), 5, 1),
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skipValidationChecks = true
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)
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)) ++
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// ==========================================
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// DO NOT change below this line without |
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// carefully adjusting the NoC config above |
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// ==========================================
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// add LeanGemmini to Rocket-core (as frontend)
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new chipyard.config.WithMultiRoCC ++
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new chipyard.config.WithMultiRoCCFromBuildRoCC(0,1,2) ++
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new gemmini.DefaultGemminiConfig(gemmini.GemminiConfigs.leanConfig.copy(use_dedicated_tl_port=false)) ++
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// Add 1 simple RocketCore+gemmini tile
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++
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// Add 1 simple RocketCore+gemmini tile
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++
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// Add 1 simple RocketCore+gemmini tile
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++
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// Use 4 banks of L2 cache
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new freechips.rocketchip.subsystem.WithNBanks(4) ++
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new chipyard.config.AbstractConfig
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)
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