//16 bit Linear Feedback Shift Register (LFSR)
module lfsr16 #(
    parameter DATA_WIDTH = 16
)(
    input clk,
    input rst,
    output reg [15:0] out
);
    always @(posedge clk or posedge rst) begin
        if (rst)
            out <= 16'h1;
        else
            out <= {out[14:0], out[15] ^ out[13] ^ out[12] ^ out[10]};
    end
endmodule