`timescale 1ns / 1ps module tb_top_rpas #( // Parameters parameter ROWS1 = 16, // Reading matrix rows parameter COLS1 = 12, // Reading matrix cols parameter ROWS2 = 12, parameter COLS2 = 12, parameter ROWS3 = 16, // Writing matrix rows parameter COLS3 = 32, // Writing matrix cols parameter DATA_WIDTH = 16 )(); // === Clock and Reset === reg clk = 0; reg rst = 1; always #5 clk = ~clk; // 100MHz clock (10ns period) // === Control Signals === reg enable_rpas; // === Address and Size Configs === reg [$clog2(ROWS1)-1:0] rows_start_add_reading, rows_start_add_writing, rows_size_reading, rows_size_writing; reg [$clog2(COLS1)-1:0] cols_start_add_reading, cols_size_reading; // Corrected width reg [$clog2(COLS3)-1:0] cols_size_writing, cols_start_add_writing; // === Wires for RPAS <-> Memory Connections === wire [$clog2(ROWS1)-1:0] row_addr_out_read, row_addr_out_write; wire [$clog2(COLS1)-1:0] col_addr_out_read; wire [$clog2(COLS3)-1:0] col_addr_out_write; wire write_enable; wire read_enable; wire read_valid; wire valid_result; wire [DATA_WIDTH - 1:0] data_input_to_mem_1, data_input_to_mem_2, data_input_to_mem_3; wire [DATA_WIDTH - 1:0] data_output_from_mem_1, data_output_from_mem_2, data_output_from_mem_3; reg read_full_row_or_col1, read_full_row_or_col2, read_full_row_or_col3; wire [DATA_WIDTH*((ROWS1>COLS1)?ROWS1-1:COLS1-1):0] full_row_output_1; // For full row reads //COLS1 wire [DATA_WIDTH*((ROWS2>COLS2)?ROWS2-1:COLS2-1):0] full_row_output_2; // (optional) for Matrix 2 //COLS2 wire [DATA_WIDTH*((ROWS3>COLS3)?ROWS3-1:COLS3-1):0] full_row_output_3; // (optional) for Matrix 3 //COLS3 reg write_back_to_file_enable; //writing enable the file back into the memory wire done_writing_to_file; ////writing enable the file back into the memory // === Instantiate top_module_mem === top_module_mem #( .ROWS1(ROWS1), .COLS1(COLS1), .ROWS2(ROWS2), .COLS2(COLS2), .ROWS3(ROWS3), .COLS3(COLS3), .DATA_WIDTH(DATA_WIDTH) ) u_top_mem ( .clk(clk), // Memory 1 .row_addr_1(row_addr_out_read), .col_addr_1(col_addr_out_read), .write_enable_1(), .read_enable_1(), .data_input_1(data_input_to_mem_1), .data_output_1(data_output_from_mem_1), .valid_1(read_valid), .read_full_row_or_col1(read_full_row_or_col1), //1'b0 .read_full_row_1(read_enable), .no_cols_used1(cols_size_reading), .no_rows_used1(rows_size_reading), .full_row_output_1(full_row_output_1), .full_row_input_1(), .write_full_row_1(),//////// //memory 2 .row_addr_2(), .col_addr_2(), .write_enable_2(), .read_enable_2(), .data_input_2(data_input_to_mem_2), .valid_2(), .read_full_row_or_col2(read_full_row_or_col2), .read_full_row_2(), .no_cols_used2(), .no_rows_used2(), .full_row_output_2(full_row_output_2), .full_row_input_2(), .write_full_row_2(), //memory 3 .row_addr_3(row_addr_out_write), .col_addr_3(col_addr_out_write), .write_enable_3(write_enable), .read_enable_3(), .data_input_3(data_input_to_mem_3), .data_output_3(data_output_from_mem_3), .valid_3(), .read_full_row_or_col3(read_full_row_or_col3),//////1'b0 .read_full_row_3(), .no_cols_used3(cols_size_writing),/// .no_rows_used3(rows_size_writing),/// .full_row_output_3(full_row_output_3), .full_row_input_3(), .write_full_row_3(), .write_back_to_file_enable(write_back_to_file_enable), .done_writing_to_file(done_writing_to_file) ); // === Instantiate top_module_rpas === top_module_rpas #( .ROWS_READING(ROWS1), .COLS_READING(COLS1), .ROWS_WRITING(ROWS3), .COLS_WRITING(COLS3), .DATA_WIDTH(DATA_WIDTH) ) u_rpas ( .clk(clk), .rst(rst), .enable_rpas(enable_rpas), .read_valid(read_valid), .rows_start_add_reading(rows_start_add_reading), .cols_start_add_reading(cols_start_add_reading), .rows_start_add_writing(rows_start_add_writing), .cols_start_add_writing(cols_start_add_writing), .rows_size_reading(rows_size_reading), .cols_size_reading(cols_size_reading), .rows_size_writing(rows_size_writing), .cols_size_writing(cols_size_writing), // .data_input(data_output_from_mem_1), .data_input_rows(full_row_output_1), .row_addr_out_read(row_addr_out_read), .col_addr_out_read(col_addr_out_read), .row_addr_out_write(row_addr_out_write), .col_addr_out_write(col_addr_out_write), .data_output(data_input_to_mem_3), .write_enable(write_enable), .read_enable_full_row(read_enable), .valid_result(valid_result) ); // === Test Sequence === initial begin $display("=== RPAS Testbench Starting (1/2)==="); // Initial states read_full_row_or_col1 = 0;//0 to read row wise & 1 to read col wise read_full_row_or_col3 = 1;//0 to read row wise & 1 to read col wise enable_rpas = 0; // Reset sequence #20; rst = 0; // Enable the RPAS unit #10; enable_rpas = 1; // Set read and write offsets and sizes rows_start_add_reading <= 4'b0; cols_start_add_reading <= 4'b0; rows_start_add_writing <= 4'b0; cols_start_add_writing <= 5'b0; rows_size_reading <= 4'd15; // 0 to 15 cols_size_reading <= 4'd11; // 0 to 11 rows_size_writing <= 4'd15; // 0 to 15 cols_size_writing <= 5'd31; // 0 to 31 // Wait for result wait (valid_result); #50; $display("=== RPAS Testbench Completed (1/2)==="); #10 /* $display("=== RPAS Testbench Starting (2/2)==="); // Initial states enable_rpas = 0; rst = 1; // Reset sequence #20; rst = 0; // Enable the RPAS unit #10; enable_rpas = 1; // Set read and write offsets and sizes rows_start_add_reading <= 4'b0; cols_start_add_reading <= 4'b0; rows_start_add_writing <= 4'b0; cols_start_add_writing <= 5'b0; rows_size_reading <= 4'd15; // 0 to 15 cols_size_reading <= 4'd11; // 0 to 11 rows_size_writing <= 4'd15; // 0 to 15 cols_size_writing <= 5'd31; // 0 to 31 // Wait for result wait (valid_result); #50; $display("=== RPAS Testbench Completed (2/2)==="); */ //enable writing signal for memory dump write_back_to_file_enable = 1; // Wait a few cycles to observe #20; wait(done_writing_to_file); #20 $finish; end endmodule