`timescale 1ns / 1ps

module top_controller_module_tb;

// Parameters
parameter DATA_WIDTH = 16;
parameter MEM_ROWS = 20;//20
parameter MEM_COLS = 100;//80
parameter OUTPUT_COL = 20;
parameter OUTPUT_ROW = 20;
parameter COMMON_ROW_COL = 4;
parameter PE_ROWS = 20;
parameter PE_COLS = 20;
parameter H_LIMIT = 2;//header count
parameter TOP_K = 4;


// Inputs
reg clk;
reg rst;
reg enable_top;
reg write_back_to_file_enable_top;

// Outputs
wire done_top;
wire done_writing_to_file_top;

integer cycle_count;

// Instantiate the DUT (Device Under Test)
top_controller_module #(
    .DATA_WIDTH(DATA_WIDTH),
    .MEM_ROWS(MEM_ROWS),
    .MEM_COLS(MEM_COLS),
    .OUTPUT_COL(OUTPUT_COL),
    .OUTPUT_ROW(OUTPUT_ROW),
    .COMMON_ROW_COL(COMMON_ROW_COL),
    .PE_ROWS(PE_ROWS),
    .PE_COLS(PE_COLS),
    .H_LIMIT(H_LIMIT),
    .TOP_K(TOP_K)
) uut (
    .clk(clk),
    .rst(rst),
    .enable_top(enable_top),
    .write_back_to_file_enable_top(write_back_to_file_enable_top),
    .done_top(done_top),
    .done_writing_to_file_top(done_writing_to_file_top)
);


// Cycle counting
always @(posedge clk) begin
    if (rst) begin
        cycle_count <= 0;
    end else if (enable_top && !done_top) begin
        cycle_count <= cycle_count + 1;
    end
end



// Clock Generation: 10ns period (100MHz)
initial begin
    clk = 0;
    forever #5 clk = ~clk;
end

// Test Stimulus
initial begin
    // Initialize signals
    cycle_count <= 0;
    rst = 1;
    enable_top = 0;
    write_back_to_file_enable_top = 0;

    // Hold reset for a few cycles
    #20;
    rst = 0;

    // Enable top controller
    #30;
    enable_top = 1;
    write_back_to_file_enable_top = 0;

    wait(done_top);
    $display("Top controller Operation completed in %0d cycles", cycle_count);  
    #50;
    write_back_to_file_enable_top = 1;

    wait(done_writing_to_file_top);

    // Stop simulation
    $display("Simulation finished.");
    $stop;
end

// // Monitor output states
// initial begin
//     $monitor("Time=%t | enable_top=%b | done_top=%b | done_writing_to_file_top=%b",
//              $time, enable_top, done_top, done_writing_to_file_top);
// end

endmodule