137 lines
5.7 KiB
Verilog
137 lines
5.7 KiB
Verilog
module top_module_mem #(
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parameter ROWS1 = 16, // Matrix 1: 16x12
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parameter COLS1 = 12,
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parameter ROWS2 = 12, // Matrix 2: 12x12
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parameter COLS2 = 12,
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parameter ROWS3 = 16, // Matrix 3: 16x32
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parameter COLS3 = 32,
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parameter DATA_WIDTH = 16,
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parameter COLS_USED = 4
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)(
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input clk,
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// Address Inputs
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input [$clog2(ROWS1)-1:0] row_addr_1,
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input [$clog2(COLS1)-1:0] col_addr_1,
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input [$clog2(ROWS2)-1:0] row_addr_2,
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input [$clog2(COLS2)-1:0] col_addr_2,
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input [$clog2(ROWS3)-1:0] row_addr_3,
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input [$clog2(COLS3)-1:0] col_addr_3,
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// Control Signals
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input write_enable_1, write_enable_2, write_enable_3,
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input read_enable_1, read_enable_2, read_enable_3,
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input read_full_row_1, read_full_row_2, read_full_row_3, // NEW signals
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input write_full_row_1, write_full_row_2, write_full_row_3, // NEW signals
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input read_full_row_or_col1, read_full_row_or_col2, read_full_row_or_col3, //0 to read row wise & 1 to read col wise
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// Data Inputs
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input [DATA_WIDTH-1:0] data_input_1, data_input_2, data_input_3,
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input [DATA_WIDTH*((ROWS1>COLS1)?ROWS1-1:COLS1-1):0] full_row_input_1,
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input [DATA_WIDTH*((ROWS2>COLS2)?ROWS2-1:COLS2-1):0] full_row_input_2,
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input [DATA_WIDTH*((ROWS3>COLS3)?ROWS3-1:COLS3-1):0] full_row_input_3,
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input [$clog2(COLS1)-1:0] no_cols_used1, // in row wise reading or writing
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input [$clog2(COLS2)-1:0] no_cols_used2, // in row wise reading or writing
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input [$clog2(COLS3)-1:0] no_cols_used3, // in row wise reading or writing
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input [$clog2(ROWS1)-1:0] no_rows_used1, // in col wise reading or writing
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input [$clog2(ROWS2)-1:0] no_rows_used2, // in col wise reading or writing
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input [$clog2(ROWS3)-1:0] no_rows_used3, // in col wise reading or writing
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input write_back_to_file_enable,
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// Data Outputs
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output [DATA_WIDTH-1:0] data_output_1, data_output_2, data_output_3,
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output [DATA_WIDTH*((ROWS1>COLS1)?ROWS1-1:COLS1-1):0] full_row_output_1, // For full row reads //COLS1
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output [DATA_WIDTH*((ROWS2>COLS2)?ROWS2-1:COLS2-1):0] full_row_output_2, // (optional) for Matrix 2 //COLS2
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output [DATA_WIDTH*((ROWS3>COLS3)?ROWS3-1:COLS3-1):0] full_row_output_3, // (optional) for Matrix 3 //COLS3
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output done_writing_to_file,
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// Valid outputs
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output valid_1, valid_2, valid_3
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);
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// === Memory Block 1: Matrix 1 (A Matrix, Input) ===
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matrix_memory_flexible #(
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.MEM_ROWS(ROWS1),
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.MEM_COLS(COLS1),
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.INIT_FILE("D:/Project_verilog_item/project_files/hdl_verilog/phase5/matrix_data_temp_20_X_100_column_wise.hex"),
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.DATA_WIDTH(DATA_WIDTH),
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.COLS_USED(COLS_USED),
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.OUTPUT_FILE("D:/Project_verilog_item/project_files/hdl_verilog/phase5/file_dump/mem1.hex")
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) u_matrix_mem_1 (
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.clk(clk),
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.write_enable(write_enable_1),
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.write_full_row(write_full_row_1),
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.full_row_in(full_row_input_1),
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.read_enable(read_enable_1),
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.read_full_row(read_full_row_1),
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.row(row_addr_1),
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.col(col_addr_1),
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.read_full_row_or_col(read_full_row_or_col1),
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.no_cols_used(no_cols_used1),
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.no_rows_used(no_rows_used1),
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.data_in(data_input_1),
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.write_back_to_file_enable(write_back_to_file_enable),
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.data_out(data_output_1),
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.full_row_out(full_row_output_1),
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.valid(valid_1),
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.done_writing_to_file(done_writing_to_file)
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);
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// === Memory Block 2: Matrix 2 (Weights) ===
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matrix_memory_flexible #(
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.MEM_ROWS(ROWS2),
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.MEM_COLS(COLS2),
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.INIT_FILE("D:/Project_verilog_item/project_files/hdl_verilog/phase5/matrix_data_temp_20_X_100_column_wise.hex"),
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.DATA_WIDTH(DATA_WIDTH),
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.COLS_USED(COLS_USED),
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.OUTPUT_FILE("D:/Project_verilog_item/project_files/hdl_verilog/phase5/file_dump/mem2.hex")
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) u_matrix_mem_2 (
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.clk(clk),
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.write_enable(write_enable_2),
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.read_enable(read_enable_2),
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.write_full_row(write_full_row_2),
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.full_row_in(full_row_input_2),
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.read_full_row(read_full_row_2),
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.row(row_addr_2),
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.col(col_addr_2),
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.read_full_row_or_col(read_full_row_or_col2),
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.no_cols_used(no_cols_used2),
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.no_rows_used(no_rows_used2),
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.data_in(data_input_2),
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.write_back_to_file_enable(write_back_to_file_enable),
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.data_out(data_output_2),
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.full_row_out(full_row_output_2),
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.valid(valid_2),
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.done_writing_to_file(done_writing_to_file)
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);
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// === Memory Block 3: Matrix 3 (Temporary / Output Buffer) ===
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matrix_memory_flexible #(
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.MEM_ROWS(ROWS3),
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.MEM_COLS(COLS3),
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.INIT_FILE("D:/Project_verilog_item/project_files/hdl_verilog/phase5/matrix_data_temp_20_X_100_ones.hex"),
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.DATA_WIDTH(DATA_WIDTH),
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.COLS_USED(COLS_USED),
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.OUTPUT_FILE("D:/Project_verilog_item/project_files/hdl_verilog/phase5/file_dump/mem3.hex")
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) u_matrix_mem_3 (
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.clk(clk),
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.write_enable(write_enable_3),
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.read_enable(read_enable_3),
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.write_full_row(write_full_row_3),
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.full_row_in(full_row_input_3),
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.read_full_row(read_full_row_3),
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.row(row_addr_3),
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.col(col_addr_3),
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.read_full_row_or_col(read_full_row_or_col3),
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.no_cols_used(no_cols_used3),
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.no_rows_used(no_rows_used3),
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.data_in(data_input_3),
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.write_back_to_file_enable(write_back_to_file_enable),
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.data_out(data_output_3),
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.full_row_out(full_row_output_3),
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.valid(valid_3),
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.done_writing_to_file(done_writing_to_file)
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);
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endmodule
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