82 lines
2.9 KiB
VHDL
82 lines
2.9 KiB
VHDL
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-------------------------------------------------------------------------------
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-- Title : FiFo buffer regular (no moving of data in buffer;
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-- for credit based flow-control)
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-- Project : Modular, heterogenous 3D NoC
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-------------------------------------------------------------------------------
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-- File : fifo.vhd
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-- Author : Lennart Bamberg <bamberg@office.item.uni-bremen.de>
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-- Company :
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-- Created : 2018-05-24
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-- Last update: 2018-11-28
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-- Platform :
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-- Standard : VHDL'93/02
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-------------------------------------------------------------------------------
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-- Description: Buffer to read or write one flit (credit-based flow ctrl)
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-- when read_enable is set the first word is already fetched in
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-- the same clock cycle (NOT THE NEXT CYCLE!)
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-------------------------------------------------------------------------------
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-- Copyright (c) 2018
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-------------------------------------------------------------------------------
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-- Revisions :
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-- Date Version Author Description
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-- 2018-05-24 1.0 bamberg Created
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.math_real.all;
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use work.NOC_3D_PACKAGE.all;
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entity fifo is
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generic (
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buff_depth : integer := 4); -- buffer depths
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port (
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data_in : in flit; -- Data in
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write_en : in std_logic; -- Write enable
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read_en : in std_logic; -- Read enable
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clk, rst : in std_logic;
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data_out : out flit; -- Output data
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valid_data : out std_logic); -- Buffer not empty
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end entity fifo;
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architecture rtl of fifo is
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signal read_pointer, write_pointer :
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unsigned(bit_width(buff_depth)-1 downto 0);
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type buffer_type is array (buff_depth-1 downto 0) of flit;
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signal fifo : buffer_type;
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begin
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-- BUFFER + READ/WRITE POINTER
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process(clk, rst)
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begin
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if rst = RST_LVL then
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write_pointer <= (others => '0');
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read_pointer <= (others => '0');
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fifo <= (others => (others => '0'));
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elsif clk'event and clk = '1' then
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if write_en = '1' then
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fifo(to_integer(write_pointer)) <= data_in;
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write_pointer <= (write_pointer + 1) mod buff_depth;
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end if;
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if read_en = '1' then
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read_pointer <= (read_pointer + 1) mod buff_depth;
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end if;
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end if;
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end process;
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data_out <= fifo(to_integer(read_pointer));
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process(clk, rst)
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begin
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if rst = RST_LVL then
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valid_data <= '0';
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elsif clk = '1' and clk'event then
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if write_en = '1' then
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valid_data <= '1';
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elsif (write_pointer = ((read_pointer+1) mod buff_depth) and read_en = '1')
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or (buff_depth = 1 and read_en = '1') then
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valid_data <= '0';
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end if;
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end if;
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end process;
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end architecture;
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