5013 lines
232 KiB
VHDL
5013 lines
232 KiB
VHDL
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-------------------------------------------------------------------------------
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-- Title : Full Noc with packet injector
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-- Automatically generated by full_noc_generator.py
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-- Project :
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-------------------------------------------------------------------------------
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-- File : full_noc.vhd
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-- Author : Behnam Razi Perjikolaei <raziperj@uni-bremen.de>
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-- Company :
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-- Created : 2019-06-17
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-- Last update: 2020-09-18
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-- Platform :
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-- Standard : VHDL'87
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-------------------------------------------------------------------------------
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-- Description:
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-------------------------------------------------------------------------------
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-- Copyright (c) 2019
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-------------------------------------------------------------------------------
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-- Revisions :
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-- Date Version Author Description
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-- 2019-05-29 1.0 behnam Created
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use IEEE.math_real.all;
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USE ieee.numeric_std.ALL;
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use work.NOC_3D_PACKAGE.all;
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entity full_noc is
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port(
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clk, rst : in std_logic;
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local_rx : in flit_vector(48-1 downto 0);
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local_vc_write_rx : in std_logic_vector(192-1 downto 0);
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local_incr_rx_vec : in std_logic_vector(192-1 downto 0);
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local_tx : out flit_vector(48-1 downto 0);
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local_vc_write_tx : out std_logic_vector(192-1 downto 0);
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local_incr_tx_vec : out std_logic_vector(192-1 downto 0)
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);
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end entity full_noc;
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architecture structural of full_noc is
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type flit_vector_array is array (0 to 2) of flit_vector(max_port_num-1 downto 0);
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type flit_vector_2D_array is array (0 to 3) of flit_vector_array;
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type flit_vector_3D_array is array (0 to 3) of flit_vector_2D_array;
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subtype incr_per_port is std_logic_vector(4-1 downto 0);
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type incr_per_router is array (max_port_num-1 downto 0) of incr_per_port;
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type incr_array is array (0 to 2) of incr_per_router;
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type incr_2D_array is array (0 to 3) of incr_array;
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type incr_3D_array is array (0 to 3) of incr_2D_array;
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signal inter_data_in : flit_vector_3D_array;
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signal inter_data_out : flit_vector_3D_array;
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signal inter_incr_in : incr_3D_array;
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signal inter_incr_out : incr_3D_array;
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signal inter_vc_write_in : incr_3D_array;
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signal inter_vc_write_out : incr_3D_array;
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signal data_in000, data_out000: flit_vector(4-1 downto 0);
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signal vc_write_rx_vec000: std_logic_vector(16-1 downto 0);
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signal incr_rx_vec000: std_logic_vector(16-1 downto 0);
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signal vc_write_tx_pl_vec000: std_logic_vector(16-1 downto 0);
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signal incr_tx_pl_vec000: std_logic_vector(16-1 downto 0);
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signal data_in100, data_out100: flit_vector(5-1 downto 0);
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signal vc_write_rx_vec100: std_logic_vector(20-1 downto 0);
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signal incr_rx_vec100: std_logic_vector(20-1 downto 0);
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signal vc_write_tx_pl_vec100: std_logic_vector(20-1 downto 0);
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signal incr_tx_pl_vec100: std_logic_vector(20-1 downto 0);
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signal data_in200, data_out200: flit_vector(5-1 downto 0);
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signal vc_write_rx_vec200: std_logic_vector(20-1 downto 0);
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signal incr_rx_vec200: std_logic_vector(20-1 downto 0);
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signal vc_write_tx_pl_vec200: std_logic_vector(20-1 downto 0);
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signal incr_tx_pl_vec200: std_logic_vector(20-1 downto 0);
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signal data_in300, data_out300: flit_vector(4-1 downto 0);
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signal vc_write_rx_vec300: std_logic_vector(16-1 downto 0);
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signal incr_rx_vec300: std_logic_vector(16-1 downto 0);
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signal vc_write_tx_pl_vec300: std_logic_vector(16-1 downto 0);
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signal incr_tx_pl_vec300: std_logic_vector(16-1 downto 0);
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signal data_in010, data_out010: flit_vector(5-1 downto 0);
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signal vc_write_rx_vec010: std_logic_vector(20-1 downto 0);
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signal incr_rx_vec010: std_logic_vector(20-1 downto 0);
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signal vc_write_tx_pl_vec010: std_logic_vector(20-1 downto 0);
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signal incr_tx_pl_vec010: std_logic_vector(20-1 downto 0);
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signal data_in110, data_out110: flit_vector(6-1 downto 0);
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signal vc_write_rx_vec110: std_logic_vector(24-1 downto 0);
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signal incr_rx_vec110: std_logic_vector(24-1 downto 0);
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signal vc_write_tx_pl_vec110: std_logic_vector(24-1 downto 0);
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signal incr_tx_pl_vec110: std_logic_vector(24-1 downto 0);
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signal data_in210, data_out210: flit_vector(6-1 downto 0);
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signal vc_write_rx_vec210: std_logic_vector(24-1 downto 0);
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signal incr_rx_vec210: std_logic_vector(24-1 downto 0);
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signal vc_write_tx_pl_vec210: std_logic_vector(24-1 downto 0);
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signal incr_tx_pl_vec210: std_logic_vector(24-1 downto 0);
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signal data_in310, data_out310: flit_vector(5-1 downto 0);
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signal vc_write_rx_vec310: std_logic_vector(20-1 downto 0);
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signal incr_rx_vec310: std_logic_vector(20-1 downto 0);
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signal vc_write_tx_pl_vec310: std_logic_vector(20-1 downto 0);
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signal incr_tx_pl_vec310: std_logic_vector(20-1 downto 0);
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signal data_in020, data_out020: flit_vector(5-1 downto 0);
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signal vc_write_rx_vec020: std_logic_vector(20-1 downto 0);
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signal incr_rx_vec020: std_logic_vector(20-1 downto 0);
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signal vc_write_tx_pl_vec020: std_logic_vector(20-1 downto 0);
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signal incr_tx_pl_vec020: std_logic_vector(20-1 downto 0);
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signal data_in120, data_out120: flit_vector(6-1 downto 0);
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signal vc_write_rx_vec120: std_logic_vector(24-1 downto 0);
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signal incr_rx_vec120: std_logic_vector(24-1 downto 0);
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signal vc_write_tx_pl_vec120: std_logic_vector(24-1 downto 0);
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signal incr_tx_pl_vec120: std_logic_vector(24-1 downto 0);
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signal data_in220, data_out220: flit_vector(6-1 downto 0);
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signal vc_write_rx_vec220: std_logic_vector(24-1 downto 0);
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signal incr_rx_vec220: std_logic_vector(24-1 downto 0);
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signal vc_write_tx_pl_vec220: std_logic_vector(24-1 downto 0);
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signal incr_tx_pl_vec220: std_logic_vector(24-1 downto 0);
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signal data_in320, data_out320: flit_vector(5-1 downto 0);
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signal vc_write_rx_vec320: std_logic_vector(20-1 downto 0);
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signal incr_rx_vec320: std_logic_vector(20-1 downto 0);
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signal vc_write_tx_pl_vec320: std_logic_vector(20-1 downto 0);
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signal incr_tx_pl_vec320: std_logic_vector(20-1 downto 0);
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signal data_in030, data_out030: flit_vector(4-1 downto 0);
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signal vc_write_rx_vec030: std_logic_vector(16-1 downto 0);
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signal incr_rx_vec030: std_logic_vector(16-1 downto 0);
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signal vc_write_tx_pl_vec030: std_logic_vector(16-1 downto 0);
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signal incr_tx_pl_vec030: std_logic_vector(16-1 downto 0);
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signal data_in130, data_out130: flit_vector(5-1 downto 0);
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signal vc_write_rx_vec130: std_logic_vector(20-1 downto 0);
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signal incr_rx_vec130: std_logic_vector(20-1 downto 0);
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signal vc_write_tx_pl_vec130: std_logic_vector(20-1 downto 0);
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signal incr_tx_pl_vec130: std_logic_vector(20-1 downto 0);
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signal data_in230, data_out230: flit_vector(5-1 downto 0);
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signal vc_write_rx_vec230: std_logic_vector(20-1 downto 0);
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signal incr_rx_vec230: std_logic_vector(20-1 downto 0);
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signal vc_write_tx_pl_vec230: std_logic_vector(20-1 downto 0);
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signal incr_tx_pl_vec230: std_logic_vector(20-1 downto 0);
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signal data_in330, data_out330: flit_vector(4-1 downto 0);
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signal vc_write_rx_vec330: std_logic_vector(16-1 downto 0);
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signal incr_rx_vec330: std_logic_vector(16-1 downto 0);
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signal vc_write_tx_pl_vec330: std_logic_vector(16-1 downto 0);
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signal incr_tx_pl_vec330: std_logic_vector(16-1 downto 0);
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signal data_in001, data_out001: flit_vector(5-1 downto 0);
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signal vc_write_rx_vec001: std_logic_vector(20-1 downto 0);
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signal incr_rx_vec001: std_logic_vector(20-1 downto 0);
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signal vc_write_tx_pl_vec001: std_logic_vector(20-1 downto 0);
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signal incr_tx_pl_vec001: std_logic_vector(20-1 downto 0);
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signal data_in101, data_out101: flit_vector(6-1 downto 0);
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signal vc_write_rx_vec101: std_logic_vector(24-1 downto 0);
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signal incr_rx_vec101: std_logic_vector(24-1 downto 0);
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signal vc_write_tx_pl_vec101: std_logic_vector(24-1 downto 0);
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signal incr_tx_pl_vec101: std_logic_vector(24-1 downto 0);
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signal data_in201, data_out201: flit_vector(6-1 downto 0);
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signal vc_write_rx_vec201: std_logic_vector(24-1 downto 0);
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signal incr_rx_vec201: std_logic_vector(24-1 downto 0);
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signal vc_write_tx_pl_vec201: std_logic_vector(24-1 downto 0);
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signal incr_tx_pl_vec201: std_logic_vector(24-1 downto 0);
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signal data_in301, data_out301: flit_vector(5-1 downto 0);
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signal vc_write_rx_vec301: std_logic_vector(20-1 downto 0);
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signal incr_rx_vec301: std_logic_vector(20-1 downto 0);
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signal vc_write_tx_pl_vec301: std_logic_vector(20-1 downto 0);
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signal incr_tx_pl_vec301: std_logic_vector(20-1 downto 0);
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signal data_in011, data_out011: flit_vector(6-1 downto 0);
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signal vc_write_rx_vec011: std_logic_vector(24-1 downto 0);
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signal incr_rx_vec011: std_logic_vector(24-1 downto 0);
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signal vc_write_tx_pl_vec011: std_logic_vector(24-1 downto 0);
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signal incr_tx_pl_vec011: std_logic_vector(24-1 downto 0);
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signal data_in111, data_out111: flit_vector(7-1 downto 0);
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signal vc_write_rx_vec111: std_logic_vector(28-1 downto 0);
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signal incr_rx_vec111: std_logic_vector(28-1 downto 0);
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signal vc_write_tx_pl_vec111: std_logic_vector(28-1 downto 0);
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signal incr_tx_pl_vec111: std_logic_vector(28-1 downto 0);
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signal data_in211, data_out211: flit_vector(7-1 downto 0);
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signal vc_write_rx_vec211: std_logic_vector(28-1 downto 0);
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signal incr_rx_vec211: std_logic_vector(28-1 downto 0);
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signal vc_write_tx_pl_vec211: std_logic_vector(28-1 downto 0);
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signal incr_tx_pl_vec211: std_logic_vector(28-1 downto 0);
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signal data_in311, data_out311: flit_vector(6-1 downto 0);
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signal vc_write_rx_vec311: std_logic_vector(24-1 downto 0);
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signal incr_rx_vec311: std_logic_vector(24-1 downto 0);
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signal vc_write_tx_pl_vec311: std_logic_vector(24-1 downto 0);
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signal incr_tx_pl_vec311: std_logic_vector(24-1 downto 0);
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signal data_in021, data_out021: flit_vector(6-1 downto 0);
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signal vc_write_rx_vec021: std_logic_vector(24-1 downto 0);
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signal incr_rx_vec021: std_logic_vector(24-1 downto 0);
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signal vc_write_tx_pl_vec021: std_logic_vector(24-1 downto 0);
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signal incr_tx_pl_vec021: std_logic_vector(24-1 downto 0);
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signal data_in121, data_out121: flit_vector(7-1 downto 0);
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signal vc_write_rx_vec121: std_logic_vector(28-1 downto 0);
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signal incr_rx_vec121: std_logic_vector(28-1 downto 0);
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signal vc_write_tx_pl_vec121: std_logic_vector(28-1 downto 0);
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signal incr_tx_pl_vec121: std_logic_vector(28-1 downto 0);
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signal data_in221, data_out221: flit_vector(7-1 downto 0);
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signal vc_write_rx_vec221: std_logic_vector(28-1 downto 0);
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signal incr_rx_vec221: std_logic_vector(28-1 downto 0);
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signal vc_write_tx_pl_vec221: std_logic_vector(28-1 downto 0);
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signal incr_tx_pl_vec221: std_logic_vector(28-1 downto 0);
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signal data_in321, data_out321: flit_vector(6-1 downto 0);
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signal vc_write_rx_vec321: std_logic_vector(24-1 downto 0);
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signal incr_rx_vec321: std_logic_vector(24-1 downto 0);
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signal vc_write_tx_pl_vec321: std_logic_vector(24-1 downto 0);
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signal incr_tx_pl_vec321: std_logic_vector(24-1 downto 0);
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signal data_in031, data_out031: flit_vector(5-1 downto 0);
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signal vc_write_rx_vec031: std_logic_vector(20-1 downto 0);
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signal incr_rx_vec031: std_logic_vector(20-1 downto 0);
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signal vc_write_tx_pl_vec031: std_logic_vector(20-1 downto 0);
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signal incr_tx_pl_vec031: std_logic_vector(20-1 downto 0);
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signal data_in131, data_out131: flit_vector(6-1 downto 0);
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signal vc_write_rx_vec131: std_logic_vector(24-1 downto 0);
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signal incr_rx_vec131: std_logic_vector(24-1 downto 0);
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signal vc_write_tx_pl_vec131: std_logic_vector(24-1 downto 0);
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signal incr_tx_pl_vec131: std_logic_vector(24-1 downto 0);
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signal data_in231, data_out231: flit_vector(6-1 downto 0);
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signal vc_write_rx_vec231: std_logic_vector(24-1 downto 0);
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signal incr_rx_vec231: std_logic_vector(24-1 downto 0);
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signal vc_write_tx_pl_vec231: std_logic_vector(24-1 downto 0);
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signal incr_tx_pl_vec231: std_logic_vector(24-1 downto 0);
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signal data_in331, data_out331: flit_vector(5-1 downto 0);
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signal vc_write_rx_vec331: std_logic_vector(20-1 downto 0);
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signal incr_rx_vec331: std_logic_vector(20-1 downto 0);
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signal vc_write_tx_pl_vec331: std_logic_vector(20-1 downto 0);
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signal incr_tx_pl_vec331: std_logic_vector(20-1 downto 0);
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signal data_in002, data_out002: flit_vector(4-1 downto 0);
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signal vc_write_rx_vec002: std_logic_vector(16-1 downto 0);
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signal incr_rx_vec002: std_logic_vector(16-1 downto 0);
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signal vc_write_tx_pl_vec002: std_logic_vector(16-1 downto 0);
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signal incr_tx_pl_vec002: std_logic_vector(16-1 downto 0);
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signal data_in102, data_out102: flit_vector(5-1 downto 0);
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signal vc_write_rx_vec102: std_logic_vector(20-1 downto 0);
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signal incr_rx_vec102: std_logic_vector(20-1 downto 0);
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signal vc_write_tx_pl_vec102: std_logic_vector(20-1 downto 0);
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signal incr_tx_pl_vec102: std_logic_vector(20-1 downto 0);
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signal data_in202, data_out202: flit_vector(5-1 downto 0);
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signal vc_write_rx_vec202: std_logic_vector(20-1 downto 0);
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signal incr_rx_vec202: std_logic_vector(20-1 downto 0);
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signal vc_write_tx_pl_vec202: std_logic_vector(20-1 downto 0);
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signal incr_tx_pl_vec202: std_logic_vector(20-1 downto 0);
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signal data_in302, data_out302: flit_vector(4-1 downto 0);
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signal vc_write_rx_vec302: std_logic_vector(16-1 downto 0);
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|
signal incr_rx_vec302: std_logic_vector(16-1 downto 0);
|
||
|
|
signal vc_write_tx_pl_vec302: std_logic_vector(16-1 downto 0);
|
||
|
|
signal incr_tx_pl_vec302: std_logic_vector(16-1 downto 0);
|
||
|
|
signal data_in012, data_out012: flit_vector(5-1 downto 0);
|
||
|
|
signal vc_write_rx_vec012: std_logic_vector(20-1 downto 0);
|
||
|
|
signal incr_rx_vec012: std_logic_vector(20-1 downto 0);
|
||
|
|
signal vc_write_tx_pl_vec012: std_logic_vector(20-1 downto 0);
|
||
|
|
signal incr_tx_pl_vec012: std_logic_vector(20-1 downto 0);
|
||
|
|
signal data_in112, data_out112: flit_vector(6-1 downto 0);
|
||
|
|
signal vc_write_rx_vec112: std_logic_vector(24-1 downto 0);
|
||
|
|
signal incr_rx_vec112: std_logic_vector(24-1 downto 0);
|
||
|
|
signal vc_write_tx_pl_vec112: std_logic_vector(24-1 downto 0);
|
||
|
|
signal incr_tx_pl_vec112: std_logic_vector(24-1 downto 0);
|
||
|
|
signal data_in212, data_out212: flit_vector(6-1 downto 0);
|
||
|
|
signal vc_write_rx_vec212: std_logic_vector(24-1 downto 0);
|
||
|
|
signal incr_rx_vec212: std_logic_vector(24-1 downto 0);
|
||
|
|
signal vc_write_tx_pl_vec212: std_logic_vector(24-1 downto 0);
|
||
|
|
signal incr_tx_pl_vec212: std_logic_vector(24-1 downto 0);
|
||
|
|
signal data_in312, data_out312: flit_vector(5-1 downto 0);
|
||
|
|
signal vc_write_rx_vec312: std_logic_vector(20-1 downto 0);
|
||
|
|
signal incr_rx_vec312: std_logic_vector(20-1 downto 0);
|
||
|
|
signal vc_write_tx_pl_vec312: std_logic_vector(20-1 downto 0);
|
||
|
|
signal incr_tx_pl_vec312: std_logic_vector(20-1 downto 0);
|
||
|
|
signal data_in022, data_out022: flit_vector(5-1 downto 0);
|
||
|
|
signal vc_write_rx_vec022: std_logic_vector(20-1 downto 0);
|
||
|
|
signal incr_rx_vec022: std_logic_vector(20-1 downto 0);
|
||
|
|
signal vc_write_tx_pl_vec022: std_logic_vector(20-1 downto 0);
|
||
|
|
signal incr_tx_pl_vec022: std_logic_vector(20-1 downto 0);
|
||
|
|
signal data_in122, data_out122: flit_vector(6-1 downto 0);
|
||
|
|
signal vc_write_rx_vec122: std_logic_vector(24-1 downto 0);
|
||
|
|
signal incr_rx_vec122: std_logic_vector(24-1 downto 0);
|
||
|
|
signal vc_write_tx_pl_vec122: std_logic_vector(24-1 downto 0);
|
||
|
|
signal incr_tx_pl_vec122: std_logic_vector(24-1 downto 0);
|
||
|
|
signal data_in222, data_out222: flit_vector(6-1 downto 0);
|
||
|
|
signal vc_write_rx_vec222: std_logic_vector(24-1 downto 0);
|
||
|
|
signal incr_rx_vec222: std_logic_vector(24-1 downto 0);
|
||
|
|
signal vc_write_tx_pl_vec222: std_logic_vector(24-1 downto 0);
|
||
|
|
signal incr_tx_pl_vec222: std_logic_vector(24-1 downto 0);
|
||
|
|
signal data_in322, data_out322: flit_vector(5-1 downto 0);
|
||
|
|
signal vc_write_rx_vec322: std_logic_vector(20-1 downto 0);
|
||
|
|
signal incr_rx_vec322: std_logic_vector(20-1 downto 0);
|
||
|
|
signal vc_write_tx_pl_vec322: std_logic_vector(20-1 downto 0);
|
||
|
|
signal incr_tx_pl_vec322: std_logic_vector(20-1 downto 0);
|
||
|
|
signal data_in032, data_out032: flit_vector(4-1 downto 0);
|
||
|
|
signal vc_write_rx_vec032: std_logic_vector(16-1 downto 0);
|
||
|
|
signal incr_rx_vec032: std_logic_vector(16-1 downto 0);
|
||
|
|
signal vc_write_tx_pl_vec032: std_logic_vector(16-1 downto 0);
|
||
|
|
signal incr_tx_pl_vec032: std_logic_vector(16-1 downto 0);
|
||
|
|
signal data_in132, data_out132: flit_vector(5-1 downto 0);
|
||
|
|
signal vc_write_rx_vec132: std_logic_vector(20-1 downto 0);
|
||
|
|
signal incr_rx_vec132: std_logic_vector(20-1 downto 0);
|
||
|
|
signal vc_write_tx_pl_vec132: std_logic_vector(20-1 downto 0);
|
||
|
|
signal incr_tx_pl_vec132: std_logic_vector(20-1 downto 0);
|
||
|
|
signal data_in232, data_out232: flit_vector(5-1 downto 0);
|
||
|
|
signal vc_write_rx_vec232: std_logic_vector(20-1 downto 0);
|
||
|
|
signal incr_rx_vec232: std_logic_vector(20-1 downto 0);
|
||
|
|
signal vc_write_tx_pl_vec232: std_logic_vector(20-1 downto 0);
|
||
|
|
signal incr_tx_pl_vec232: std_logic_vector(20-1 downto 0);
|
||
|
|
signal data_in332, data_out332: flit_vector(4-1 downto 0);
|
||
|
|
signal vc_write_rx_vec332: std_logic_vector(16-1 downto 0);
|
||
|
|
signal incr_rx_vec332: std_logic_vector(16-1 downto 0);
|
||
|
|
signal vc_write_tx_pl_vec332: std_logic_vector(16-1 downto 0);
|
||
|
|
signal incr_tx_pl_vec332: std_logic_vector(16-1 downto 0);
|
||
|
|
|
||
|
|
signal data_rx110, data_tx110 : std_logic_vector(6*flit_size-1 downto 0);
|
||
|
|
begin
|
||
|
|
data_in000(0) <= inter_data_in(0)(0)(0)(0);
|
||
|
|
inter_data_out(0)(0)(0)(0) <= data_out000(0) after delay_constant;
|
||
|
|
incr_rx_vec000(4-1 downto 0) <= inter_incr_in(0)(0)(0)(0)(4-1 downto 0);
|
||
|
|
inter_incr_out(0)(0)(0)(0)(4-1 downto 0) <= incr_tx_pl_vec000(4-1 downto 0);
|
||
|
|
vc_write_rx_vec000(4-1 downto 0) <= inter_vc_write_in(0)(0)(0)(0)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(0)(0)(0)(0)(4-1 downto 0) <= vc_write_tx_pl_vec000(4-1 downto 0);
|
||
|
|
data_in000(1) <= inter_data_in(0)(0)(0)(1);
|
||
|
|
inter_data_out(0)(0)(0)(1) <= data_out000(1) after delay_constant;
|
||
|
|
incr_rx_vec000(8-1 downto 4) <= inter_incr_in(0)(0)(0)(1)(4-1 downto 0);
|
||
|
|
inter_incr_out(0)(0)(0)(1)(4-1 downto 0) <= incr_tx_pl_vec000(8-1 downto 4);
|
||
|
|
vc_write_rx_vec000(8-1 downto 4) <= inter_vc_write_in(0)(0)(0)(1)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(0)(0)(0)(1)(4-1 downto 0) <= vc_write_tx_pl_vec000(8-1 downto 4);
|
||
|
|
|
||
|
|
inter_data_in(0)(0)(0)(1) <= inter_data_out(0)(0+1)(0)(3);
|
||
|
|
|
||
|
|
inter_incr_in(0)(0)(0)(1) <= inter_incr_out(0)(0+1)(0)(3);
|
||
|
|
|
||
|
|
inter_vc_write_in(0)(0)(0)(1) <= inter_vc_write_out(0)(0+1)(0)(3);
|
||
|
|
data_in000(2) <= inter_data_in(0)(0)(0)(2);
|
||
|
|
inter_data_out(0)(0)(0)(2) <= data_out000(2) after delay_constant;
|
||
|
|
incr_rx_vec000(12-1 downto 8) <= inter_incr_in(0)(0)(0)(2)(4-1 downto 0);
|
||
|
|
inter_incr_out(0)(0)(0)(2)(4-1 downto 0) <= incr_tx_pl_vec000(12-1 downto 8);
|
||
|
|
vc_write_rx_vec000(12-1 downto 8) <= inter_vc_write_in(0)(0)(0)(2)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(0)(0)(0)(2)(4-1 downto 0) <= vc_write_tx_pl_vec000(12-1 downto 8);
|
||
|
|
|
||
|
|
inter_data_in(0)(0)(0)(2) <= inter_data_out(0+1)(0)(0)(4);
|
||
|
|
|
||
|
|
inter_incr_in(0)(0)(0)(2) <= inter_incr_out(0+1)(0)(0)(4);
|
||
|
|
|
||
|
|
inter_vc_write_in(0)(0)(0)(2) <= inter_vc_write_out(0+1)(0)(0)(4);
|
||
|
|
data_in000(3) <= inter_data_in(0)(0)(0)(5);
|
||
|
|
inter_data_out(0)(0)(0)(5) <= data_out000(3) after delay_constant;
|
||
|
|
incr_rx_vec000(16-1 downto 12) <= inter_incr_in(0)(0)(0)(5)(4-1 downto 0);
|
||
|
|
inter_incr_out(0)(0)(0)(5)(4-1 downto 0) <= incr_tx_pl_vec000(16-1 downto 12);
|
||
|
|
vc_write_rx_vec000(16-1 downto 12) <= inter_vc_write_in(0)(0)(0)(5)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(0)(0)(0)(5)(4-1 downto 0) <= vc_write_tx_pl_vec000(16-1 downto 12);
|
||
|
|
|
||
|
|
inter_data_in(0)(0)(0)(5) <= inter_data_out(0)(0)(0+1)(6);
|
||
|
|
|
||
|
|
inter_incr_in(0)(0)(0)(5) <= inter_incr_out(0)(0)(0+1)(6);
|
||
|
|
|
||
|
|
inter_vc_write_in(0)(0)(0)(5) <= inter_vc_write_out(0)(0)(0+1)(6);
|
||
|
|
|
||
|
|
inter_data_in(0)(0)(0)(0) <= local_rx(0);
|
||
|
|
local_tx(0) <= inter_data_out(0)(0)(0)(0);
|
||
|
|
|
||
|
|
inter_incr_in(0)(0)(0)(0)(4-1 downto 0) <= local_incr_rx_vec(4-1 downto 0);
|
||
|
|
local_incr_tx_vec(4-1 downto 0) <= inter_incr_out(0)(0)(0)(0)(4-1 downto 0);
|
||
|
|
|
||
|
|
inter_vc_write_in(0)(0)(0)(0)(4-1 downto 0) <= local_vc_write_rx(4-1 downto 0);
|
||
|
|
local_vc_write_tx(4-1 downto 0) <= inter_vc_write_out(0)(0)(0)(0)(4-1 downto 0);
|
||
|
|
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
-- Router at x= 0 y=0 z=0
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
router_000: entity work.router_pl
|
||
|
|
generic map (
|
||
|
|
port_num => 4,
|
||
|
|
Xis => 0,
|
||
|
|
Yis => 0,
|
||
|
|
Zis => 0,
|
||
|
|
header_incl_in_packet_length => true,
|
||
|
|
port_exist => (0,1,2,5),
|
||
|
|
vc_num_vec => (4, 4, 4, 4),
|
||
|
|
vc_num_out_vec => (4, 4, 4, 4),
|
||
|
|
vc_depth_array => ((4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4)),
|
||
|
|
vc_depth_out_array => ((4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4)),
|
||
|
|
rout_algo => "DXYU"
|
||
|
|
)
|
||
|
|
port map (
|
||
|
|
clk => clk,
|
||
|
|
rst => rst,
|
||
|
|
data_rx => data_in000,
|
||
|
|
vc_write_rx_vec => vc_write_rx_vec000,
|
||
|
|
incr_rx_vec => incr_rx_vec000,
|
||
|
|
data_tx_pl => data_out000,
|
||
|
|
vc_write_tx_pl_vec => vc_write_tx_pl_vec000,
|
||
|
|
incr_tx_pl_vec => incr_tx_pl_vec000
|
||
|
|
);
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
-- Router port connections to adjacent routers
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
data_in100(0) <= inter_data_in(1)(0)(0)(0);
|
||
|
|
inter_data_out(1)(0)(0)(0) <= data_out100(0) after delay_constant;
|
||
|
|
incr_rx_vec100(4-1 downto 0) <= inter_incr_in(1)(0)(0)(0)(4-1 downto 0);
|
||
|
|
inter_incr_out(1)(0)(0)(0)(4-1 downto 0) <= incr_tx_pl_vec100(4-1 downto 0);
|
||
|
|
vc_write_rx_vec100(4-1 downto 0) <= inter_vc_write_in(1)(0)(0)(0)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(1)(0)(0)(0)(4-1 downto 0) <= vc_write_tx_pl_vec100(4-1 downto 0);
|
||
|
|
data_in100(1) <= inter_data_in(1)(0)(0)(1);
|
||
|
|
inter_data_out(1)(0)(0)(1) <= data_out100(1) after delay_constant;
|
||
|
|
incr_rx_vec100(8-1 downto 4) <= inter_incr_in(1)(0)(0)(1)(4-1 downto 0);
|
||
|
|
inter_incr_out(1)(0)(0)(1)(4-1 downto 0) <= incr_tx_pl_vec100(8-1 downto 4);
|
||
|
|
vc_write_rx_vec100(8-1 downto 4) <= inter_vc_write_in(1)(0)(0)(1)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(1)(0)(0)(1)(4-1 downto 0) <= vc_write_tx_pl_vec100(8-1 downto 4);
|
||
|
|
|
||
|
|
inter_data_in(1)(0)(0)(1) <= inter_data_out(1)(0+1)(0)(3);
|
||
|
|
|
||
|
|
inter_incr_in(1)(0)(0)(1) <= inter_incr_out(1)(0+1)(0)(3);
|
||
|
|
|
||
|
|
inter_vc_write_in(1)(0)(0)(1) <= inter_vc_write_out(1)(0+1)(0)(3);
|
||
|
|
data_in100(2) <= inter_data_in(1)(0)(0)(2);
|
||
|
|
inter_data_out(1)(0)(0)(2) <= data_out100(2) after delay_constant;
|
||
|
|
incr_rx_vec100(12-1 downto 8) <= inter_incr_in(1)(0)(0)(2)(4-1 downto 0);
|
||
|
|
inter_incr_out(1)(0)(0)(2)(4-1 downto 0) <= incr_tx_pl_vec100(12-1 downto 8);
|
||
|
|
vc_write_rx_vec100(12-1 downto 8) <= inter_vc_write_in(1)(0)(0)(2)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(1)(0)(0)(2)(4-1 downto 0) <= vc_write_tx_pl_vec100(12-1 downto 8);
|
||
|
|
|
||
|
|
inter_data_in(1)(0)(0)(2) <= inter_data_out(1+1)(0)(0)(4);
|
||
|
|
|
||
|
|
inter_incr_in(1)(0)(0)(2) <= inter_incr_out(1+1)(0)(0)(4);
|
||
|
|
|
||
|
|
inter_vc_write_in(1)(0)(0)(2) <= inter_vc_write_out(1+1)(0)(0)(4);
|
||
|
|
data_in100(3) <= inter_data_in(1)(0)(0)(4);
|
||
|
|
inter_data_out(1)(0)(0)(4) <= data_out100(3) after delay_constant;
|
||
|
|
incr_rx_vec100(16-1 downto 12) <= inter_incr_in(1)(0)(0)(4)(4-1 downto 0);
|
||
|
|
inter_incr_out(1)(0)(0)(4)(4-1 downto 0) <= incr_tx_pl_vec100(16-1 downto 12);
|
||
|
|
vc_write_rx_vec100(16-1 downto 12) <= inter_vc_write_in(1)(0)(0)(4)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(1)(0)(0)(4)(4-1 downto 0) <= vc_write_tx_pl_vec100(16-1 downto 12);
|
||
|
|
|
||
|
|
inter_data_in(1)(0)(0)(4) <= inter_data_out(1-1)(0)(0)(2);
|
||
|
|
|
||
|
|
inter_incr_in(1)(0)(0)(4) <= inter_incr_out(1-1)(0)(0)(2);
|
||
|
|
|
||
|
|
inter_vc_write_in(1)(0)(0)(4) <= inter_vc_write_out(1-1)(0)(0)(2);
|
||
|
|
data_in100(4) <= inter_data_in(1)(0)(0)(5);
|
||
|
|
inter_data_out(1)(0)(0)(5) <= data_out100(4) after delay_constant;
|
||
|
|
incr_rx_vec100(20-1 downto 16) <= inter_incr_in(1)(0)(0)(5)(4-1 downto 0);
|
||
|
|
inter_incr_out(1)(0)(0)(5)(4-1 downto 0) <= incr_tx_pl_vec100(20-1 downto 16);
|
||
|
|
vc_write_rx_vec100(20-1 downto 16) <= inter_vc_write_in(1)(0)(0)(5)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(1)(0)(0)(5)(4-1 downto 0) <= vc_write_tx_pl_vec100(20-1 downto 16);
|
||
|
|
|
||
|
|
inter_data_in(1)(0)(0)(5) <= inter_data_out(1)(0)(0+1)(6);
|
||
|
|
|
||
|
|
inter_incr_in(1)(0)(0)(5) <= inter_incr_out(1)(0)(0+1)(6);
|
||
|
|
|
||
|
|
inter_vc_write_in(1)(0)(0)(5) <= inter_vc_write_out(1)(0)(0+1)(6);
|
||
|
|
|
||
|
|
inter_data_in(1)(0)(0)(0) <= local_rx(1);
|
||
|
|
local_tx(1) <= inter_data_out(1)(0)(0)(0);
|
||
|
|
|
||
|
|
inter_incr_in(1)(0)(0)(0)(4-1 downto 0) <= local_incr_rx_vec(8-1 downto 4);
|
||
|
|
local_incr_tx_vec(8-1 downto 4) <= inter_incr_out(1)(0)(0)(0)(4-1 downto 0);
|
||
|
|
|
||
|
|
inter_vc_write_in(1)(0)(0)(0)(4-1 downto 0) <= local_vc_write_rx(8-1 downto 4);
|
||
|
|
local_vc_write_tx(8-1 downto 4) <= inter_vc_write_out(1)(0)(0)(0)(4-1 downto 0);
|
||
|
|
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
-- Router at x= 1 y=0 z=0
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
router_100: entity work.router_pl
|
||
|
|
generic map (
|
||
|
|
port_num => 5,
|
||
|
|
Xis => 1,
|
||
|
|
Yis => 0,
|
||
|
|
Zis => 0,
|
||
|
|
header_incl_in_packet_length => true,
|
||
|
|
port_exist => (0,1,2,4,5),
|
||
|
|
vc_num_vec => (4, 4, 4, 4, 4),
|
||
|
|
vc_num_out_vec => (4, 4, 4, 4, 4),
|
||
|
|
vc_depth_array => ((4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4)),
|
||
|
|
vc_depth_out_array => ((4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4)),
|
||
|
|
rout_algo => "DXYU"
|
||
|
|
)
|
||
|
|
port map (
|
||
|
|
clk => clk,
|
||
|
|
rst => rst,
|
||
|
|
data_rx => data_in100,
|
||
|
|
vc_write_rx_vec => vc_write_rx_vec100,
|
||
|
|
incr_rx_vec => incr_rx_vec100,
|
||
|
|
data_tx_pl => data_out100,
|
||
|
|
vc_write_tx_pl_vec => vc_write_tx_pl_vec100,
|
||
|
|
incr_tx_pl_vec => incr_tx_pl_vec100
|
||
|
|
);
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
-- Router port connections to adjacent routers
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
data_in200(0) <= inter_data_in(2)(0)(0)(0);
|
||
|
|
inter_data_out(2)(0)(0)(0) <= data_out200(0) after delay_constant;
|
||
|
|
incr_rx_vec200(4-1 downto 0) <= inter_incr_in(2)(0)(0)(0)(4-1 downto 0);
|
||
|
|
inter_incr_out(2)(0)(0)(0)(4-1 downto 0) <= incr_tx_pl_vec200(4-1 downto 0);
|
||
|
|
vc_write_rx_vec200(4-1 downto 0) <= inter_vc_write_in(2)(0)(0)(0)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(2)(0)(0)(0)(4-1 downto 0) <= vc_write_tx_pl_vec200(4-1 downto 0);
|
||
|
|
data_in200(1) <= inter_data_in(2)(0)(0)(1);
|
||
|
|
inter_data_out(2)(0)(0)(1) <= data_out200(1) after delay_constant;
|
||
|
|
incr_rx_vec200(8-1 downto 4) <= inter_incr_in(2)(0)(0)(1)(4-1 downto 0);
|
||
|
|
inter_incr_out(2)(0)(0)(1)(4-1 downto 0) <= incr_tx_pl_vec200(8-1 downto 4);
|
||
|
|
vc_write_rx_vec200(8-1 downto 4) <= inter_vc_write_in(2)(0)(0)(1)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(2)(0)(0)(1)(4-1 downto 0) <= vc_write_tx_pl_vec200(8-1 downto 4);
|
||
|
|
|
||
|
|
inter_data_in(2)(0)(0)(1) <= inter_data_out(2)(0+1)(0)(3);
|
||
|
|
|
||
|
|
inter_incr_in(2)(0)(0)(1) <= inter_incr_out(2)(0+1)(0)(3);
|
||
|
|
|
||
|
|
inter_vc_write_in(2)(0)(0)(1) <= inter_vc_write_out(2)(0+1)(0)(3);
|
||
|
|
data_in200(2) <= inter_data_in(2)(0)(0)(2);
|
||
|
|
inter_data_out(2)(0)(0)(2) <= data_out200(2) after delay_constant;
|
||
|
|
incr_rx_vec200(12-1 downto 8) <= inter_incr_in(2)(0)(0)(2)(4-1 downto 0);
|
||
|
|
inter_incr_out(2)(0)(0)(2)(4-1 downto 0) <= incr_tx_pl_vec200(12-1 downto 8);
|
||
|
|
vc_write_rx_vec200(12-1 downto 8) <= inter_vc_write_in(2)(0)(0)(2)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(2)(0)(0)(2)(4-1 downto 0) <= vc_write_tx_pl_vec200(12-1 downto 8);
|
||
|
|
|
||
|
|
inter_data_in(2)(0)(0)(2) <= inter_data_out(2+1)(0)(0)(4);
|
||
|
|
|
||
|
|
inter_incr_in(2)(0)(0)(2) <= inter_incr_out(2+1)(0)(0)(4);
|
||
|
|
|
||
|
|
inter_vc_write_in(2)(0)(0)(2) <= inter_vc_write_out(2+1)(0)(0)(4);
|
||
|
|
data_in200(3) <= inter_data_in(2)(0)(0)(4);
|
||
|
|
inter_data_out(2)(0)(0)(4) <= data_out200(3) after delay_constant;
|
||
|
|
incr_rx_vec200(16-1 downto 12) <= inter_incr_in(2)(0)(0)(4)(4-1 downto 0);
|
||
|
|
inter_incr_out(2)(0)(0)(4)(4-1 downto 0) <= incr_tx_pl_vec200(16-1 downto 12);
|
||
|
|
vc_write_rx_vec200(16-1 downto 12) <= inter_vc_write_in(2)(0)(0)(4)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(2)(0)(0)(4)(4-1 downto 0) <= vc_write_tx_pl_vec200(16-1 downto 12);
|
||
|
|
|
||
|
|
inter_data_in(2)(0)(0)(4) <= inter_data_out(2-1)(0)(0)(2);
|
||
|
|
|
||
|
|
inter_incr_in(2)(0)(0)(4) <= inter_incr_out(2-1)(0)(0)(2);
|
||
|
|
|
||
|
|
inter_vc_write_in(2)(0)(0)(4) <= inter_vc_write_out(2-1)(0)(0)(2);
|
||
|
|
data_in200(4) <= inter_data_in(2)(0)(0)(5);
|
||
|
|
inter_data_out(2)(0)(0)(5) <= data_out200(4) after delay_constant;
|
||
|
|
incr_rx_vec200(20-1 downto 16) <= inter_incr_in(2)(0)(0)(5)(4-1 downto 0);
|
||
|
|
inter_incr_out(2)(0)(0)(5)(4-1 downto 0) <= incr_tx_pl_vec200(20-1 downto 16);
|
||
|
|
vc_write_rx_vec200(20-1 downto 16) <= inter_vc_write_in(2)(0)(0)(5)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(2)(0)(0)(5)(4-1 downto 0) <= vc_write_tx_pl_vec200(20-1 downto 16);
|
||
|
|
|
||
|
|
inter_data_in(2)(0)(0)(5) <= inter_data_out(2)(0)(0+1)(6);
|
||
|
|
|
||
|
|
inter_incr_in(2)(0)(0)(5) <= inter_incr_out(2)(0)(0+1)(6);
|
||
|
|
|
||
|
|
inter_vc_write_in(2)(0)(0)(5) <= inter_vc_write_out(2)(0)(0+1)(6);
|
||
|
|
|
||
|
|
inter_data_in(2)(0)(0)(0) <= local_rx(2);
|
||
|
|
local_tx(2) <= inter_data_out(2)(0)(0)(0);
|
||
|
|
|
||
|
|
inter_incr_in(2)(0)(0)(0)(4-1 downto 0) <= local_incr_rx_vec(12-1 downto 8);
|
||
|
|
local_incr_tx_vec(12-1 downto 8) <= inter_incr_out(2)(0)(0)(0)(4-1 downto 0);
|
||
|
|
|
||
|
|
inter_vc_write_in(2)(0)(0)(0)(4-1 downto 0) <= local_vc_write_rx(12-1 downto 8);
|
||
|
|
local_vc_write_tx(12-1 downto 8) <= inter_vc_write_out(2)(0)(0)(0)(4-1 downto 0);
|
||
|
|
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
-- Router at x= 2 y=0 z=0
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
router_200: entity work.router_pl
|
||
|
|
generic map (
|
||
|
|
port_num => 5,
|
||
|
|
Xis => 2,
|
||
|
|
Yis => 0,
|
||
|
|
Zis => 0,
|
||
|
|
header_incl_in_packet_length => true,
|
||
|
|
port_exist => (0,1,2,4,5),
|
||
|
|
vc_num_vec => (4, 4, 4, 4, 4),
|
||
|
|
vc_num_out_vec => (4, 4, 4, 4, 4),
|
||
|
|
vc_depth_array => ((4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4)),
|
||
|
|
vc_depth_out_array => ((4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4)),
|
||
|
|
rout_algo => "DXYU"
|
||
|
|
)
|
||
|
|
port map (
|
||
|
|
clk => clk,
|
||
|
|
rst => rst,
|
||
|
|
data_rx => data_in200,
|
||
|
|
vc_write_rx_vec => vc_write_rx_vec200,
|
||
|
|
incr_rx_vec => incr_rx_vec200,
|
||
|
|
data_tx_pl => data_out200,
|
||
|
|
vc_write_tx_pl_vec => vc_write_tx_pl_vec200,
|
||
|
|
incr_tx_pl_vec => incr_tx_pl_vec200
|
||
|
|
);
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
-- Router port connections to adjacent routers
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
data_in300(0) <= inter_data_in(3)(0)(0)(0);
|
||
|
|
inter_data_out(3)(0)(0)(0) <= data_out300(0) after delay_constant;
|
||
|
|
incr_rx_vec300(4-1 downto 0) <= inter_incr_in(3)(0)(0)(0)(4-1 downto 0);
|
||
|
|
inter_incr_out(3)(0)(0)(0)(4-1 downto 0) <= incr_tx_pl_vec300(4-1 downto 0);
|
||
|
|
vc_write_rx_vec300(4-1 downto 0) <= inter_vc_write_in(3)(0)(0)(0)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(3)(0)(0)(0)(4-1 downto 0) <= vc_write_tx_pl_vec300(4-1 downto 0);
|
||
|
|
data_in300(1) <= inter_data_in(3)(0)(0)(1);
|
||
|
|
inter_data_out(3)(0)(0)(1) <= data_out300(1) after delay_constant;
|
||
|
|
incr_rx_vec300(8-1 downto 4) <= inter_incr_in(3)(0)(0)(1)(4-1 downto 0);
|
||
|
|
inter_incr_out(3)(0)(0)(1)(4-1 downto 0) <= incr_tx_pl_vec300(8-1 downto 4);
|
||
|
|
vc_write_rx_vec300(8-1 downto 4) <= inter_vc_write_in(3)(0)(0)(1)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(3)(0)(0)(1)(4-1 downto 0) <= vc_write_tx_pl_vec300(8-1 downto 4);
|
||
|
|
|
||
|
|
inter_data_in(3)(0)(0)(1) <= inter_data_out(3)(0+1)(0)(3);
|
||
|
|
|
||
|
|
inter_incr_in(3)(0)(0)(1) <= inter_incr_out(3)(0+1)(0)(3);
|
||
|
|
|
||
|
|
inter_vc_write_in(3)(0)(0)(1) <= inter_vc_write_out(3)(0+1)(0)(3);
|
||
|
|
data_in300(2) <= inter_data_in(3)(0)(0)(4);
|
||
|
|
inter_data_out(3)(0)(0)(4) <= data_out300(2) after delay_constant;
|
||
|
|
incr_rx_vec300(12-1 downto 8) <= inter_incr_in(3)(0)(0)(4)(4-1 downto 0);
|
||
|
|
inter_incr_out(3)(0)(0)(4)(4-1 downto 0) <= incr_tx_pl_vec300(12-1 downto 8);
|
||
|
|
vc_write_rx_vec300(12-1 downto 8) <= inter_vc_write_in(3)(0)(0)(4)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(3)(0)(0)(4)(4-1 downto 0) <= vc_write_tx_pl_vec300(12-1 downto 8);
|
||
|
|
|
||
|
|
inter_data_in(3)(0)(0)(4) <= inter_data_out(3-1)(0)(0)(2);
|
||
|
|
|
||
|
|
inter_incr_in(3)(0)(0)(4) <= inter_incr_out(3-1)(0)(0)(2);
|
||
|
|
|
||
|
|
inter_vc_write_in(3)(0)(0)(4) <= inter_vc_write_out(3-1)(0)(0)(2);
|
||
|
|
data_in300(3) <= inter_data_in(3)(0)(0)(5);
|
||
|
|
inter_data_out(3)(0)(0)(5) <= data_out300(3) after delay_constant;
|
||
|
|
incr_rx_vec300(16-1 downto 12) <= inter_incr_in(3)(0)(0)(5)(4-1 downto 0);
|
||
|
|
inter_incr_out(3)(0)(0)(5)(4-1 downto 0) <= incr_tx_pl_vec300(16-1 downto 12);
|
||
|
|
vc_write_rx_vec300(16-1 downto 12) <= inter_vc_write_in(3)(0)(0)(5)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(3)(0)(0)(5)(4-1 downto 0) <= vc_write_tx_pl_vec300(16-1 downto 12);
|
||
|
|
|
||
|
|
inter_data_in(3)(0)(0)(5) <= inter_data_out(3)(0)(0+1)(6);
|
||
|
|
|
||
|
|
inter_incr_in(3)(0)(0)(5) <= inter_incr_out(3)(0)(0+1)(6);
|
||
|
|
|
||
|
|
inter_vc_write_in(3)(0)(0)(5) <= inter_vc_write_out(3)(0)(0+1)(6);
|
||
|
|
|
||
|
|
inter_data_in(3)(0)(0)(0) <= local_rx(3);
|
||
|
|
local_tx(3) <= inter_data_out(3)(0)(0)(0);
|
||
|
|
|
||
|
|
inter_incr_in(3)(0)(0)(0)(4-1 downto 0) <= local_incr_rx_vec(16-1 downto 12);
|
||
|
|
local_incr_tx_vec(16-1 downto 12) <= inter_incr_out(3)(0)(0)(0)(4-1 downto 0);
|
||
|
|
|
||
|
|
inter_vc_write_in(3)(0)(0)(0)(4-1 downto 0) <= local_vc_write_rx(16-1 downto 12);
|
||
|
|
local_vc_write_tx(16-1 downto 12) <= inter_vc_write_out(3)(0)(0)(0)(4-1 downto 0);
|
||
|
|
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
-- Router at x= 3 y=0 z=0
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
router_300: entity work.router_pl
|
||
|
|
generic map (
|
||
|
|
port_num => 4,
|
||
|
|
Xis => 3,
|
||
|
|
Yis => 0,
|
||
|
|
Zis => 0,
|
||
|
|
header_incl_in_packet_length => true,
|
||
|
|
port_exist => (0,1,4,5),
|
||
|
|
vc_num_vec => (4, 4, 4, 4),
|
||
|
|
vc_num_out_vec => (4, 4, 4, 4),
|
||
|
|
vc_depth_array => ((4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4)),
|
||
|
|
vc_depth_out_array => ((4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4)),
|
||
|
|
rout_algo => "DXYU"
|
||
|
|
)
|
||
|
|
port map (
|
||
|
|
clk => clk,
|
||
|
|
rst => rst,
|
||
|
|
data_rx => data_in300,
|
||
|
|
vc_write_rx_vec => vc_write_rx_vec300,
|
||
|
|
incr_rx_vec => incr_rx_vec300,
|
||
|
|
data_tx_pl => data_out300,
|
||
|
|
vc_write_tx_pl_vec => vc_write_tx_pl_vec300,
|
||
|
|
incr_tx_pl_vec => incr_tx_pl_vec300
|
||
|
|
);
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
-- Router port connections to adjacent routers
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
data_in010(0) <= inter_data_in(0)(1)(0)(0);
|
||
|
|
inter_data_out(0)(1)(0)(0) <= data_out010(0) after delay_constant;
|
||
|
|
incr_rx_vec010(4-1 downto 0) <= inter_incr_in(0)(1)(0)(0)(4-1 downto 0);
|
||
|
|
inter_incr_out(0)(1)(0)(0)(4-1 downto 0) <= incr_tx_pl_vec010(4-1 downto 0);
|
||
|
|
vc_write_rx_vec010(4-1 downto 0) <= inter_vc_write_in(0)(1)(0)(0)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(0)(1)(0)(0)(4-1 downto 0) <= vc_write_tx_pl_vec010(4-1 downto 0);
|
||
|
|
data_in010(1) <= inter_data_in(0)(1)(0)(1);
|
||
|
|
inter_data_out(0)(1)(0)(1) <= data_out010(1) after delay_constant;
|
||
|
|
incr_rx_vec010(8-1 downto 4) <= inter_incr_in(0)(1)(0)(1)(4-1 downto 0);
|
||
|
|
inter_incr_out(0)(1)(0)(1)(4-1 downto 0) <= incr_tx_pl_vec010(8-1 downto 4);
|
||
|
|
vc_write_rx_vec010(8-1 downto 4) <= inter_vc_write_in(0)(1)(0)(1)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(0)(1)(0)(1)(4-1 downto 0) <= vc_write_tx_pl_vec010(8-1 downto 4);
|
||
|
|
|
||
|
|
inter_data_in(0)(1)(0)(1) <= inter_data_out(0)(1+1)(0)(3);
|
||
|
|
|
||
|
|
inter_incr_in(0)(1)(0)(1) <= inter_incr_out(0)(1+1)(0)(3);
|
||
|
|
|
||
|
|
inter_vc_write_in(0)(1)(0)(1) <= inter_vc_write_out(0)(1+1)(0)(3);
|
||
|
|
data_in010(2) <= inter_data_in(0)(1)(0)(2);
|
||
|
|
inter_data_out(0)(1)(0)(2) <= data_out010(2) after delay_constant;
|
||
|
|
incr_rx_vec010(12-1 downto 8) <= inter_incr_in(0)(1)(0)(2)(4-1 downto 0);
|
||
|
|
inter_incr_out(0)(1)(0)(2)(4-1 downto 0) <= incr_tx_pl_vec010(12-1 downto 8);
|
||
|
|
vc_write_rx_vec010(12-1 downto 8) <= inter_vc_write_in(0)(1)(0)(2)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(0)(1)(0)(2)(4-1 downto 0) <= vc_write_tx_pl_vec010(12-1 downto 8);
|
||
|
|
|
||
|
|
inter_data_in(0)(1)(0)(2) <= inter_data_out(0+1)(1)(0)(4);
|
||
|
|
|
||
|
|
inter_incr_in(0)(1)(0)(2) <= inter_incr_out(0+1)(1)(0)(4);
|
||
|
|
|
||
|
|
inter_vc_write_in(0)(1)(0)(2) <= inter_vc_write_out(0+1)(1)(0)(4);
|
||
|
|
data_in010(3) <= inter_data_in(0)(1)(0)(3);
|
||
|
|
inter_data_out(0)(1)(0)(3) <= data_out010(3) after delay_constant;
|
||
|
|
incr_rx_vec010(16-1 downto 12) <= inter_incr_in(0)(1)(0)(3)(4-1 downto 0);
|
||
|
|
inter_incr_out(0)(1)(0)(3)(4-1 downto 0) <= incr_tx_pl_vec010(16-1 downto 12);
|
||
|
|
vc_write_rx_vec010(16-1 downto 12) <= inter_vc_write_in(0)(1)(0)(3)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(0)(1)(0)(3)(4-1 downto 0) <= vc_write_tx_pl_vec010(16-1 downto 12);
|
||
|
|
|
||
|
|
inter_data_in(0)(1)(0)(3) <= inter_data_out(0)(1-1)(0)(1);
|
||
|
|
|
||
|
|
inter_incr_in(0)(1)(0)(3) <= inter_incr_out(0)(1-1)(0)(1);
|
||
|
|
|
||
|
|
inter_vc_write_in(0)(1)(0)(3) <= inter_vc_write_out(0)(1-1)(0)(1);
|
||
|
|
data_in010(4) <= inter_data_in(0)(1)(0)(5);
|
||
|
|
inter_data_out(0)(1)(0)(5) <= data_out010(4) after delay_constant;
|
||
|
|
incr_rx_vec010(20-1 downto 16) <= inter_incr_in(0)(1)(0)(5)(4-1 downto 0);
|
||
|
|
inter_incr_out(0)(1)(0)(5)(4-1 downto 0) <= incr_tx_pl_vec010(20-1 downto 16);
|
||
|
|
vc_write_rx_vec010(20-1 downto 16) <= inter_vc_write_in(0)(1)(0)(5)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(0)(1)(0)(5)(4-1 downto 0) <= vc_write_tx_pl_vec010(20-1 downto 16);
|
||
|
|
|
||
|
|
inter_data_in(0)(1)(0)(5) <= inter_data_out(0)(1)(0+1)(6);
|
||
|
|
|
||
|
|
inter_incr_in(0)(1)(0)(5) <= inter_incr_out(0)(1)(0+1)(6);
|
||
|
|
|
||
|
|
inter_vc_write_in(0)(1)(0)(5) <= inter_vc_write_out(0)(1)(0+1)(6);
|
||
|
|
|
||
|
|
inter_data_in(0)(1)(0)(0) <= local_rx(4);
|
||
|
|
local_tx(4) <= inter_data_out(0)(1)(0)(0);
|
||
|
|
|
||
|
|
inter_incr_in(0)(1)(0)(0)(4-1 downto 0) <= local_incr_rx_vec(20-1 downto 16);
|
||
|
|
local_incr_tx_vec(20-1 downto 16) <= inter_incr_out(0)(1)(0)(0)(4-1 downto 0);
|
||
|
|
|
||
|
|
inter_vc_write_in(0)(1)(0)(0)(4-1 downto 0) <= local_vc_write_rx(20-1 downto 16);
|
||
|
|
local_vc_write_tx(20-1 downto 16) <= inter_vc_write_out(0)(1)(0)(0)(4-1 downto 0);
|
||
|
|
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
-- Router at x= 0 y=1 z=0
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
router_010: entity work.router_pl
|
||
|
|
generic map (
|
||
|
|
port_num => 5,
|
||
|
|
Xis => 0,
|
||
|
|
Yis => 1,
|
||
|
|
Zis => 0,
|
||
|
|
header_incl_in_packet_length => true,
|
||
|
|
port_exist => (0,1,2,3,5),
|
||
|
|
vc_num_vec => (4, 4, 4, 4, 4),
|
||
|
|
vc_num_out_vec => (4, 4, 4, 4, 4),
|
||
|
|
vc_depth_array => ((4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4)),
|
||
|
|
vc_depth_out_array => ((4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4)),
|
||
|
|
rout_algo => "DXYU"
|
||
|
|
)
|
||
|
|
port map (
|
||
|
|
clk => clk,
|
||
|
|
rst => rst,
|
||
|
|
data_rx => data_in010,
|
||
|
|
vc_write_rx_vec => vc_write_rx_vec010,
|
||
|
|
incr_rx_vec => incr_rx_vec010,
|
||
|
|
data_tx_pl => data_out010,
|
||
|
|
vc_write_tx_pl_vec => vc_write_tx_pl_vec010,
|
||
|
|
incr_tx_pl_vec => incr_tx_pl_vec010
|
||
|
|
);
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
-- Router port connections to adjacent routers
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
data_in110(0) <= inter_data_in(1)(1)(0)(0);
|
||
|
|
inter_data_out(1)(1)(0)(0) <= data_out110(0) after delay_constant;
|
||
|
|
incr_rx_vec110(4-1 downto 0) <= inter_incr_in(1)(1)(0)(0)(4-1 downto 0);
|
||
|
|
inter_incr_out(1)(1)(0)(0)(4-1 downto 0) <= incr_tx_pl_vec110(4-1 downto 0);
|
||
|
|
vc_write_rx_vec110(4-1 downto 0) <= inter_vc_write_in(1)(1)(0)(0)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(1)(1)(0)(0)(4-1 downto 0) <= vc_write_tx_pl_vec110(4-1 downto 0);
|
||
|
|
data_in110(1) <= inter_data_in(1)(1)(0)(1);
|
||
|
|
inter_data_out(1)(1)(0)(1) <= data_out110(1) after delay_constant;
|
||
|
|
incr_rx_vec110(8-1 downto 4) <= inter_incr_in(1)(1)(0)(1)(4-1 downto 0);
|
||
|
|
inter_incr_out(1)(1)(0)(1)(4-1 downto 0) <= incr_tx_pl_vec110(8-1 downto 4);
|
||
|
|
vc_write_rx_vec110(8-1 downto 4) <= inter_vc_write_in(1)(1)(0)(1)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(1)(1)(0)(1)(4-1 downto 0) <= vc_write_tx_pl_vec110(8-1 downto 4);
|
||
|
|
|
||
|
|
inter_data_in(1)(1)(0)(1) <= inter_data_out(1)(1+1)(0)(3);
|
||
|
|
|
||
|
|
inter_incr_in(1)(1)(0)(1) <= inter_incr_out(1)(1+1)(0)(3);
|
||
|
|
|
||
|
|
inter_vc_write_in(1)(1)(0)(1) <= inter_vc_write_out(1)(1+1)(0)(3);
|
||
|
|
data_in110(2) <= inter_data_in(1)(1)(0)(2);
|
||
|
|
inter_data_out(1)(1)(0)(2) <= data_out110(2) after delay_constant;
|
||
|
|
incr_rx_vec110(12-1 downto 8) <= inter_incr_in(1)(1)(0)(2)(4-1 downto 0);
|
||
|
|
inter_incr_out(1)(1)(0)(2)(4-1 downto 0) <= incr_tx_pl_vec110(12-1 downto 8);
|
||
|
|
vc_write_rx_vec110(12-1 downto 8) <= inter_vc_write_in(1)(1)(0)(2)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(1)(1)(0)(2)(4-1 downto 0) <= vc_write_tx_pl_vec110(12-1 downto 8);
|
||
|
|
|
||
|
|
inter_data_in(1)(1)(0)(2) <= inter_data_out(1+1)(1)(0)(4);
|
||
|
|
|
||
|
|
inter_incr_in(1)(1)(0)(2) <= inter_incr_out(1+1)(1)(0)(4);
|
||
|
|
|
||
|
|
inter_vc_write_in(1)(1)(0)(2) <= inter_vc_write_out(1+1)(1)(0)(4);
|
||
|
|
data_in110(3) <= inter_data_in(1)(1)(0)(3);
|
||
|
|
inter_data_out(1)(1)(0)(3) <= data_out110(3) after delay_constant;
|
||
|
|
incr_rx_vec110(16-1 downto 12) <= inter_incr_in(1)(1)(0)(3)(4-1 downto 0);
|
||
|
|
inter_incr_out(1)(1)(0)(3)(4-1 downto 0) <= incr_tx_pl_vec110(16-1 downto 12);
|
||
|
|
vc_write_rx_vec110(16-1 downto 12) <= inter_vc_write_in(1)(1)(0)(3)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(1)(1)(0)(3)(4-1 downto 0) <= vc_write_tx_pl_vec110(16-1 downto 12);
|
||
|
|
|
||
|
|
inter_data_in(1)(1)(0)(3) <= inter_data_out(1)(1-1)(0)(1);
|
||
|
|
|
||
|
|
inter_incr_in(1)(1)(0)(3) <= inter_incr_out(1)(1-1)(0)(1);
|
||
|
|
|
||
|
|
inter_vc_write_in(1)(1)(0)(3) <= inter_vc_write_out(1)(1-1)(0)(1);
|
||
|
|
data_in110(4) <= inter_data_in(1)(1)(0)(4);
|
||
|
|
inter_data_out(1)(1)(0)(4) <= data_out110(4) after delay_constant;
|
||
|
|
incr_rx_vec110(20-1 downto 16) <= inter_incr_in(1)(1)(0)(4)(4-1 downto 0);
|
||
|
|
inter_incr_out(1)(1)(0)(4)(4-1 downto 0) <= incr_tx_pl_vec110(20-1 downto 16);
|
||
|
|
vc_write_rx_vec110(20-1 downto 16) <= inter_vc_write_in(1)(1)(0)(4)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(1)(1)(0)(4)(4-1 downto 0) <= vc_write_tx_pl_vec110(20-1 downto 16);
|
||
|
|
|
||
|
|
inter_data_in(1)(1)(0)(4) <= inter_data_out(1-1)(1)(0)(2);
|
||
|
|
|
||
|
|
inter_incr_in(1)(1)(0)(4) <= inter_incr_out(1-1)(1)(0)(2);
|
||
|
|
|
||
|
|
inter_vc_write_in(1)(1)(0)(4) <= inter_vc_write_out(1-1)(1)(0)(2);
|
||
|
|
data_in110(5) <= inter_data_in(1)(1)(0)(5);
|
||
|
|
inter_data_out(1)(1)(0)(5) <= data_out110(5) after delay_constant;
|
||
|
|
incr_rx_vec110(24-1 downto 20) <= inter_incr_in(1)(1)(0)(5)(4-1 downto 0);
|
||
|
|
inter_incr_out(1)(1)(0)(5)(4-1 downto 0) <= incr_tx_pl_vec110(24-1 downto 20);
|
||
|
|
vc_write_rx_vec110(24-1 downto 20) <= inter_vc_write_in(1)(1)(0)(5)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(1)(1)(0)(5)(4-1 downto 0) <= vc_write_tx_pl_vec110(24-1 downto 20);
|
||
|
|
|
||
|
|
inter_data_in(1)(1)(0)(5) <= inter_data_out(1)(1)(0+1)(6);
|
||
|
|
|
||
|
|
inter_incr_in(1)(1)(0)(5) <= inter_incr_out(1)(1)(0+1)(6);
|
||
|
|
|
||
|
|
inter_vc_write_in(1)(1)(0)(5) <= inter_vc_write_out(1)(1)(0+1)(6);
|
||
|
|
|
||
|
|
inter_data_in(1)(1)(0)(0) <= local_rx(5);
|
||
|
|
local_tx(5) <= inter_data_out(1)(1)(0)(0);
|
||
|
|
|
||
|
|
inter_incr_in(1)(1)(0)(0)(4-1 downto 0) <= local_incr_rx_vec(24-1 downto 20);
|
||
|
|
local_incr_tx_vec(24-1 downto 20) <= inter_incr_out(1)(1)(0)(0)(4-1 downto 0);
|
||
|
|
|
||
|
|
inter_vc_write_in(1)(1)(0)(0)(4-1 downto 0) <= local_vc_write_rx(24-1 downto 20);
|
||
|
|
local_vc_write_tx(24-1 downto 20) <= inter_vc_write_out(1)(1)(0)(0)(4-1 downto 0);
|
||
|
|
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
-- Router at x= 1 y=1 z=0 From Verilog code in gate folder
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
router_110: entity work.router_pl --work.router_fast_110
|
||
|
|
generic map (
|
||
|
|
port_num => 6,
|
||
|
|
Xis => 1,
|
||
|
|
Yis => 1,
|
||
|
|
Zis => 0,
|
||
|
|
header_incl_in_packet_length => true,
|
||
|
|
port_exist => (0,1,2,3,4,5),
|
||
|
|
vc_num_vec => (4, 4, 4, 4, 4, 4),
|
||
|
|
vc_num_out_vec => (4, 4, 4, 4, 4, 4),
|
||
|
|
vc_depth_array => ((4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4)),
|
||
|
|
vc_depth_out_array => ((4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4)),
|
||
|
|
rout_algo => "DXYU"
|
||
|
|
)
|
||
|
|
port map (
|
||
|
|
clk => clk,
|
||
|
|
rst => rst,
|
||
|
|
data_rx => data_in110, --data_rx110,
|
||
|
|
vc_write_rx_vec => vc_write_rx_vec110,
|
||
|
|
incr_rx_vec => incr_rx_vec110,
|
||
|
|
data_tx_pl => data_out110, --data_tx110,
|
||
|
|
vc_write_tx_pl_vec => vc_write_tx_pl_vec110,
|
||
|
|
incr_tx_pl_vec => incr_tx_pl_vec110
|
||
|
|
);
|
||
|
|
|
||
|
|
--data_in_gen: for i in 0 to 5 generate
|
||
|
|
-- data_rx110((i+1)*flit_size-1 downto i*flit_size) <= data_in110(i);
|
||
|
|
-- data_out110(i) <= data_tx110((i+1)*flit_size-1 downto i*flit_size);
|
||
|
|
--end generate;
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
-- Router port connections to adjacent routers
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
data_in210(0) <= inter_data_in(2)(1)(0)(0);
|
||
|
|
inter_data_out(2)(1)(0)(0) <= data_out210(0) after delay_constant;
|
||
|
|
incr_rx_vec210(4-1 downto 0) <= inter_incr_in(2)(1)(0)(0)(4-1 downto 0);
|
||
|
|
inter_incr_out(2)(1)(0)(0)(4-1 downto 0) <= incr_tx_pl_vec210(4-1 downto 0);
|
||
|
|
vc_write_rx_vec210(4-1 downto 0) <= inter_vc_write_in(2)(1)(0)(0)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(2)(1)(0)(0)(4-1 downto 0) <= vc_write_tx_pl_vec210(4-1 downto 0);
|
||
|
|
data_in210(1) <= inter_data_in(2)(1)(0)(1);
|
||
|
|
inter_data_out(2)(1)(0)(1) <= data_out210(1) after delay_constant;
|
||
|
|
incr_rx_vec210(8-1 downto 4) <= inter_incr_in(2)(1)(0)(1)(4-1 downto 0);
|
||
|
|
inter_incr_out(2)(1)(0)(1)(4-1 downto 0) <= incr_tx_pl_vec210(8-1 downto 4);
|
||
|
|
vc_write_rx_vec210(8-1 downto 4) <= inter_vc_write_in(2)(1)(0)(1)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(2)(1)(0)(1)(4-1 downto 0) <= vc_write_tx_pl_vec210(8-1 downto 4);
|
||
|
|
|
||
|
|
inter_data_in(2)(1)(0)(1) <= inter_data_out(2)(1+1)(0)(3);
|
||
|
|
|
||
|
|
inter_incr_in(2)(1)(0)(1) <= inter_incr_out(2)(1+1)(0)(3);
|
||
|
|
|
||
|
|
inter_vc_write_in(2)(1)(0)(1) <= inter_vc_write_out(2)(1+1)(0)(3);
|
||
|
|
data_in210(2) <= inter_data_in(2)(1)(0)(2);
|
||
|
|
inter_data_out(2)(1)(0)(2) <= data_out210(2) after delay_constant;
|
||
|
|
incr_rx_vec210(12-1 downto 8) <= inter_incr_in(2)(1)(0)(2)(4-1 downto 0);
|
||
|
|
inter_incr_out(2)(1)(0)(2)(4-1 downto 0) <= incr_tx_pl_vec210(12-1 downto 8);
|
||
|
|
vc_write_rx_vec210(12-1 downto 8) <= inter_vc_write_in(2)(1)(0)(2)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(2)(1)(0)(2)(4-1 downto 0) <= vc_write_tx_pl_vec210(12-1 downto 8);
|
||
|
|
|
||
|
|
inter_data_in(2)(1)(0)(2) <= inter_data_out(2+1)(1)(0)(4);
|
||
|
|
|
||
|
|
inter_incr_in(2)(1)(0)(2) <= inter_incr_out(2+1)(1)(0)(4);
|
||
|
|
|
||
|
|
inter_vc_write_in(2)(1)(0)(2) <= inter_vc_write_out(2+1)(1)(0)(4);
|
||
|
|
data_in210(3) <= inter_data_in(2)(1)(0)(3);
|
||
|
|
inter_data_out(2)(1)(0)(3) <= data_out210(3) after delay_constant;
|
||
|
|
incr_rx_vec210(16-1 downto 12) <= inter_incr_in(2)(1)(0)(3)(4-1 downto 0);
|
||
|
|
inter_incr_out(2)(1)(0)(3)(4-1 downto 0) <= incr_tx_pl_vec210(16-1 downto 12);
|
||
|
|
vc_write_rx_vec210(16-1 downto 12) <= inter_vc_write_in(2)(1)(0)(3)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(2)(1)(0)(3)(4-1 downto 0) <= vc_write_tx_pl_vec210(16-1 downto 12);
|
||
|
|
|
||
|
|
inter_data_in(2)(1)(0)(3) <= inter_data_out(2)(1-1)(0)(1);
|
||
|
|
|
||
|
|
inter_incr_in(2)(1)(0)(3) <= inter_incr_out(2)(1-1)(0)(1);
|
||
|
|
|
||
|
|
inter_vc_write_in(2)(1)(0)(3) <= inter_vc_write_out(2)(1-1)(0)(1);
|
||
|
|
data_in210(4) <= inter_data_in(2)(1)(0)(4);
|
||
|
|
inter_data_out(2)(1)(0)(4) <= data_out210(4) after delay_constant;
|
||
|
|
incr_rx_vec210(20-1 downto 16) <= inter_incr_in(2)(1)(0)(4)(4-1 downto 0);
|
||
|
|
inter_incr_out(2)(1)(0)(4)(4-1 downto 0) <= incr_tx_pl_vec210(20-1 downto 16);
|
||
|
|
vc_write_rx_vec210(20-1 downto 16) <= inter_vc_write_in(2)(1)(0)(4)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(2)(1)(0)(4)(4-1 downto 0) <= vc_write_tx_pl_vec210(20-1 downto 16);
|
||
|
|
|
||
|
|
inter_data_in(2)(1)(0)(4) <= inter_data_out(2-1)(1)(0)(2);
|
||
|
|
|
||
|
|
inter_incr_in(2)(1)(0)(4) <= inter_incr_out(2-1)(1)(0)(2);
|
||
|
|
|
||
|
|
inter_vc_write_in(2)(1)(0)(4) <= inter_vc_write_out(2-1)(1)(0)(2);
|
||
|
|
data_in210(5) <= inter_data_in(2)(1)(0)(5);
|
||
|
|
inter_data_out(2)(1)(0)(5) <= data_out210(5) after delay_constant;
|
||
|
|
incr_rx_vec210(24-1 downto 20) <= inter_incr_in(2)(1)(0)(5)(4-1 downto 0);
|
||
|
|
inter_incr_out(2)(1)(0)(5)(4-1 downto 0) <= incr_tx_pl_vec210(24-1 downto 20);
|
||
|
|
vc_write_rx_vec210(24-1 downto 20) <= inter_vc_write_in(2)(1)(0)(5)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(2)(1)(0)(5)(4-1 downto 0) <= vc_write_tx_pl_vec210(24-1 downto 20);
|
||
|
|
|
||
|
|
inter_data_in(2)(1)(0)(5) <= inter_data_out(2)(1)(0+1)(6);
|
||
|
|
|
||
|
|
inter_incr_in(2)(1)(0)(5) <= inter_incr_out(2)(1)(0+1)(6);
|
||
|
|
|
||
|
|
inter_vc_write_in(2)(1)(0)(5) <= inter_vc_write_out(2)(1)(0+1)(6);
|
||
|
|
|
||
|
|
inter_data_in(2)(1)(0)(0) <= local_rx(6);
|
||
|
|
local_tx(6) <= inter_data_out(2)(1)(0)(0);
|
||
|
|
|
||
|
|
inter_incr_in(2)(1)(0)(0)(4-1 downto 0) <= local_incr_rx_vec(28-1 downto 24);
|
||
|
|
local_incr_tx_vec(28-1 downto 24) <= inter_incr_out(2)(1)(0)(0)(4-1 downto 0);
|
||
|
|
|
||
|
|
inter_vc_write_in(2)(1)(0)(0)(4-1 downto 0) <= local_vc_write_rx(28-1 downto 24);
|
||
|
|
local_vc_write_tx(28-1 downto 24) <= inter_vc_write_out(2)(1)(0)(0)(4-1 downto 0);
|
||
|
|
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
-- Router at x= 2 y=1 z=0
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
router_210: entity work.router_pl
|
||
|
|
generic map (
|
||
|
|
port_num => 6,
|
||
|
|
Xis => 2,
|
||
|
|
Yis => 1,
|
||
|
|
Zis => 0,
|
||
|
|
header_incl_in_packet_length => true,
|
||
|
|
port_exist => (0,1,2,3,4,5),
|
||
|
|
vc_num_vec => (4, 4, 4, 4, 4, 4),
|
||
|
|
vc_num_out_vec => (4, 4, 4, 4, 4, 4),
|
||
|
|
vc_depth_array => ((4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4)),
|
||
|
|
vc_depth_out_array => ((4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4)),
|
||
|
|
rout_algo => "DXYU"
|
||
|
|
)
|
||
|
|
port map (
|
||
|
|
clk => clk,
|
||
|
|
rst => rst,
|
||
|
|
data_rx => data_in210,
|
||
|
|
vc_write_rx_vec => vc_write_rx_vec210,
|
||
|
|
incr_rx_vec => incr_rx_vec210,
|
||
|
|
data_tx_pl => data_out210,
|
||
|
|
vc_write_tx_pl_vec => vc_write_tx_pl_vec210,
|
||
|
|
incr_tx_pl_vec => incr_tx_pl_vec210
|
||
|
|
);
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
-- Router port connections to adjacent routers
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
data_in310(0) <= inter_data_in(3)(1)(0)(0);
|
||
|
|
inter_data_out(3)(1)(0)(0) <= data_out310(0) after delay_constant;
|
||
|
|
incr_rx_vec310(4-1 downto 0) <= inter_incr_in(3)(1)(0)(0)(4-1 downto 0);
|
||
|
|
inter_incr_out(3)(1)(0)(0)(4-1 downto 0) <= incr_tx_pl_vec310(4-1 downto 0);
|
||
|
|
vc_write_rx_vec310(4-1 downto 0) <= inter_vc_write_in(3)(1)(0)(0)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(3)(1)(0)(0)(4-1 downto 0) <= vc_write_tx_pl_vec310(4-1 downto 0);
|
||
|
|
data_in310(1) <= inter_data_in(3)(1)(0)(1);
|
||
|
|
inter_data_out(3)(1)(0)(1) <= data_out310(1) after delay_constant;
|
||
|
|
incr_rx_vec310(8-1 downto 4) <= inter_incr_in(3)(1)(0)(1)(4-1 downto 0);
|
||
|
|
inter_incr_out(3)(1)(0)(1)(4-1 downto 0) <= incr_tx_pl_vec310(8-1 downto 4);
|
||
|
|
vc_write_rx_vec310(8-1 downto 4) <= inter_vc_write_in(3)(1)(0)(1)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(3)(1)(0)(1)(4-1 downto 0) <= vc_write_tx_pl_vec310(8-1 downto 4);
|
||
|
|
|
||
|
|
inter_data_in(3)(1)(0)(1) <= inter_data_out(3)(1+1)(0)(3);
|
||
|
|
|
||
|
|
inter_incr_in(3)(1)(0)(1) <= inter_incr_out(3)(1+1)(0)(3);
|
||
|
|
|
||
|
|
inter_vc_write_in(3)(1)(0)(1) <= inter_vc_write_out(3)(1+1)(0)(3);
|
||
|
|
data_in310(2) <= inter_data_in(3)(1)(0)(3);
|
||
|
|
inter_data_out(3)(1)(0)(3) <= data_out310(2) after delay_constant;
|
||
|
|
incr_rx_vec310(12-1 downto 8) <= inter_incr_in(3)(1)(0)(3)(4-1 downto 0);
|
||
|
|
inter_incr_out(3)(1)(0)(3)(4-1 downto 0) <= incr_tx_pl_vec310(12-1 downto 8);
|
||
|
|
vc_write_rx_vec310(12-1 downto 8) <= inter_vc_write_in(3)(1)(0)(3)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(3)(1)(0)(3)(4-1 downto 0) <= vc_write_tx_pl_vec310(12-1 downto 8);
|
||
|
|
|
||
|
|
inter_data_in(3)(1)(0)(3) <= inter_data_out(3)(1-1)(0)(1);
|
||
|
|
|
||
|
|
inter_incr_in(3)(1)(0)(3) <= inter_incr_out(3)(1-1)(0)(1);
|
||
|
|
|
||
|
|
inter_vc_write_in(3)(1)(0)(3) <= inter_vc_write_out(3)(1-1)(0)(1);
|
||
|
|
data_in310(3) <= inter_data_in(3)(1)(0)(4);
|
||
|
|
inter_data_out(3)(1)(0)(4) <= data_out310(3) after delay_constant;
|
||
|
|
incr_rx_vec310(16-1 downto 12) <= inter_incr_in(3)(1)(0)(4)(4-1 downto 0);
|
||
|
|
inter_incr_out(3)(1)(0)(4)(4-1 downto 0) <= incr_tx_pl_vec310(16-1 downto 12);
|
||
|
|
vc_write_rx_vec310(16-1 downto 12) <= inter_vc_write_in(3)(1)(0)(4)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(3)(1)(0)(4)(4-1 downto 0) <= vc_write_tx_pl_vec310(16-1 downto 12);
|
||
|
|
|
||
|
|
inter_data_in(3)(1)(0)(4) <= inter_data_out(3-1)(1)(0)(2);
|
||
|
|
|
||
|
|
inter_incr_in(3)(1)(0)(4) <= inter_incr_out(3-1)(1)(0)(2);
|
||
|
|
|
||
|
|
inter_vc_write_in(3)(1)(0)(4) <= inter_vc_write_out(3-1)(1)(0)(2);
|
||
|
|
data_in310(4) <= inter_data_in(3)(1)(0)(5);
|
||
|
|
inter_data_out(3)(1)(0)(5) <= data_out310(4) after delay_constant;
|
||
|
|
incr_rx_vec310(20-1 downto 16) <= inter_incr_in(3)(1)(0)(5)(4-1 downto 0);
|
||
|
|
inter_incr_out(3)(1)(0)(5)(4-1 downto 0) <= incr_tx_pl_vec310(20-1 downto 16);
|
||
|
|
vc_write_rx_vec310(20-1 downto 16) <= inter_vc_write_in(3)(1)(0)(5)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(3)(1)(0)(5)(4-1 downto 0) <= vc_write_tx_pl_vec310(20-1 downto 16);
|
||
|
|
|
||
|
|
inter_data_in(3)(1)(0)(5) <= inter_data_out(3)(1)(0+1)(6);
|
||
|
|
|
||
|
|
inter_incr_in(3)(1)(0)(5) <= inter_incr_out(3)(1)(0+1)(6);
|
||
|
|
|
||
|
|
inter_vc_write_in(3)(1)(0)(5) <= inter_vc_write_out(3)(1)(0+1)(6);
|
||
|
|
|
||
|
|
inter_data_in(3)(1)(0)(0) <= local_rx(7);
|
||
|
|
local_tx(7) <= inter_data_out(3)(1)(0)(0);
|
||
|
|
|
||
|
|
inter_incr_in(3)(1)(0)(0)(4-1 downto 0) <= local_incr_rx_vec(32-1 downto 28);
|
||
|
|
local_incr_tx_vec(32-1 downto 28) <= inter_incr_out(3)(1)(0)(0)(4-1 downto 0);
|
||
|
|
|
||
|
|
inter_vc_write_in(3)(1)(0)(0)(4-1 downto 0) <= local_vc_write_rx(32-1 downto 28);
|
||
|
|
local_vc_write_tx(32-1 downto 28) <= inter_vc_write_out(3)(1)(0)(0)(4-1 downto 0);
|
||
|
|
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
-- Router at x= 3 y=1 z=0
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
router_310: entity work.router_pl
|
||
|
|
generic map (
|
||
|
|
port_num => 5,
|
||
|
|
Xis => 3,
|
||
|
|
Yis => 1,
|
||
|
|
Zis => 0,
|
||
|
|
header_incl_in_packet_length => true,
|
||
|
|
port_exist => (0,1,3,4,5),
|
||
|
|
vc_num_vec => (4, 4, 4, 4, 4),
|
||
|
|
vc_num_out_vec => (4, 4, 4, 4, 4),
|
||
|
|
vc_depth_array => ((4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4)),
|
||
|
|
vc_depth_out_array => ((4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4)),
|
||
|
|
rout_algo => "DXYU"
|
||
|
|
)
|
||
|
|
port map (
|
||
|
|
clk => clk,
|
||
|
|
rst => rst,
|
||
|
|
data_rx => data_in310,
|
||
|
|
vc_write_rx_vec => vc_write_rx_vec310,
|
||
|
|
incr_rx_vec => incr_rx_vec310,
|
||
|
|
data_tx_pl => data_out310,
|
||
|
|
vc_write_tx_pl_vec => vc_write_tx_pl_vec310,
|
||
|
|
incr_tx_pl_vec => incr_tx_pl_vec310
|
||
|
|
);
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
-- Router port connections to adjacent routers
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
data_in020(0) <= inter_data_in(0)(2)(0)(0);
|
||
|
|
inter_data_out(0)(2)(0)(0) <= data_out020(0) after delay_constant;
|
||
|
|
incr_rx_vec020(4-1 downto 0) <= inter_incr_in(0)(2)(0)(0)(4-1 downto 0);
|
||
|
|
inter_incr_out(0)(2)(0)(0)(4-1 downto 0) <= incr_tx_pl_vec020(4-1 downto 0);
|
||
|
|
vc_write_rx_vec020(4-1 downto 0) <= inter_vc_write_in(0)(2)(0)(0)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(0)(2)(0)(0)(4-1 downto 0) <= vc_write_tx_pl_vec020(4-1 downto 0);
|
||
|
|
data_in020(1) <= inter_data_in(0)(2)(0)(1);
|
||
|
|
inter_data_out(0)(2)(0)(1) <= data_out020(1) after delay_constant;
|
||
|
|
incr_rx_vec020(8-1 downto 4) <= inter_incr_in(0)(2)(0)(1)(4-1 downto 0);
|
||
|
|
inter_incr_out(0)(2)(0)(1)(4-1 downto 0) <= incr_tx_pl_vec020(8-1 downto 4);
|
||
|
|
vc_write_rx_vec020(8-1 downto 4) <= inter_vc_write_in(0)(2)(0)(1)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(0)(2)(0)(1)(4-1 downto 0) <= vc_write_tx_pl_vec020(8-1 downto 4);
|
||
|
|
|
||
|
|
inter_data_in(0)(2)(0)(1) <= inter_data_out(0)(2+1)(0)(3);
|
||
|
|
|
||
|
|
inter_incr_in(0)(2)(0)(1) <= inter_incr_out(0)(2+1)(0)(3);
|
||
|
|
|
||
|
|
inter_vc_write_in(0)(2)(0)(1) <= inter_vc_write_out(0)(2+1)(0)(3);
|
||
|
|
data_in020(2) <= inter_data_in(0)(2)(0)(2);
|
||
|
|
inter_data_out(0)(2)(0)(2) <= data_out020(2) after delay_constant;
|
||
|
|
incr_rx_vec020(12-1 downto 8) <= inter_incr_in(0)(2)(0)(2)(4-1 downto 0);
|
||
|
|
inter_incr_out(0)(2)(0)(2)(4-1 downto 0) <= incr_tx_pl_vec020(12-1 downto 8);
|
||
|
|
vc_write_rx_vec020(12-1 downto 8) <= inter_vc_write_in(0)(2)(0)(2)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(0)(2)(0)(2)(4-1 downto 0) <= vc_write_tx_pl_vec020(12-1 downto 8);
|
||
|
|
|
||
|
|
inter_data_in(0)(2)(0)(2) <= inter_data_out(0+1)(2)(0)(4);
|
||
|
|
|
||
|
|
inter_incr_in(0)(2)(0)(2) <= inter_incr_out(0+1)(2)(0)(4);
|
||
|
|
|
||
|
|
inter_vc_write_in(0)(2)(0)(2) <= inter_vc_write_out(0+1)(2)(0)(4);
|
||
|
|
data_in020(3) <= inter_data_in(0)(2)(0)(3);
|
||
|
|
inter_data_out(0)(2)(0)(3) <= data_out020(3) after delay_constant;
|
||
|
|
incr_rx_vec020(16-1 downto 12) <= inter_incr_in(0)(2)(0)(3)(4-1 downto 0);
|
||
|
|
inter_incr_out(0)(2)(0)(3)(4-1 downto 0) <= incr_tx_pl_vec020(16-1 downto 12);
|
||
|
|
vc_write_rx_vec020(16-1 downto 12) <= inter_vc_write_in(0)(2)(0)(3)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(0)(2)(0)(3)(4-1 downto 0) <= vc_write_tx_pl_vec020(16-1 downto 12);
|
||
|
|
|
||
|
|
inter_data_in(0)(2)(0)(3) <= inter_data_out(0)(2-1)(0)(1);
|
||
|
|
|
||
|
|
inter_incr_in(0)(2)(0)(3) <= inter_incr_out(0)(2-1)(0)(1);
|
||
|
|
|
||
|
|
inter_vc_write_in(0)(2)(0)(3) <= inter_vc_write_out(0)(2-1)(0)(1);
|
||
|
|
data_in020(4) <= inter_data_in(0)(2)(0)(5);
|
||
|
|
inter_data_out(0)(2)(0)(5) <= data_out020(4) after delay_constant;
|
||
|
|
incr_rx_vec020(20-1 downto 16) <= inter_incr_in(0)(2)(0)(5)(4-1 downto 0);
|
||
|
|
inter_incr_out(0)(2)(0)(5)(4-1 downto 0) <= incr_tx_pl_vec020(20-1 downto 16);
|
||
|
|
vc_write_rx_vec020(20-1 downto 16) <= inter_vc_write_in(0)(2)(0)(5)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(0)(2)(0)(5)(4-1 downto 0) <= vc_write_tx_pl_vec020(20-1 downto 16);
|
||
|
|
|
||
|
|
inter_data_in(0)(2)(0)(5) <= inter_data_out(0)(2)(0+1)(6);
|
||
|
|
|
||
|
|
inter_incr_in(0)(2)(0)(5) <= inter_incr_out(0)(2)(0+1)(6);
|
||
|
|
|
||
|
|
inter_vc_write_in(0)(2)(0)(5) <= inter_vc_write_out(0)(2)(0+1)(6);
|
||
|
|
|
||
|
|
inter_data_in(0)(2)(0)(0) <= local_rx(8);
|
||
|
|
local_tx(8) <= inter_data_out(0)(2)(0)(0);
|
||
|
|
|
||
|
|
inter_incr_in(0)(2)(0)(0)(4-1 downto 0) <= local_incr_rx_vec(36-1 downto 32);
|
||
|
|
local_incr_tx_vec(36-1 downto 32) <= inter_incr_out(0)(2)(0)(0)(4-1 downto 0);
|
||
|
|
|
||
|
|
inter_vc_write_in(0)(2)(0)(0)(4-1 downto 0) <= local_vc_write_rx(36-1 downto 32);
|
||
|
|
local_vc_write_tx(36-1 downto 32) <= inter_vc_write_out(0)(2)(0)(0)(4-1 downto 0);
|
||
|
|
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
-- Router at x= 0 y=2 z=0
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
router_020: entity work.router_pl
|
||
|
|
generic map (
|
||
|
|
port_num => 5,
|
||
|
|
Xis => 0,
|
||
|
|
Yis => 2,
|
||
|
|
Zis => 0,
|
||
|
|
header_incl_in_packet_length => true,
|
||
|
|
port_exist => (0,1,2,3,5),
|
||
|
|
vc_num_vec => (4, 4, 4, 4, 4),
|
||
|
|
vc_num_out_vec => (4, 4, 4, 4, 4),
|
||
|
|
vc_depth_array => ((4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4)),
|
||
|
|
vc_depth_out_array => ((4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4)),
|
||
|
|
rout_algo => "DXYU"
|
||
|
|
)
|
||
|
|
port map (
|
||
|
|
clk => clk,
|
||
|
|
rst => rst,
|
||
|
|
data_rx => data_in020,
|
||
|
|
vc_write_rx_vec => vc_write_rx_vec020,
|
||
|
|
incr_rx_vec => incr_rx_vec020,
|
||
|
|
data_tx_pl => data_out020,
|
||
|
|
vc_write_tx_pl_vec => vc_write_tx_pl_vec020,
|
||
|
|
incr_tx_pl_vec => incr_tx_pl_vec020
|
||
|
|
);
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
-- Router port connections to adjacent routers
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
data_in120(0) <= inter_data_in(1)(2)(0)(0);
|
||
|
|
inter_data_out(1)(2)(0)(0) <= data_out120(0) after delay_constant;
|
||
|
|
incr_rx_vec120(4-1 downto 0) <= inter_incr_in(1)(2)(0)(0)(4-1 downto 0);
|
||
|
|
inter_incr_out(1)(2)(0)(0)(4-1 downto 0) <= incr_tx_pl_vec120(4-1 downto 0);
|
||
|
|
vc_write_rx_vec120(4-1 downto 0) <= inter_vc_write_in(1)(2)(0)(0)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(1)(2)(0)(0)(4-1 downto 0) <= vc_write_tx_pl_vec120(4-1 downto 0);
|
||
|
|
data_in120(1) <= inter_data_in(1)(2)(0)(1);
|
||
|
|
inter_data_out(1)(2)(0)(1) <= data_out120(1) after delay_constant;
|
||
|
|
incr_rx_vec120(8-1 downto 4) <= inter_incr_in(1)(2)(0)(1)(4-1 downto 0);
|
||
|
|
inter_incr_out(1)(2)(0)(1)(4-1 downto 0) <= incr_tx_pl_vec120(8-1 downto 4);
|
||
|
|
vc_write_rx_vec120(8-1 downto 4) <= inter_vc_write_in(1)(2)(0)(1)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(1)(2)(0)(1)(4-1 downto 0) <= vc_write_tx_pl_vec120(8-1 downto 4);
|
||
|
|
|
||
|
|
inter_data_in(1)(2)(0)(1) <= inter_data_out(1)(2+1)(0)(3);
|
||
|
|
|
||
|
|
inter_incr_in(1)(2)(0)(1) <= inter_incr_out(1)(2+1)(0)(3);
|
||
|
|
|
||
|
|
inter_vc_write_in(1)(2)(0)(1) <= inter_vc_write_out(1)(2+1)(0)(3);
|
||
|
|
data_in120(2) <= inter_data_in(1)(2)(0)(2);
|
||
|
|
inter_data_out(1)(2)(0)(2) <= data_out120(2) after delay_constant;
|
||
|
|
incr_rx_vec120(12-1 downto 8) <= inter_incr_in(1)(2)(0)(2)(4-1 downto 0);
|
||
|
|
inter_incr_out(1)(2)(0)(2)(4-1 downto 0) <= incr_tx_pl_vec120(12-1 downto 8);
|
||
|
|
vc_write_rx_vec120(12-1 downto 8) <= inter_vc_write_in(1)(2)(0)(2)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(1)(2)(0)(2)(4-1 downto 0) <= vc_write_tx_pl_vec120(12-1 downto 8);
|
||
|
|
|
||
|
|
inter_data_in(1)(2)(0)(2) <= inter_data_out(1+1)(2)(0)(4);
|
||
|
|
|
||
|
|
inter_incr_in(1)(2)(0)(2) <= inter_incr_out(1+1)(2)(0)(4);
|
||
|
|
|
||
|
|
inter_vc_write_in(1)(2)(0)(2) <= inter_vc_write_out(1+1)(2)(0)(4);
|
||
|
|
data_in120(3) <= inter_data_in(1)(2)(0)(3);
|
||
|
|
inter_data_out(1)(2)(0)(3) <= data_out120(3) after delay_constant;
|
||
|
|
incr_rx_vec120(16-1 downto 12) <= inter_incr_in(1)(2)(0)(3)(4-1 downto 0);
|
||
|
|
inter_incr_out(1)(2)(0)(3)(4-1 downto 0) <= incr_tx_pl_vec120(16-1 downto 12);
|
||
|
|
vc_write_rx_vec120(16-1 downto 12) <= inter_vc_write_in(1)(2)(0)(3)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(1)(2)(0)(3)(4-1 downto 0) <= vc_write_tx_pl_vec120(16-1 downto 12);
|
||
|
|
|
||
|
|
inter_data_in(1)(2)(0)(3) <= inter_data_out(1)(2-1)(0)(1);
|
||
|
|
|
||
|
|
inter_incr_in(1)(2)(0)(3) <= inter_incr_out(1)(2-1)(0)(1);
|
||
|
|
|
||
|
|
inter_vc_write_in(1)(2)(0)(3) <= inter_vc_write_out(1)(2-1)(0)(1);
|
||
|
|
data_in120(4) <= inter_data_in(1)(2)(0)(4);
|
||
|
|
inter_data_out(1)(2)(0)(4) <= data_out120(4) after delay_constant;
|
||
|
|
incr_rx_vec120(20-1 downto 16) <= inter_incr_in(1)(2)(0)(4)(4-1 downto 0);
|
||
|
|
inter_incr_out(1)(2)(0)(4)(4-1 downto 0) <= incr_tx_pl_vec120(20-1 downto 16);
|
||
|
|
vc_write_rx_vec120(20-1 downto 16) <= inter_vc_write_in(1)(2)(0)(4)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(1)(2)(0)(4)(4-1 downto 0) <= vc_write_tx_pl_vec120(20-1 downto 16);
|
||
|
|
|
||
|
|
inter_data_in(1)(2)(0)(4) <= inter_data_out(1-1)(2)(0)(2);
|
||
|
|
|
||
|
|
inter_incr_in(1)(2)(0)(4) <= inter_incr_out(1-1)(2)(0)(2);
|
||
|
|
|
||
|
|
inter_vc_write_in(1)(2)(0)(4) <= inter_vc_write_out(1-1)(2)(0)(2);
|
||
|
|
data_in120(5) <= inter_data_in(1)(2)(0)(5);
|
||
|
|
inter_data_out(1)(2)(0)(5) <= data_out120(5) after delay_constant;
|
||
|
|
incr_rx_vec120(24-1 downto 20) <= inter_incr_in(1)(2)(0)(5)(4-1 downto 0);
|
||
|
|
inter_incr_out(1)(2)(0)(5)(4-1 downto 0) <= incr_tx_pl_vec120(24-1 downto 20);
|
||
|
|
vc_write_rx_vec120(24-1 downto 20) <= inter_vc_write_in(1)(2)(0)(5)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(1)(2)(0)(5)(4-1 downto 0) <= vc_write_tx_pl_vec120(24-1 downto 20);
|
||
|
|
|
||
|
|
inter_data_in(1)(2)(0)(5) <= inter_data_out(1)(2)(0+1)(6);
|
||
|
|
|
||
|
|
inter_incr_in(1)(2)(0)(5) <= inter_incr_out(1)(2)(0+1)(6);
|
||
|
|
|
||
|
|
inter_vc_write_in(1)(2)(0)(5) <= inter_vc_write_out(1)(2)(0+1)(6);
|
||
|
|
|
||
|
|
inter_data_in(1)(2)(0)(0) <= local_rx(9);
|
||
|
|
local_tx(9) <= inter_data_out(1)(2)(0)(0);
|
||
|
|
|
||
|
|
inter_incr_in(1)(2)(0)(0)(4-1 downto 0) <= local_incr_rx_vec(40-1 downto 36);
|
||
|
|
local_incr_tx_vec(40-1 downto 36) <= inter_incr_out(1)(2)(0)(0)(4-1 downto 0);
|
||
|
|
|
||
|
|
inter_vc_write_in(1)(2)(0)(0)(4-1 downto 0) <= local_vc_write_rx(40-1 downto 36);
|
||
|
|
local_vc_write_tx(40-1 downto 36) <= inter_vc_write_out(1)(2)(0)(0)(4-1 downto 0);
|
||
|
|
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
-- Router at x= 1 y=2 z=0
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
router_120: entity work.router_pl
|
||
|
|
generic map (
|
||
|
|
port_num => 6,
|
||
|
|
Xis => 1,
|
||
|
|
Yis => 2,
|
||
|
|
Zis => 0,
|
||
|
|
header_incl_in_packet_length => true,
|
||
|
|
port_exist => (0,1,2,3,4,5),
|
||
|
|
vc_num_vec => (4, 4, 4, 4, 4, 4),
|
||
|
|
vc_num_out_vec => (4, 4, 4, 4, 4, 4),
|
||
|
|
vc_depth_array => ((4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4)),
|
||
|
|
vc_depth_out_array => ((4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4)),
|
||
|
|
rout_algo => "DXYU"
|
||
|
|
)
|
||
|
|
port map (
|
||
|
|
clk => clk,
|
||
|
|
rst => rst,
|
||
|
|
data_rx => data_in120,
|
||
|
|
vc_write_rx_vec => vc_write_rx_vec120,
|
||
|
|
incr_rx_vec => incr_rx_vec120,
|
||
|
|
data_tx_pl => data_out120,
|
||
|
|
vc_write_tx_pl_vec => vc_write_tx_pl_vec120,
|
||
|
|
incr_tx_pl_vec => incr_tx_pl_vec120
|
||
|
|
);
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
-- Router port connections to adjacent routers
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
data_in220(0) <= inter_data_in(2)(2)(0)(0);
|
||
|
|
inter_data_out(2)(2)(0)(0) <= data_out220(0) after delay_constant;
|
||
|
|
incr_rx_vec220(4-1 downto 0) <= inter_incr_in(2)(2)(0)(0)(4-1 downto 0);
|
||
|
|
inter_incr_out(2)(2)(0)(0)(4-1 downto 0) <= incr_tx_pl_vec220(4-1 downto 0);
|
||
|
|
vc_write_rx_vec220(4-1 downto 0) <= inter_vc_write_in(2)(2)(0)(0)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(2)(2)(0)(0)(4-1 downto 0) <= vc_write_tx_pl_vec220(4-1 downto 0);
|
||
|
|
data_in220(1) <= inter_data_in(2)(2)(0)(1);
|
||
|
|
inter_data_out(2)(2)(0)(1) <= data_out220(1) after delay_constant;
|
||
|
|
incr_rx_vec220(8-1 downto 4) <= inter_incr_in(2)(2)(0)(1)(4-1 downto 0);
|
||
|
|
inter_incr_out(2)(2)(0)(1)(4-1 downto 0) <= incr_tx_pl_vec220(8-1 downto 4);
|
||
|
|
vc_write_rx_vec220(8-1 downto 4) <= inter_vc_write_in(2)(2)(0)(1)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(2)(2)(0)(1)(4-1 downto 0) <= vc_write_tx_pl_vec220(8-1 downto 4);
|
||
|
|
|
||
|
|
inter_data_in(2)(2)(0)(1) <= inter_data_out(2)(2+1)(0)(3);
|
||
|
|
|
||
|
|
inter_incr_in(2)(2)(0)(1) <= inter_incr_out(2)(2+1)(0)(3);
|
||
|
|
|
||
|
|
inter_vc_write_in(2)(2)(0)(1) <= inter_vc_write_out(2)(2+1)(0)(3);
|
||
|
|
data_in220(2) <= inter_data_in(2)(2)(0)(2);
|
||
|
|
inter_data_out(2)(2)(0)(2) <= data_out220(2) after delay_constant;
|
||
|
|
incr_rx_vec220(12-1 downto 8) <= inter_incr_in(2)(2)(0)(2)(4-1 downto 0);
|
||
|
|
inter_incr_out(2)(2)(0)(2)(4-1 downto 0) <= incr_tx_pl_vec220(12-1 downto 8);
|
||
|
|
vc_write_rx_vec220(12-1 downto 8) <= inter_vc_write_in(2)(2)(0)(2)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(2)(2)(0)(2)(4-1 downto 0) <= vc_write_tx_pl_vec220(12-1 downto 8);
|
||
|
|
|
||
|
|
inter_data_in(2)(2)(0)(2) <= inter_data_out(2+1)(2)(0)(4);
|
||
|
|
|
||
|
|
inter_incr_in(2)(2)(0)(2) <= inter_incr_out(2+1)(2)(0)(4);
|
||
|
|
|
||
|
|
inter_vc_write_in(2)(2)(0)(2) <= inter_vc_write_out(2+1)(2)(0)(4);
|
||
|
|
data_in220(3) <= inter_data_in(2)(2)(0)(3);
|
||
|
|
inter_data_out(2)(2)(0)(3) <= data_out220(3) after delay_constant;
|
||
|
|
incr_rx_vec220(16-1 downto 12) <= inter_incr_in(2)(2)(0)(3)(4-1 downto 0);
|
||
|
|
inter_incr_out(2)(2)(0)(3)(4-1 downto 0) <= incr_tx_pl_vec220(16-1 downto 12);
|
||
|
|
vc_write_rx_vec220(16-1 downto 12) <= inter_vc_write_in(2)(2)(0)(3)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(2)(2)(0)(3)(4-1 downto 0) <= vc_write_tx_pl_vec220(16-1 downto 12);
|
||
|
|
|
||
|
|
inter_data_in(2)(2)(0)(3) <= inter_data_out(2)(2-1)(0)(1);
|
||
|
|
|
||
|
|
inter_incr_in(2)(2)(0)(3) <= inter_incr_out(2)(2-1)(0)(1);
|
||
|
|
|
||
|
|
inter_vc_write_in(2)(2)(0)(3) <= inter_vc_write_out(2)(2-1)(0)(1);
|
||
|
|
data_in220(4) <= inter_data_in(2)(2)(0)(4);
|
||
|
|
inter_data_out(2)(2)(0)(4) <= data_out220(4) after delay_constant;
|
||
|
|
incr_rx_vec220(20-1 downto 16) <= inter_incr_in(2)(2)(0)(4)(4-1 downto 0);
|
||
|
|
inter_incr_out(2)(2)(0)(4)(4-1 downto 0) <= incr_tx_pl_vec220(20-1 downto 16);
|
||
|
|
vc_write_rx_vec220(20-1 downto 16) <= inter_vc_write_in(2)(2)(0)(4)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(2)(2)(0)(4)(4-1 downto 0) <= vc_write_tx_pl_vec220(20-1 downto 16);
|
||
|
|
|
||
|
|
inter_data_in(2)(2)(0)(4) <= inter_data_out(2-1)(2)(0)(2);
|
||
|
|
|
||
|
|
inter_incr_in(2)(2)(0)(4) <= inter_incr_out(2-1)(2)(0)(2);
|
||
|
|
|
||
|
|
inter_vc_write_in(2)(2)(0)(4) <= inter_vc_write_out(2-1)(2)(0)(2);
|
||
|
|
data_in220(5) <= inter_data_in(2)(2)(0)(5);
|
||
|
|
inter_data_out(2)(2)(0)(5) <= data_out220(5) after delay_constant;
|
||
|
|
incr_rx_vec220(24-1 downto 20) <= inter_incr_in(2)(2)(0)(5)(4-1 downto 0);
|
||
|
|
inter_incr_out(2)(2)(0)(5)(4-1 downto 0) <= incr_tx_pl_vec220(24-1 downto 20);
|
||
|
|
vc_write_rx_vec220(24-1 downto 20) <= inter_vc_write_in(2)(2)(0)(5)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(2)(2)(0)(5)(4-1 downto 0) <= vc_write_tx_pl_vec220(24-1 downto 20);
|
||
|
|
|
||
|
|
inter_data_in(2)(2)(0)(5) <= inter_data_out(2)(2)(0+1)(6);
|
||
|
|
|
||
|
|
inter_incr_in(2)(2)(0)(5) <= inter_incr_out(2)(2)(0+1)(6);
|
||
|
|
|
||
|
|
inter_vc_write_in(2)(2)(0)(5) <= inter_vc_write_out(2)(2)(0+1)(6);
|
||
|
|
|
||
|
|
inter_data_in(2)(2)(0)(0) <= local_rx(10);
|
||
|
|
local_tx(10) <= inter_data_out(2)(2)(0)(0);
|
||
|
|
|
||
|
|
inter_incr_in(2)(2)(0)(0)(4-1 downto 0) <= local_incr_rx_vec(44-1 downto 40);
|
||
|
|
local_incr_tx_vec(44-1 downto 40) <= inter_incr_out(2)(2)(0)(0)(4-1 downto 0);
|
||
|
|
|
||
|
|
inter_vc_write_in(2)(2)(0)(0)(4-1 downto 0) <= local_vc_write_rx(44-1 downto 40);
|
||
|
|
local_vc_write_tx(44-1 downto 40) <= inter_vc_write_out(2)(2)(0)(0)(4-1 downto 0);
|
||
|
|
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
-- Router at x= 2 y=2 z=0
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
router_220: entity work.router_pl
|
||
|
|
generic map (
|
||
|
|
port_num => 6,
|
||
|
|
Xis => 2,
|
||
|
|
Yis => 2,
|
||
|
|
Zis => 0,
|
||
|
|
header_incl_in_packet_length => true,
|
||
|
|
port_exist => (0,1,2,3,4,5),
|
||
|
|
vc_num_vec => (4, 4, 4, 4, 4, 4),
|
||
|
|
vc_num_out_vec => (4, 4, 4, 4, 4, 4),
|
||
|
|
vc_depth_array => ((4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4)),
|
||
|
|
vc_depth_out_array => ((4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4)),
|
||
|
|
rout_algo => "DXYU"
|
||
|
|
)
|
||
|
|
port map (
|
||
|
|
clk => clk,
|
||
|
|
rst => rst,
|
||
|
|
data_rx => data_in220,
|
||
|
|
vc_write_rx_vec => vc_write_rx_vec220,
|
||
|
|
incr_rx_vec => incr_rx_vec220,
|
||
|
|
data_tx_pl => data_out220,
|
||
|
|
vc_write_tx_pl_vec => vc_write_tx_pl_vec220,
|
||
|
|
incr_tx_pl_vec => incr_tx_pl_vec220
|
||
|
|
);
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
-- Router port connections to adjacent routers
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
data_in320(0) <= inter_data_in(3)(2)(0)(0);
|
||
|
|
inter_data_out(3)(2)(0)(0) <= data_out320(0) after delay_constant;
|
||
|
|
incr_rx_vec320(4-1 downto 0) <= inter_incr_in(3)(2)(0)(0)(4-1 downto 0);
|
||
|
|
inter_incr_out(3)(2)(0)(0)(4-1 downto 0) <= incr_tx_pl_vec320(4-1 downto 0);
|
||
|
|
vc_write_rx_vec320(4-1 downto 0) <= inter_vc_write_in(3)(2)(0)(0)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(3)(2)(0)(0)(4-1 downto 0) <= vc_write_tx_pl_vec320(4-1 downto 0);
|
||
|
|
data_in320(1) <= inter_data_in(3)(2)(0)(1);
|
||
|
|
inter_data_out(3)(2)(0)(1) <= data_out320(1) after delay_constant;
|
||
|
|
incr_rx_vec320(8-1 downto 4) <= inter_incr_in(3)(2)(0)(1)(4-1 downto 0);
|
||
|
|
inter_incr_out(3)(2)(0)(1)(4-1 downto 0) <= incr_tx_pl_vec320(8-1 downto 4);
|
||
|
|
vc_write_rx_vec320(8-1 downto 4) <= inter_vc_write_in(3)(2)(0)(1)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(3)(2)(0)(1)(4-1 downto 0) <= vc_write_tx_pl_vec320(8-1 downto 4);
|
||
|
|
|
||
|
|
inter_data_in(3)(2)(0)(1) <= inter_data_out(3)(2+1)(0)(3);
|
||
|
|
|
||
|
|
inter_incr_in(3)(2)(0)(1) <= inter_incr_out(3)(2+1)(0)(3);
|
||
|
|
|
||
|
|
inter_vc_write_in(3)(2)(0)(1) <= inter_vc_write_out(3)(2+1)(0)(3);
|
||
|
|
data_in320(2) <= inter_data_in(3)(2)(0)(3);
|
||
|
|
inter_data_out(3)(2)(0)(3) <= data_out320(2) after delay_constant;
|
||
|
|
incr_rx_vec320(12-1 downto 8) <= inter_incr_in(3)(2)(0)(3)(4-1 downto 0);
|
||
|
|
inter_incr_out(3)(2)(0)(3)(4-1 downto 0) <= incr_tx_pl_vec320(12-1 downto 8);
|
||
|
|
vc_write_rx_vec320(12-1 downto 8) <= inter_vc_write_in(3)(2)(0)(3)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(3)(2)(0)(3)(4-1 downto 0) <= vc_write_tx_pl_vec320(12-1 downto 8);
|
||
|
|
|
||
|
|
inter_data_in(3)(2)(0)(3) <= inter_data_out(3)(2-1)(0)(1);
|
||
|
|
|
||
|
|
inter_incr_in(3)(2)(0)(3) <= inter_incr_out(3)(2-1)(0)(1);
|
||
|
|
|
||
|
|
inter_vc_write_in(3)(2)(0)(3) <= inter_vc_write_out(3)(2-1)(0)(1);
|
||
|
|
data_in320(3) <= inter_data_in(3)(2)(0)(4);
|
||
|
|
inter_data_out(3)(2)(0)(4) <= data_out320(3) after delay_constant;
|
||
|
|
incr_rx_vec320(16-1 downto 12) <= inter_incr_in(3)(2)(0)(4)(4-1 downto 0);
|
||
|
|
inter_incr_out(3)(2)(0)(4)(4-1 downto 0) <= incr_tx_pl_vec320(16-1 downto 12);
|
||
|
|
vc_write_rx_vec320(16-1 downto 12) <= inter_vc_write_in(3)(2)(0)(4)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(3)(2)(0)(4)(4-1 downto 0) <= vc_write_tx_pl_vec320(16-1 downto 12);
|
||
|
|
|
||
|
|
inter_data_in(3)(2)(0)(4) <= inter_data_out(3-1)(2)(0)(2);
|
||
|
|
|
||
|
|
inter_incr_in(3)(2)(0)(4) <= inter_incr_out(3-1)(2)(0)(2);
|
||
|
|
|
||
|
|
inter_vc_write_in(3)(2)(0)(4) <= inter_vc_write_out(3-1)(2)(0)(2);
|
||
|
|
data_in320(4) <= inter_data_in(3)(2)(0)(5);
|
||
|
|
inter_data_out(3)(2)(0)(5) <= data_out320(4) after delay_constant;
|
||
|
|
incr_rx_vec320(20-1 downto 16) <= inter_incr_in(3)(2)(0)(5)(4-1 downto 0);
|
||
|
|
inter_incr_out(3)(2)(0)(5)(4-1 downto 0) <= incr_tx_pl_vec320(20-1 downto 16);
|
||
|
|
vc_write_rx_vec320(20-1 downto 16) <= inter_vc_write_in(3)(2)(0)(5)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(3)(2)(0)(5)(4-1 downto 0) <= vc_write_tx_pl_vec320(20-1 downto 16);
|
||
|
|
|
||
|
|
inter_data_in(3)(2)(0)(5) <= inter_data_out(3)(2)(0+1)(6);
|
||
|
|
|
||
|
|
inter_incr_in(3)(2)(0)(5) <= inter_incr_out(3)(2)(0+1)(6);
|
||
|
|
|
||
|
|
inter_vc_write_in(3)(2)(0)(5) <= inter_vc_write_out(3)(2)(0+1)(6);
|
||
|
|
|
||
|
|
inter_data_in(3)(2)(0)(0) <= local_rx(11);
|
||
|
|
local_tx(11) <= inter_data_out(3)(2)(0)(0);
|
||
|
|
|
||
|
|
inter_incr_in(3)(2)(0)(0)(4-1 downto 0) <= local_incr_rx_vec(48-1 downto 44);
|
||
|
|
local_incr_tx_vec(48-1 downto 44) <= inter_incr_out(3)(2)(0)(0)(4-1 downto 0);
|
||
|
|
|
||
|
|
inter_vc_write_in(3)(2)(0)(0)(4-1 downto 0) <= local_vc_write_rx(48-1 downto 44);
|
||
|
|
local_vc_write_tx(48-1 downto 44) <= inter_vc_write_out(3)(2)(0)(0)(4-1 downto 0);
|
||
|
|
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
-- Router at x= 3 y=2 z=0
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
router_320: entity work.router_pl
|
||
|
|
generic map (
|
||
|
|
port_num => 5,
|
||
|
|
Xis => 3,
|
||
|
|
Yis => 2,
|
||
|
|
Zis => 0,
|
||
|
|
header_incl_in_packet_length => true,
|
||
|
|
port_exist => (0,1,3,4,5),
|
||
|
|
vc_num_vec => (4, 4, 4, 4, 4),
|
||
|
|
vc_num_out_vec => (4, 4, 4, 4, 4),
|
||
|
|
vc_depth_array => ((4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4)),
|
||
|
|
vc_depth_out_array => ((4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4)),
|
||
|
|
rout_algo => "DXYU"
|
||
|
|
)
|
||
|
|
port map (
|
||
|
|
clk => clk,
|
||
|
|
rst => rst,
|
||
|
|
data_rx => data_in320,
|
||
|
|
vc_write_rx_vec => vc_write_rx_vec320,
|
||
|
|
incr_rx_vec => incr_rx_vec320,
|
||
|
|
data_tx_pl => data_out320,
|
||
|
|
vc_write_tx_pl_vec => vc_write_tx_pl_vec320,
|
||
|
|
incr_tx_pl_vec => incr_tx_pl_vec320
|
||
|
|
);
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
-- Router port connections to adjacent routers
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
data_in030(0) <= inter_data_in(0)(3)(0)(0);
|
||
|
|
inter_data_out(0)(3)(0)(0) <= data_out030(0) after delay_constant;
|
||
|
|
incr_rx_vec030(4-1 downto 0) <= inter_incr_in(0)(3)(0)(0)(4-1 downto 0);
|
||
|
|
inter_incr_out(0)(3)(0)(0)(4-1 downto 0) <= incr_tx_pl_vec030(4-1 downto 0);
|
||
|
|
vc_write_rx_vec030(4-1 downto 0) <= inter_vc_write_in(0)(3)(0)(0)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(0)(3)(0)(0)(4-1 downto 0) <= vc_write_tx_pl_vec030(4-1 downto 0);
|
||
|
|
data_in030(1) <= inter_data_in(0)(3)(0)(2);
|
||
|
|
inter_data_out(0)(3)(0)(2) <= data_out030(1) after delay_constant;
|
||
|
|
incr_rx_vec030(8-1 downto 4) <= inter_incr_in(0)(3)(0)(2)(4-1 downto 0);
|
||
|
|
inter_incr_out(0)(3)(0)(2)(4-1 downto 0) <= incr_tx_pl_vec030(8-1 downto 4);
|
||
|
|
vc_write_rx_vec030(8-1 downto 4) <= inter_vc_write_in(0)(3)(0)(2)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(0)(3)(0)(2)(4-1 downto 0) <= vc_write_tx_pl_vec030(8-1 downto 4);
|
||
|
|
|
||
|
|
inter_data_in(0)(3)(0)(2) <= inter_data_out(0+1)(3)(0)(4);
|
||
|
|
|
||
|
|
inter_incr_in(0)(3)(0)(2) <= inter_incr_out(0+1)(3)(0)(4);
|
||
|
|
|
||
|
|
inter_vc_write_in(0)(3)(0)(2) <= inter_vc_write_out(0+1)(3)(0)(4);
|
||
|
|
data_in030(2) <= inter_data_in(0)(3)(0)(3);
|
||
|
|
inter_data_out(0)(3)(0)(3) <= data_out030(2) after delay_constant;
|
||
|
|
incr_rx_vec030(12-1 downto 8) <= inter_incr_in(0)(3)(0)(3)(4-1 downto 0);
|
||
|
|
inter_incr_out(0)(3)(0)(3)(4-1 downto 0) <= incr_tx_pl_vec030(12-1 downto 8);
|
||
|
|
vc_write_rx_vec030(12-1 downto 8) <= inter_vc_write_in(0)(3)(0)(3)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(0)(3)(0)(3)(4-1 downto 0) <= vc_write_tx_pl_vec030(12-1 downto 8);
|
||
|
|
|
||
|
|
inter_data_in(0)(3)(0)(3) <= inter_data_out(0)(3-1)(0)(1);
|
||
|
|
|
||
|
|
inter_incr_in(0)(3)(0)(3) <= inter_incr_out(0)(3-1)(0)(1);
|
||
|
|
|
||
|
|
inter_vc_write_in(0)(3)(0)(3) <= inter_vc_write_out(0)(3-1)(0)(1);
|
||
|
|
data_in030(3) <= inter_data_in(0)(3)(0)(5);
|
||
|
|
inter_data_out(0)(3)(0)(5) <= data_out030(3) after delay_constant;
|
||
|
|
incr_rx_vec030(16-1 downto 12) <= inter_incr_in(0)(3)(0)(5)(4-1 downto 0);
|
||
|
|
inter_incr_out(0)(3)(0)(5)(4-1 downto 0) <= incr_tx_pl_vec030(16-1 downto 12);
|
||
|
|
vc_write_rx_vec030(16-1 downto 12) <= inter_vc_write_in(0)(3)(0)(5)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(0)(3)(0)(5)(4-1 downto 0) <= vc_write_tx_pl_vec030(16-1 downto 12);
|
||
|
|
|
||
|
|
inter_data_in(0)(3)(0)(5) <= inter_data_out(0)(3)(0+1)(6);
|
||
|
|
|
||
|
|
inter_incr_in(0)(3)(0)(5) <= inter_incr_out(0)(3)(0+1)(6);
|
||
|
|
|
||
|
|
inter_vc_write_in(0)(3)(0)(5) <= inter_vc_write_out(0)(3)(0+1)(6);
|
||
|
|
|
||
|
|
inter_data_in(0)(3)(0)(0) <= local_rx(12);
|
||
|
|
local_tx(12) <= inter_data_out(0)(3)(0)(0);
|
||
|
|
|
||
|
|
inter_incr_in(0)(3)(0)(0)(4-1 downto 0) <= local_incr_rx_vec(52-1 downto 48);
|
||
|
|
local_incr_tx_vec(52-1 downto 48) <= inter_incr_out(0)(3)(0)(0)(4-1 downto 0);
|
||
|
|
|
||
|
|
inter_vc_write_in(0)(3)(0)(0)(4-1 downto 0) <= local_vc_write_rx(52-1 downto 48);
|
||
|
|
local_vc_write_tx(52-1 downto 48) <= inter_vc_write_out(0)(3)(0)(0)(4-1 downto 0);
|
||
|
|
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
-- Router at x= 0 y=3 z=0
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
router_030: entity work.router_pl
|
||
|
|
generic map (
|
||
|
|
port_num => 4,
|
||
|
|
Xis => 0,
|
||
|
|
Yis => 3,
|
||
|
|
Zis => 0,
|
||
|
|
header_incl_in_packet_length => true,
|
||
|
|
port_exist => (0,2,3,5),
|
||
|
|
vc_num_vec => (4, 4, 4, 4),
|
||
|
|
vc_num_out_vec => (4, 4, 4, 4),
|
||
|
|
vc_depth_array => ((4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4)),
|
||
|
|
vc_depth_out_array => ((4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4)),
|
||
|
|
rout_algo => "DXYU"
|
||
|
|
)
|
||
|
|
port map (
|
||
|
|
clk => clk,
|
||
|
|
rst => rst,
|
||
|
|
data_rx => data_in030,
|
||
|
|
vc_write_rx_vec => vc_write_rx_vec030,
|
||
|
|
incr_rx_vec => incr_rx_vec030,
|
||
|
|
data_tx_pl => data_out030,
|
||
|
|
vc_write_tx_pl_vec => vc_write_tx_pl_vec030,
|
||
|
|
incr_tx_pl_vec => incr_tx_pl_vec030
|
||
|
|
);
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
-- Router port connections to adjacent routers
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
data_in130(0) <= inter_data_in(1)(3)(0)(0);
|
||
|
|
inter_data_out(1)(3)(0)(0) <= data_out130(0) after delay_constant;
|
||
|
|
incr_rx_vec130(4-1 downto 0) <= inter_incr_in(1)(3)(0)(0)(4-1 downto 0);
|
||
|
|
inter_incr_out(1)(3)(0)(0)(4-1 downto 0) <= incr_tx_pl_vec130(4-1 downto 0);
|
||
|
|
vc_write_rx_vec130(4-1 downto 0) <= inter_vc_write_in(1)(3)(0)(0)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(1)(3)(0)(0)(4-1 downto 0) <= vc_write_tx_pl_vec130(4-1 downto 0);
|
||
|
|
data_in130(1) <= inter_data_in(1)(3)(0)(2);
|
||
|
|
inter_data_out(1)(3)(0)(2) <= data_out130(1) after delay_constant;
|
||
|
|
incr_rx_vec130(8-1 downto 4) <= inter_incr_in(1)(3)(0)(2)(4-1 downto 0);
|
||
|
|
inter_incr_out(1)(3)(0)(2)(4-1 downto 0) <= incr_tx_pl_vec130(8-1 downto 4);
|
||
|
|
vc_write_rx_vec130(8-1 downto 4) <= inter_vc_write_in(1)(3)(0)(2)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(1)(3)(0)(2)(4-1 downto 0) <= vc_write_tx_pl_vec130(8-1 downto 4);
|
||
|
|
|
||
|
|
inter_data_in(1)(3)(0)(2) <= inter_data_out(1+1)(3)(0)(4);
|
||
|
|
|
||
|
|
inter_incr_in(1)(3)(0)(2) <= inter_incr_out(1+1)(3)(0)(4);
|
||
|
|
|
||
|
|
inter_vc_write_in(1)(3)(0)(2) <= inter_vc_write_out(1+1)(3)(0)(4);
|
||
|
|
data_in130(2) <= inter_data_in(1)(3)(0)(3);
|
||
|
|
inter_data_out(1)(3)(0)(3) <= data_out130(2) after delay_constant;
|
||
|
|
incr_rx_vec130(12-1 downto 8) <= inter_incr_in(1)(3)(0)(3)(4-1 downto 0);
|
||
|
|
inter_incr_out(1)(3)(0)(3)(4-1 downto 0) <= incr_tx_pl_vec130(12-1 downto 8);
|
||
|
|
vc_write_rx_vec130(12-1 downto 8) <= inter_vc_write_in(1)(3)(0)(3)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(1)(3)(0)(3)(4-1 downto 0) <= vc_write_tx_pl_vec130(12-1 downto 8);
|
||
|
|
|
||
|
|
inter_data_in(1)(3)(0)(3) <= inter_data_out(1)(3-1)(0)(1);
|
||
|
|
|
||
|
|
inter_incr_in(1)(3)(0)(3) <= inter_incr_out(1)(3-1)(0)(1);
|
||
|
|
|
||
|
|
inter_vc_write_in(1)(3)(0)(3) <= inter_vc_write_out(1)(3-1)(0)(1);
|
||
|
|
data_in130(3) <= inter_data_in(1)(3)(0)(4);
|
||
|
|
inter_data_out(1)(3)(0)(4) <= data_out130(3) after delay_constant;
|
||
|
|
incr_rx_vec130(16-1 downto 12) <= inter_incr_in(1)(3)(0)(4)(4-1 downto 0);
|
||
|
|
inter_incr_out(1)(3)(0)(4)(4-1 downto 0) <= incr_tx_pl_vec130(16-1 downto 12);
|
||
|
|
vc_write_rx_vec130(16-1 downto 12) <= inter_vc_write_in(1)(3)(0)(4)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(1)(3)(0)(4)(4-1 downto 0) <= vc_write_tx_pl_vec130(16-1 downto 12);
|
||
|
|
|
||
|
|
inter_data_in(1)(3)(0)(4) <= inter_data_out(1-1)(3)(0)(2);
|
||
|
|
|
||
|
|
inter_incr_in(1)(3)(0)(4) <= inter_incr_out(1-1)(3)(0)(2);
|
||
|
|
|
||
|
|
inter_vc_write_in(1)(3)(0)(4) <= inter_vc_write_out(1-1)(3)(0)(2);
|
||
|
|
data_in130(4) <= inter_data_in(1)(3)(0)(5);
|
||
|
|
inter_data_out(1)(3)(0)(5) <= data_out130(4) after delay_constant;
|
||
|
|
incr_rx_vec130(20-1 downto 16) <= inter_incr_in(1)(3)(0)(5)(4-1 downto 0);
|
||
|
|
inter_incr_out(1)(3)(0)(5)(4-1 downto 0) <= incr_tx_pl_vec130(20-1 downto 16);
|
||
|
|
vc_write_rx_vec130(20-1 downto 16) <= inter_vc_write_in(1)(3)(0)(5)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(1)(3)(0)(5)(4-1 downto 0) <= vc_write_tx_pl_vec130(20-1 downto 16);
|
||
|
|
|
||
|
|
inter_data_in(1)(3)(0)(5) <= inter_data_out(1)(3)(0+1)(6);
|
||
|
|
|
||
|
|
inter_incr_in(1)(3)(0)(5) <= inter_incr_out(1)(3)(0+1)(6);
|
||
|
|
|
||
|
|
inter_vc_write_in(1)(3)(0)(5) <= inter_vc_write_out(1)(3)(0+1)(6);
|
||
|
|
|
||
|
|
inter_data_in(1)(3)(0)(0) <= local_rx(13);
|
||
|
|
local_tx(13) <= inter_data_out(1)(3)(0)(0);
|
||
|
|
|
||
|
|
inter_incr_in(1)(3)(0)(0)(4-1 downto 0) <= local_incr_rx_vec(56-1 downto 52);
|
||
|
|
local_incr_tx_vec(56-1 downto 52) <= inter_incr_out(1)(3)(0)(0)(4-1 downto 0);
|
||
|
|
|
||
|
|
inter_vc_write_in(1)(3)(0)(0)(4-1 downto 0) <= local_vc_write_rx(56-1 downto 52);
|
||
|
|
local_vc_write_tx(56-1 downto 52) <= inter_vc_write_out(1)(3)(0)(0)(4-1 downto 0);
|
||
|
|
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
-- Router at x= 1 y=3 z=0
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
router_130: entity work.router_pl
|
||
|
|
generic map (
|
||
|
|
port_num => 5,
|
||
|
|
Xis => 1,
|
||
|
|
Yis => 3,
|
||
|
|
Zis => 0,
|
||
|
|
header_incl_in_packet_length => true,
|
||
|
|
port_exist => (0,2,3,4,5),
|
||
|
|
vc_num_vec => (4, 4, 4, 4, 4),
|
||
|
|
vc_num_out_vec => (4, 4, 4, 4, 4),
|
||
|
|
vc_depth_array => ((4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4)),
|
||
|
|
vc_depth_out_array => ((4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4)),
|
||
|
|
rout_algo => "DXYU"
|
||
|
|
)
|
||
|
|
port map (
|
||
|
|
clk => clk,
|
||
|
|
rst => rst,
|
||
|
|
data_rx => data_in130,
|
||
|
|
vc_write_rx_vec => vc_write_rx_vec130,
|
||
|
|
incr_rx_vec => incr_rx_vec130,
|
||
|
|
data_tx_pl => data_out130,
|
||
|
|
vc_write_tx_pl_vec => vc_write_tx_pl_vec130,
|
||
|
|
incr_tx_pl_vec => incr_tx_pl_vec130
|
||
|
|
);
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
-- Router port connections to adjacent routers
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
data_in230(0) <= inter_data_in(2)(3)(0)(0);
|
||
|
|
inter_data_out(2)(3)(0)(0) <= data_out230(0) after delay_constant;
|
||
|
|
incr_rx_vec230(4-1 downto 0) <= inter_incr_in(2)(3)(0)(0)(4-1 downto 0);
|
||
|
|
inter_incr_out(2)(3)(0)(0)(4-1 downto 0) <= incr_tx_pl_vec230(4-1 downto 0);
|
||
|
|
vc_write_rx_vec230(4-1 downto 0) <= inter_vc_write_in(2)(3)(0)(0)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(2)(3)(0)(0)(4-1 downto 0) <= vc_write_tx_pl_vec230(4-1 downto 0);
|
||
|
|
data_in230(1) <= inter_data_in(2)(3)(0)(2);
|
||
|
|
inter_data_out(2)(3)(0)(2) <= data_out230(1) after delay_constant;
|
||
|
|
incr_rx_vec230(8-1 downto 4) <= inter_incr_in(2)(3)(0)(2)(4-1 downto 0);
|
||
|
|
inter_incr_out(2)(3)(0)(2)(4-1 downto 0) <= incr_tx_pl_vec230(8-1 downto 4);
|
||
|
|
vc_write_rx_vec230(8-1 downto 4) <= inter_vc_write_in(2)(3)(0)(2)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(2)(3)(0)(2)(4-1 downto 0) <= vc_write_tx_pl_vec230(8-1 downto 4);
|
||
|
|
|
||
|
|
inter_data_in(2)(3)(0)(2) <= inter_data_out(2+1)(3)(0)(4);
|
||
|
|
|
||
|
|
inter_incr_in(2)(3)(0)(2) <= inter_incr_out(2+1)(3)(0)(4);
|
||
|
|
|
||
|
|
inter_vc_write_in(2)(3)(0)(2) <= inter_vc_write_out(2+1)(3)(0)(4);
|
||
|
|
data_in230(2) <= inter_data_in(2)(3)(0)(3);
|
||
|
|
inter_data_out(2)(3)(0)(3) <= data_out230(2) after delay_constant;
|
||
|
|
incr_rx_vec230(12-1 downto 8) <= inter_incr_in(2)(3)(0)(3)(4-1 downto 0);
|
||
|
|
inter_incr_out(2)(3)(0)(3)(4-1 downto 0) <= incr_tx_pl_vec230(12-1 downto 8);
|
||
|
|
vc_write_rx_vec230(12-1 downto 8) <= inter_vc_write_in(2)(3)(0)(3)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(2)(3)(0)(3)(4-1 downto 0) <= vc_write_tx_pl_vec230(12-1 downto 8);
|
||
|
|
|
||
|
|
inter_data_in(2)(3)(0)(3) <= inter_data_out(2)(3-1)(0)(1);
|
||
|
|
|
||
|
|
inter_incr_in(2)(3)(0)(3) <= inter_incr_out(2)(3-1)(0)(1);
|
||
|
|
|
||
|
|
inter_vc_write_in(2)(3)(0)(3) <= inter_vc_write_out(2)(3-1)(0)(1);
|
||
|
|
data_in230(3) <= inter_data_in(2)(3)(0)(4);
|
||
|
|
inter_data_out(2)(3)(0)(4) <= data_out230(3) after delay_constant;
|
||
|
|
incr_rx_vec230(16-1 downto 12) <= inter_incr_in(2)(3)(0)(4)(4-1 downto 0);
|
||
|
|
inter_incr_out(2)(3)(0)(4)(4-1 downto 0) <= incr_tx_pl_vec230(16-1 downto 12);
|
||
|
|
vc_write_rx_vec230(16-1 downto 12) <= inter_vc_write_in(2)(3)(0)(4)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(2)(3)(0)(4)(4-1 downto 0) <= vc_write_tx_pl_vec230(16-1 downto 12);
|
||
|
|
|
||
|
|
inter_data_in(2)(3)(0)(4) <= inter_data_out(2-1)(3)(0)(2);
|
||
|
|
|
||
|
|
inter_incr_in(2)(3)(0)(4) <= inter_incr_out(2-1)(3)(0)(2);
|
||
|
|
|
||
|
|
inter_vc_write_in(2)(3)(0)(4) <= inter_vc_write_out(2-1)(3)(0)(2);
|
||
|
|
data_in230(4) <= inter_data_in(2)(3)(0)(5);
|
||
|
|
inter_data_out(2)(3)(0)(5) <= data_out230(4) after delay_constant;
|
||
|
|
incr_rx_vec230(20-1 downto 16) <= inter_incr_in(2)(3)(0)(5)(4-1 downto 0);
|
||
|
|
inter_incr_out(2)(3)(0)(5)(4-1 downto 0) <= incr_tx_pl_vec230(20-1 downto 16);
|
||
|
|
vc_write_rx_vec230(20-1 downto 16) <= inter_vc_write_in(2)(3)(0)(5)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(2)(3)(0)(5)(4-1 downto 0) <= vc_write_tx_pl_vec230(20-1 downto 16);
|
||
|
|
|
||
|
|
inter_data_in(2)(3)(0)(5) <= inter_data_out(2)(3)(0+1)(6);
|
||
|
|
|
||
|
|
inter_incr_in(2)(3)(0)(5) <= inter_incr_out(2)(3)(0+1)(6);
|
||
|
|
|
||
|
|
inter_vc_write_in(2)(3)(0)(5) <= inter_vc_write_out(2)(3)(0+1)(6);
|
||
|
|
|
||
|
|
inter_data_in(2)(3)(0)(0) <= local_rx(14);
|
||
|
|
local_tx(14) <= inter_data_out(2)(3)(0)(0);
|
||
|
|
|
||
|
|
inter_incr_in(2)(3)(0)(0)(4-1 downto 0) <= local_incr_rx_vec(60-1 downto 56);
|
||
|
|
local_incr_tx_vec(60-1 downto 56) <= inter_incr_out(2)(3)(0)(0)(4-1 downto 0);
|
||
|
|
|
||
|
|
inter_vc_write_in(2)(3)(0)(0)(4-1 downto 0) <= local_vc_write_rx(60-1 downto 56);
|
||
|
|
local_vc_write_tx(60-1 downto 56) <= inter_vc_write_out(2)(3)(0)(0)(4-1 downto 0);
|
||
|
|
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
-- Router at x= 2 y=3 z=0
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
router_230: entity work.router_pl
|
||
|
|
generic map (
|
||
|
|
port_num => 5,
|
||
|
|
Xis => 2,
|
||
|
|
Yis => 3,
|
||
|
|
Zis => 0,
|
||
|
|
header_incl_in_packet_length => true,
|
||
|
|
port_exist => (0,2,3,4,5),
|
||
|
|
vc_num_vec => (4, 4, 4, 4, 4),
|
||
|
|
vc_num_out_vec => (4, 4, 4, 4, 4),
|
||
|
|
vc_depth_array => ((4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4)),
|
||
|
|
vc_depth_out_array => ((4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4)),
|
||
|
|
rout_algo => "DXYU"
|
||
|
|
)
|
||
|
|
port map (
|
||
|
|
clk => clk,
|
||
|
|
rst => rst,
|
||
|
|
data_rx => data_in230,
|
||
|
|
vc_write_rx_vec => vc_write_rx_vec230,
|
||
|
|
incr_rx_vec => incr_rx_vec230,
|
||
|
|
data_tx_pl => data_out230,
|
||
|
|
vc_write_tx_pl_vec => vc_write_tx_pl_vec230,
|
||
|
|
incr_tx_pl_vec => incr_tx_pl_vec230
|
||
|
|
);
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
-- Router port connections to adjacent routers
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
data_in330(0) <= inter_data_in(3)(3)(0)(0);
|
||
|
|
inter_data_out(3)(3)(0)(0) <= data_out330(0) after delay_constant;
|
||
|
|
incr_rx_vec330(4-1 downto 0) <= inter_incr_in(3)(3)(0)(0)(4-1 downto 0);
|
||
|
|
inter_incr_out(3)(3)(0)(0)(4-1 downto 0) <= incr_tx_pl_vec330(4-1 downto 0);
|
||
|
|
vc_write_rx_vec330(4-1 downto 0) <= inter_vc_write_in(3)(3)(0)(0)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(3)(3)(0)(0)(4-1 downto 0) <= vc_write_tx_pl_vec330(4-1 downto 0);
|
||
|
|
data_in330(1) <= inter_data_in(3)(3)(0)(3);
|
||
|
|
inter_data_out(3)(3)(0)(3) <= data_out330(1) after delay_constant;
|
||
|
|
incr_rx_vec330(8-1 downto 4) <= inter_incr_in(3)(3)(0)(3)(4-1 downto 0);
|
||
|
|
inter_incr_out(3)(3)(0)(3)(4-1 downto 0) <= incr_tx_pl_vec330(8-1 downto 4);
|
||
|
|
vc_write_rx_vec330(8-1 downto 4) <= inter_vc_write_in(3)(3)(0)(3)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(3)(3)(0)(3)(4-1 downto 0) <= vc_write_tx_pl_vec330(8-1 downto 4);
|
||
|
|
|
||
|
|
inter_data_in(3)(3)(0)(3) <= inter_data_out(3)(3-1)(0)(1);
|
||
|
|
|
||
|
|
inter_incr_in(3)(3)(0)(3) <= inter_incr_out(3)(3-1)(0)(1);
|
||
|
|
|
||
|
|
inter_vc_write_in(3)(3)(0)(3) <= inter_vc_write_out(3)(3-1)(0)(1);
|
||
|
|
data_in330(2) <= inter_data_in(3)(3)(0)(4);
|
||
|
|
inter_data_out(3)(3)(0)(4) <= data_out330(2) after delay_constant;
|
||
|
|
incr_rx_vec330(12-1 downto 8) <= inter_incr_in(3)(3)(0)(4)(4-1 downto 0);
|
||
|
|
inter_incr_out(3)(3)(0)(4)(4-1 downto 0) <= incr_tx_pl_vec330(12-1 downto 8);
|
||
|
|
vc_write_rx_vec330(12-1 downto 8) <= inter_vc_write_in(3)(3)(0)(4)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(3)(3)(0)(4)(4-1 downto 0) <= vc_write_tx_pl_vec330(12-1 downto 8);
|
||
|
|
|
||
|
|
inter_data_in(3)(3)(0)(4) <= inter_data_out(3-1)(3)(0)(2);
|
||
|
|
|
||
|
|
inter_incr_in(3)(3)(0)(4) <= inter_incr_out(3-1)(3)(0)(2);
|
||
|
|
|
||
|
|
inter_vc_write_in(3)(3)(0)(4) <= inter_vc_write_out(3-1)(3)(0)(2);
|
||
|
|
data_in330(3) <= inter_data_in(3)(3)(0)(5);
|
||
|
|
inter_data_out(3)(3)(0)(5) <= data_out330(3) after delay_constant;
|
||
|
|
incr_rx_vec330(16-1 downto 12) <= inter_incr_in(3)(3)(0)(5)(4-1 downto 0);
|
||
|
|
inter_incr_out(3)(3)(0)(5)(4-1 downto 0) <= incr_tx_pl_vec330(16-1 downto 12);
|
||
|
|
vc_write_rx_vec330(16-1 downto 12) <= inter_vc_write_in(3)(3)(0)(5)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(3)(3)(0)(5)(4-1 downto 0) <= vc_write_tx_pl_vec330(16-1 downto 12);
|
||
|
|
|
||
|
|
inter_data_in(3)(3)(0)(5) <= inter_data_out(3)(3)(0+1)(6);
|
||
|
|
|
||
|
|
inter_incr_in(3)(3)(0)(5) <= inter_incr_out(3)(3)(0+1)(6);
|
||
|
|
|
||
|
|
inter_vc_write_in(3)(3)(0)(5) <= inter_vc_write_out(3)(3)(0+1)(6);
|
||
|
|
|
||
|
|
inter_data_in(3)(3)(0)(0) <= local_rx(15);
|
||
|
|
local_tx(15) <= inter_data_out(3)(3)(0)(0);
|
||
|
|
|
||
|
|
inter_incr_in(3)(3)(0)(0)(4-1 downto 0) <= local_incr_rx_vec(64-1 downto 60);
|
||
|
|
local_incr_tx_vec(64-1 downto 60) <= inter_incr_out(3)(3)(0)(0)(4-1 downto 0);
|
||
|
|
|
||
|
|
inter_vc_write_in(3)(3)(0)(0)(4-1 downto 0) <= local_vc_write_rx(64-1 downto 60);
|
||
|
|
local_vc_write_tx(64-1 downto 60) <= inter_vc_write_out(3)(3)(0)(0)(4-1 downto 0);
|
||
|
|
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
-- Router at x= 3 y=3 z=0
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
router_330: entity work.router_pl
|
||
|
|
generic map (
|
||
|
|
port_num => 4,
|
||
|
|
Xis => 3,
|
||
|
|
Yis => 3,
|
||
|
|
Zis => 0,
|
||
|
|
header_incl_in_packet_length => true,
|
||
|
|
port_exist => (0,3,4,5),
|
||
|
|
vc_num_vec => (4, 4, 4, 4),
|
||
|
|
vc_num_out_vec => (4, 4, 4, 4),
|
||
|
|
vc_depth_array => ((4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4)),
|
||
|
|
vc_depth_out_array => ((4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4)),
|
||
|
|
rout_algo => "DXYU"
|
||
|
|
)
|
||
|
|
port map (
|
||
|
|
clk => clk,
|
||
|
|
rst => rst,
|
||
|
|
data_rx => data_in330,
|
||
|
|
vc_write_rx_vec => vc_write_rx_vec330,
|
||
|
|
incr_rx_vec => incr_rx_vec330,
|
||
|
|
data_tx_pl => data_out330,
|
||
|
|
vc_write_tx_pl_vec => vc_write_tx_pl_vec330,
|
||
|
|
incr_tx_pl_vec => incr_tx_pl_vec330
|
||
|
|
);
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
-- Router port connections to adjacent routers
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
data_in001(0) <= inter_data_in(0)(0)(1)(0);
|
||
|
|
inter_data_out(0)(0)(1)(0) <= data_out001(0);
|
||
|
|
incr_rx_vec001(4-1 downto 0) <= inter_incr_in(0)(0)(1)(0)(4-1 downto 0);
|
||
|
|
inter_incr_out(0)(0)(1)(0)(4-1 downto 0) <= incr_tx_pl_vec001(4-1 downto 0);
|
||
|
|
vc_write_rx_vec001(4-1 downto 0) <= inter_vc_write_in(0)(0)(1)(0)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(0)(0)(1)(0)(4-1 downto 0) <= vc_write_tx_pl_vec001(4-1 downto 0);
|
||
|
|
data_in001(1) <= inter_data_in(0)(0)(1)(1);
|
||
|
|
inter_data_out(0)(0)(1)(1) <= data_out001(1);
|
||
|
|
incr_rx_vec001(8-1 downto 4) <= inter_incr_in(0)(0)(1)(1)(4-1 downto 0);
|
||
|
|
inter_incr_out(0)(0)(1)(1)(4-1 downto 0) <= incr_tx_pl_vec001(8-1 downto 4);
|
||
|
|
vc_write_rx_vec001(8-1 downto 4) <= inter_vc_write_in(0)(0)(1)(1)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(0)(0)(1)(1)(4-1 downto 0) <= vc_write_tx_pl_vec001(8-1 downto 4);
|
||
|
|
|
||
|
|
inter_data_in(0)(0)(1)(1) <= inter_data_out(0)(0+1)(1)(3);
|
||
|
|
|
||
|
|
inter_incr_in(0)(0)(1)(1) <= inter_incr_out(0)(0+1)(1)(3);
|
||
|
|
|
||
|
|
inter_vc_write_in(0)(0)(1)(1) <= inter_vc_write_out(0)(0+1)(1)(3);
|
||
|
|
data_in001(2) <= inter_data_in(0)(0)(1)(2);
|
||
|
|
inter_data_out(0)(0)(1)(2) <= data_out001(2);
|
||
|
|
incr_rx_vec001(12-1 downto 8) <= inter_incr_in(0)(0)(1)(2)(4-1 downto 0);
|
||
|
|
inter_incr_out(0)(0)(1)(2)(4-1 downto 0) <= incr_tx_pl_vec001(12-1 downto 8);
|
||
|
|
vc_write_rx_vec001(12-1 downto 8) <= inter_vc_write_in(0)(0)(1)(2)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(0)(0)(1)(2)(4-1 downto 0) <= vc_write_tx_pl_vec001(12-1 downto 8);
|
||
|
|
|
||
|
|
inter_data_in(0)(0)(1)(2) <= inter_data_out(0+1)(0)(1)(4);
|
||
|
|
|
||
|
|
inter_incr_in(0)(0)(1)(2) <= inter_incr_out(0+1)(0)(1)(4);
|
||
|
|
|
||
|
|
inter_vc_write_in(0)(0)(1)(2) <= inter_vc_write_out(0+1)(0)(1)(4);
|
||
|
|
data_in001(3) <= inter_data_in(0)(0)(1)(5);
|
||
|
|
inter_data_out(0)(0)(1)(5) <= data_out001(3);
|
||
|
|
incr_rx_vec001(16-1 downto 12) <= inter_incr_in(0)(0)(1)(5)(4-1 downto 0);
|
||
|
|
inter_incr_out(0)(0)(1)(5)(4-1 downto 0) <= incr_tx_pl_vec001(16-1 downto 12);
|
||
|
|
vc_write_rx_vec001(16-1 downto 12) <= inter_vc_write_in(0)(0)(1)(5)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(0)(0)(1)(5)(4-1 downto 0) <= vc_write_tx_pl_vec001(16-1 downto 12);
|
||
|
|
|
||
|
|
inter_data_in(0)(0)(1)(5) <= inter_data_out(0)(0)(1+1)(6);
|
||
|
|
|
||
|
|
inter_incr_in(0)(0)(1)(5) <= inter_incr_out(0)(0)(1+1)(6);
|
||
|
|
|
||
|
|
inter_vc_write_in(0)(0)(1)(5) <= inter_vc_write_out(0)(0)(1+1)(6);
|
||
|
|
data_in001(4) <= inter_data_in(0)(0)(1)(6);
|
||
|
|
inter_data_out(0)(0)(1)(6) <= data_out001(4);
|
||
|
|
incr_rx_vec001(20-1 downto 16) <= inter_incr_in(0)(0)(1)(6)(4-1 downto 0);
|
||
|
|
inter_incr_out(0)(0)(1)(6)(4-1 downto 0) <= incr_tx_pl_vec001(20-1 downto 16);
|
||
|
|
vc_write_rx_vec001(20-1 downto 16) <= inter_vc_write_in(0)(0)(1)(6)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(0)(0)(1)(6)(4-1 downto 0) <= vc_write_tx_pl_vec001(20-1 downto 16);
|
||
|
|
|
||
|
|
inter_data_in(0)(0)(1)(6) <= inter_data_out(0)(0)(1-1)(5);
|
||
|
|
|
||
|
|
inter_incr_in(0)(0)(1)(6) <= inter_incr_out(0)(0)(1-1)(5);
|
||
|
|
|
||
|
|
inter_vc_write_in(0)(0)(1)(6) <= inter_vc_write_out(0)(0)(1-1)(5);
|
||
|
|
|
||
|
|
inter_data_in(0)(0)(1)(0) <= local_rx(16);
|
||
|
|
local_tx(16) <= inter_data_out(0)(0)(1)(0);
|
||
|
|
|
||
|
|
inter_incr_in(0)(0)(1)(0)(4-1 downto 0) <= local_incr_rx_vec(68-1 downto 64);
|
||
|
|
local_incr_tx_vec(68-1 downto 64) <= inter_incr_out(0)(0)(1)(0)(4-1 downto 0);
|
||
|
|
|
||
|
|
inter_vc_write_in(0)(0)(1)(0)(4-1 downto 0) <= local_vc_write_rx(68-1 downto 64);
|
||
|
|
local_vc_write_tx(68-1 downto 64) <= inter_vc_write_out(0)(0)(1)(0)(4-1 downto 0);
|
||
|
|
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
-- Router at x= 0 y=0 z=1
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
router_001: entity work.router_pl
|
||
|
|
generic map (
|
||
|
|
port_num => 5,
|
||
|
|
Xis => 0,
|
||
|
|
Yis => 0,
|
||
|
|
Zis => 1,
|
||
|
|
header_incl_in_packet_length => true,
|
||
|
|
port_exist => (0,1,2,5,6),
|
||
|
|
vc_num_vec => (4, 4, 4, 4, 4),
|
||
|
|
vc_num_out_vec => (4, 4, 4, 4, 4),
|
||
|
|
vc_depth_array => ((4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4)),
|
||
|
|
vc_depth_out_array => ((4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4)),
|
||
|
|
rout_algo => "DXYU"
|
||
|
|
)
|
||
|
|
port map (
|
||
|
|
clk => clk,
|
||
|
|
rst => rst,
|
||
|
|
data_rx => data_in001,
|
||
|
|
vc_write_rx_vec => vc_write_rx_vec001,
|
||
|
|
incr_rx_vec => incr_rx_vec001,
|
||
|
|
data_tx_pl => data_out001,
|
||
|
|
vc_write_tx_pl_vec => vc_write_tx_pl_vec001,
|
||
|
|
incr_tx_pl_vec => incr_tx_pl_vec001
|
||
|
|
);
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
-- Router port connections to adjacent routers
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
data_in101(0) <= inter_data_in(1)(0)(1)(0);
|
||
|
|
inter_data_out(1)(0)(1)(0) <= data_out101(0);
|
||
|
|
incr_rx_vec101(4-1 downto 0) <= inter_incr_in(1)(0)(1)(0)(4-1 downto 0);
|
||
|
|
inter_incr_out(1)(0)(1)(0)(4-1 downto 0) <= incr_tx_pl_vec101(4-1 downto 0);
|
||
|
|
vc_write_rx_vec101(4-1 downto 0) <= inter_vc_write_in(1)(0)(1)(0)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(1)(0)(1)(0)(4-1 downto 0) <= vc_write_tx_pl_vec101(4-1 downto 0);
|
||
|
|
data_in101(1) <= inter_data_in(1)(0)(1)(1);
|
||
|
|
inter_data_out(1)(0)(1)(1) <= data_out101(1);
|
||
|
|
incr_rx_vec101(8-1 downto 4) <= inter_incr_in(1)(0)(1)(1)(4-1 downto 0);
|
||
|
|
inter_incr_out(1)(0)(1)(1)(4-1 downto 0) <= incr_tx_pl_vec101(8-1 downto 4);
|
||
|
|
vc_write_rx_vec101(8-1 downto 4) <= inter_vc_write_in(1)(0)(1)(1)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(1)(0)(1)(1)(4-1 downto 0) <= vc_write_tx_pl_vec101(8-1 downto 4);
|
||
|
|
|
||
|
|
inter_data_in(1)(0)(1)(1) <= inter_data_out(1)(0+1)(1)(3);
|
||
|
|
|
||
|
|
inter_incr_in(1)(0)(1)(1) <= inter_incr_out(1)(0+1)(1)(3);
|
||
|
|
|
||
|
|
inter_vc_write_in(1)(0)(1)(1) <= inter_vc_write_out(1)(0+1)(1)(3);
|
||
|
|
data_in101(2) <= inter_data_in(1)(0)(1)(2);
|
||
|
|
inter_data_out(1)(0)(1)(2) <= data_out101(2);
|
||
|
|
incr_rx_vec101(12-1 downto 8) <= inter_incr_in(1)(0)(1)(2)(4-1 downto 0);
|
||
|
|
inter_incr_out(1)(0)(1)(2)(4-1 downto 0) <= incr_tx_pl_vec101(12-1 downto 8);
|
||
|
|
vc_write_rx_vec101(12-1 downto 8) <= inter_vc_write_in(1)(0)(1)(2)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(1)(0)(1)(2)(4-1 downto 0) <= vc_write_tx_pl_vec101(12-1 downto 8);
|
||
|
|
|
||
|
|
inter_data_in(1)(0)(1)(2) <= inter_data_out(1+1)(0)(1)(4);
|
||
|
|
|
||
|
|
inter_incr_in(1)(0)(1)(2) <= inter_incr_out(1+1)(0)(1)(4);
|
||
|
|
|
||
|
|
inter_vc_write_in(1)(0)(1)(2) <= inter_vc_write_out(1+1)(0)(1)(4);
|
||
|
|
data_in101(3) <= inter_data_in(1)(0)(1)(4);
|
||
|
|
inter_data_out(1)(0)(1)(4) <= data_out101(3);
|
||
|
|
incr_rx_vec101(16-1 downto 12) <= inter_incr_in(1)(0)(1)(4)(4-1 downto 0);
|
||
|
|
inter_incr_out(1)(0)(1)(4)(4-1 downto 0) <= incr_tx_pl_vec101(16-1 downto 12);
|
||
|
|
vc_write_rx_vec101(16-1 downto 12) <= inter_vc_write_in(1)(0)(1)(4)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(1)(0)(1)(4)(4-1 downto 0) <= vc_write_tx_pl_vec101(16-1 downto 12);
|
||
|
|
|
||
|
|
inter_data_in(1)(0)(1)(4) <= inter_data_out(1-1)(0)(1)(2);
|
||
|
|
|
||
|
|
inter_incr_in(1)(0)(1)(4) <= inter_incr_out(1-1)(0)(1)(2);
|
||
|
|
|
||
|
|
inter_vc_write_in(1)(0)(1)(4) <= inter_vc_write_out(1-1)(0)(1)(2);
|
||
|
|
data_in101(4) <= inter_data_in(1)(0)(1)(5);
|
||
|
|
inter_data_out(1)(0)(1)(5) <= data_out101(4);
|
||
|
|
incr_rx_vec101(20-1 downto 16) <= inter_incr_in(1)(0)(1)(5)(4-1 downto 0);
|
||
|
|
inter_incr_out(1)(0)(1)(5)(4-1 downto 0) <= incr_tx_pl_vec101(20-1 downto 16);
|
||
|
|
vc_write_rx_vec101(20-1 downto 16) <= inter_vc_write_in(1)(0)(1)(5)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(1)(0)(1)(5)(4-1 downto 0) <= vc_write_tx_pl_vec101(20-1 downto 16);
|
||
|
|
|
||
|
|
inter_data_in(1)(0)(1)(5) <= inter_data_out(1)(0)(1+1)(6);
|
||
|
|
|
||
|
|
inter_incr_in(1)(0)(1)(5) <= inter_incr_out(1)(0)(1+1)(6);
|
||
|
|
|
||
|
|
inter_vc_write_in(1)(0)(1)(5) <= inter_vc_write_out(1)(0)(1+1)(6);
|
||
|
|
data_in101(5) <= inter_data_in(1)(0)(1)(6);
|
||
|
|
inter_data_out(1)(0)(1)(6) <= data_out101(5);
|
||
|
|
incr_rx_vec101(24-1 downto 20) <= inter_incr_in(1)(0)(1)(6)(4-1 downto 0);
|
||
|
|
inter_incr_out(1)(0)(1)(6)(4-1 downto 0) <= incr_tx_pl_vec101(24-1 downto 20);
|
||
|
|
vc_write_rx_vec101(24-1 downto 20) <= inter_vc_write_in(1)(0)(1)(6)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(1)(0)(1)(6)(4-1 downto 0) <= vc_write_tx_pl_vec101(24-1 downto 20);
|
||
|
|
|
||
|
|
inter_data_in(1)(0)(1)(6) <= inter_data_out(1)(0)(1-1)(5);
|
||
|
|
|
||
|
|
inter_incr_in(1)(0)(1)(6) <= inter_incr_out(1)(0)(1-1)(5);
|
||
|
|
|
||
|
|
inter_vc_write_in(1)(0)(1)(6) <= inter_vc_write_out(1)(0)(1-1)(5);
|
||
|
|
|
||
|
|
inter_data_in(1)(0)(1)(0) <= local_rx(17);
|
||
|
|
local_tx(17) <= inter_data_out(1)(0)(1)(0);
|
||
|
|
|
||
|
|
inter_incr_in(1)(0)(1)(0)(4-1 downto 0) <= local_incr_rx_vec(72-1 downto 68);
|
||
|
|
local_incr_tx_vec(72-1 downto 68) <= inter_incr_out(1)(0)(1)(0)(4-1 downto 0);
|
||
|
|
|
||
|
|
inter_vc_write_in(1)(0)(1)(0)(4-1 downto 0) <= local_vc_write_rx(72-1 downto 68);
|
||
|
|
local_vc_write_tx(72-1 downto 68) <= inter_vc_write_out(1)(0)(1)(0)(4-1 downto 0);
|
||
|
|
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
-- Router at x= 1 y=0 z=1
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
router_101: entity work.router_pl
|
||
|
|
generic map (
|
||
|
|
port_num => 6,
|
||
|
|
Xis => 1,
|
||
|
|
Yis => 0,
|
||
|
|
Zis => 1,
|
||
|
|
header_incl_in_packet_length => true,
|
||
|
|
port_exist => (0,1,2,4,5,6),
|
||
|
|
vc_num_vec => (4, 4, 4, 4, 4, 4),
|
||
|
|
vc_num_out_vec => (4, 4, 4, 4, 4, 4),
|
||
|
|
vc_depth_array => ((4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4)),
|
||
|
|
vc_depth_out_array => ((4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4)),
|
||
|
|
rout_algo => "DXYU"
|
||
|
|
)
|
||
|
|
port map (
|
||
|
|
clk => clk,
|
||
|
|
rst => rst,
|
||
|
|
data_rx => data_in101,
|
||
|
|
vc_write_rx_vec => vc_write_rx_vec101,
|
||
|
|
incr_rx_vec => incr_rx_vec101,
|
||
|
|
data_tx_pl => data_out101,
|
||
|
|
vc_write_tx_pl_vec => vc_write_tx_pl_vec101,
|
||
|
|
incr_tx_pl_vec => incr_tx_pl_vec101
|
||
|
|
);
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
-- Router port connections to adjacent routers
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
data_in201(0) <= inter_data_in(2)(0)(1)(0);
|
||
|
|
inter_data_out(2)(0)(1)(0) <= data_out201(0);
|
||
|
|
incr_rx_vec201(4-1 downto 0) <= inter_incr_in(2)(0)(1)(0)(4-1 downto 0);
|
||
|
|
inter_incr_out(2)(0)(1)(0)(4-1 downto 0) <= incr_tx_pl_vec201(4-1 downto 0);
|
||
|
|
vc_write_rx_vec201(4-1 downto 0) <= inter_vc_write_in(2)(0)(1)(0)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(2)(0)(1)(0)(4-1 downto 0) <= vc_write_tx_pl_vec201(4-1 downto 0);
|
||
|
|
data_in201(1) <= inter_data_in(2)(0)(1)(1);
|
||
|
|
inter_data_out(2)(0)(1)(1) <= data_out201(1);
|
||
|
|
incr_rx_vec201(8-1 downto 4) <= inter_incr_in(2)(0)(1)(1)(4-1 downto 0);
|
||
|
|
inter_incr_out(2)(0)(1)(1)(4-1 downto 0) <= incr_tx_pl_vec201(8-1 downto 4);
|
||
|
|
vc_write_rx_vec201(8-1 downto 4) <= inter_vc_write_in(2)(0)(1)(1)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(2)(0)(1)(1)(4-1 downto 0) <= vc_write_tx_pl_vec201(8-1 downto 4);
|
||
|
|
|
||
|
|
inter_data_in(2)(0)(1)(1) <= inter_data_out(2)(0+1)(1)(3);
|
||
|
|
|
||
|
|
inter_incr_in(2)(0)(1)(1) <= inter_incr_out(2)(0+1)(1)(3);
|
||
|
|
|
||
|
|
inter_vc_write_in(2)(0)(1)(1) <= inter_vc_write_out(2)(0+1)(1)(3);
|
||
|
|
data_in201(2) <= inter_data_in(2)(0)(1)(2);
|
||
|
|
inter_data_out(2)(0)(1)(2) <= data_out201(2);
|
||
|
|
incr_rx_vec201(12-1 downto 8) <= inter_incr_in(2)(0)(1)(2)(4-1 downto 0);
|
||
|
|
inter_incr_out(2)(0)(1)(2)(4-1 downto 0) <= incr_tx_pl_vec201(12-1 downto 8);
|
||
|
|
vc_write_rx_vec201(12-1 downto 8) <= inter_vc_write_in(2)(0)(1)(2)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(2)(0)(1)(2)(4-1 downto 0) <= vc_write_tx_pl_vec201(12-1 downto 8);
|
||
|
|
|
||
|
|
inter_data_in(2)(0)(1)(2) <= inter_data_out(2+1)(0)(1)(4);
|
||
|
|
|
||
|
|
inter_incr_in(2)(0)(1)(2) <= inter_incr_out(2+1)(0)(1)(4);
|
||
|
|
|
||
|
|
inter_vc_write_in(2)(0)(1)(2) <= inter_vc_write_out(2+1)(0)(1)(4);
|
||
|
|
data_in201(3) <= inter_data_in(2)(0)(1)(4);
|
||
|
|
inter_data_out(2)(0)(1)(4) <= data_out201(3);
|
||
|
|
incr_rx_vec201(16-1 downto 12) <= inter_incr_in(2)(0)(1)(4)(4-1 downto 0);
|
||
|
|
inter_incr_out(2)(0)(1)(4)(4-1 downto 0) <= incr_tx_pl_vec201(16-1 downto 12);
|
||
|
|
vc_write_rx_vec201(16-1 downto 12) <= inter_vc_write_in(2)(0)(1)(4)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(2)(0)(1)(4)(4-1 downto 0) <= vc_write_tx_pl_vec201(16-1 downto 12);
|
||
|
|
|
||
|
|
inter_data_in(2)(0)(1)(4) <= inter_data_out(2-1)(0)(1)(2);
|
||
|
|
|
||
|
|
inter_incr_in(2)(0)(1)(4) <= inter_incr_out(2-1)(0)(1)(2);
|
||
|
|
|
||
|
|
inter_vc_write_in(2)(0)(1)(4) <= inter_vc_write_out(2-1)(0)(1)(2);
|
||
|
|
data_in201(4) <= inter_data_in(2)(0)(1)(5);
|
||
|
|
inter_data_out(2)(0)(1)(5) <= data_out201(4);
|
||
|
|
incr_rx_vec201(20-1 downto 16) <= inter_incr_in(2)(0)(1)(5)(4-1 downto 0);
|
||
|
|
inter_incr_out(2)(0)(1)(5)(4-1 downto 0) <= incr_tx_pl_vec201(20-1 downto 16);
|
||
|
|
vc_write_rx_vec201(20-1 downto 16) <= inter_vc_write_in(2)(0)(1)(5)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(2)(0)(1)(5)(4-1 downto 0) <= vc_write_tx_pl_vec201(20-1 downto 16);
|
||
|
|
|
||
|
|
inter_data_in(2)(0)(1)(5) <= inter_data_out(2)(0)(1+1)(6);
|
||
|
|
|
||
|
|
inter_incr_in(2)(0)(1)(5) <= inter_incr_out(2)(0)(1+1)(6);
|
||
|
|
|
||
|
|
inter_vc_write_in(2)(0)(1)(5) <= inter_vc_write_out(2)(0)(1+1)(6);
|
||
|
|
data_in201(5) <= inter_data_in(2)(0)(1)(6);
|
||
|
|
inter_data_out(2)(0)(1)(6) <= data_out201(5);
|
||
|
|
incr_rx_vec201(24-1 downto 20) <= inter_incr_in(2)(0)(1)(6)(4-1 downto 0);
|
||
|
|
inter_incr_out(2)(0)(1)(6)(4-1 downto 0) <= incr_tx_pl_vec201(24-1 downto 20);
|
||
|
|
vc_write_rx_vec201(24-1 downto 20) <= inter_vc_write_in(2)(0)(1)(6)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(2)(0)(1)(6)(4-1 downto 0) <= vc_write_tx_pl_vec201(24-1 downto 20);
|
||
|
|
|
||
|
|
inter_data_in(2)(0)(1)(6) <= inter_data_out(2)(0)(1-1)(5);
|
||
|
|
|
||
|
|
inter_incr_in(2)(0)(1)(6) <= inter_incr_out(2)(0)(1-1)(5);
|
||
|
|
|
||
|
|
inter_vc_write_in(2)(0)(1)(6) <= inter_vc_write_out(2)(0)(1-1)(5);
|
||
|
|
|
||
|
|
inter_data_in(2)(0)(1)(0) <= local_rx(18);
|
||
|
|
local_tx(18) <= inter_data_out(2)(0)(1)(0);
|
||
|
|
|
||
|
|
inter_incr_in(2)(0)(1)(0)(4-1 downto 0) <= local_incr_rx_vec(76-1 downto 72);
|
||
|
|
local_incr_tx_vec(76-1 downto 72) <= inter_incr_out(2)(0)(1)(0)(4-1 downto 0);
|
||
|
|
|
||
|
|
inter_vc_write_in(2)(0)(1)(0)(4-1 downto 0) <= local_vc_write_rx(76-1 downto 72);
|
||
|
|
local_vc_write_tx(76-1 downto 72) <= inter_vc_write_out(2)(0)(1)(0)(4-1 downto 0);
|
||
|
|
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
-- Router at x= 2 y=0 z=1
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
router_201: entity work.router_pl
|
||
|
|
generic map (
|
||
|
|
port_num => 6,
|
||
|
|
Xis => 2,
|
||
|
|
Yis => 0,
|
||
|
|
Zis => 1,
|
||
|
|
header_incl_in_packet_length => true,
|
||
|
|
port_exist => (0,1,2,4,5,6),
|
||
|
|
vc_num_vec => (4, 4, 4, 4, 4, 4),
|
||
|
|
vc_num_out_vec => (4, 4, 4, 4, 4, 4),
|
||
|
|
vc_depth_array => ((4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4)),
|
||
|
|
vc_depth_out_array => ((4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4)),
|
||
|
|
rout_algo => "DXYU"
|
||
|
|
)
|
||
|
|
port map (
|
||
|
|
clk => clk,
|
||
|
|
rst => rst,
|
||
|
|
data_rx => data_in201,
|
||
|
|
vc_write_rx_vec => vc_write_rx_vec201,
|
||
|
|
incr_rx_vec => incr_rx_vec201,
|
||
|
|
data_tx_pl => data_out201,
|
||
|
|
vc_write_tx_pl_vec => vc_write_tx_pl_vec201,
|
||
|
|
incr_tx_pl_vec => incr_tx_pl_vec201
|
||
|
|
);
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
-- Router port connections to adjacent routers
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
data_in301(0) <= inter_data_in(3)(0)(1)(0);
|
||
|
|
inter_data_out(3)(0)(1)(0) <= data_out301(0);
|
||
|
|
incr_rx_vec301(4-1 downto 0) <= inter_incr_in(3)(0)(1)(0)(4-1 downto 0);
|
||
|
|
inter_incr_out(3)(0)(1)(0)(4-1 downto 0) <= incr_tx_pl_vec301(4-1 downto 0);
|
||
|
|
vc_write_rx_vec301(4-1 downto 0) <= inter_vc_write_in(3)(0)(1)(0)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(3)(0)(1)(0)(4-1 downto 0) <= vc_write_tx_pl_vec301(4-1 downto 0);
|
||
|
|
data_in301(1) <= inter_data_in(3)(0)(1)(1);
|
||
|
|
inter_data_out(3)(0)(1)(1) <= data_out301(1);
|
||
|
|
incr_rx_vec301(8-1 downto 4) <= inter_incr_in(3)(0)(1)(1)(4-1 downto 0);
|
||
|
|
inter_incr_out(3)(0)(1)(1)(4-1 downto 0) <= incr_tx_pl_vec301(8-1 downto 4);
|
||
|
|
vc_write_rx_vec301(8-1 downto 4) <= inter_vc_write_in(3)(0)(1)(1)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(3)(0)(1)(1)(4-1 downto 0) <= vc_write_tx_pl_vec301(8-1 downto 4);
|
||
|
|
|
||
|
|
inter_data_in(3)(0)(1)(1) <= inter_data_out(3)(0+1)(1)(3);
|
||
|
|
|
||
|
|
inter_incr_in(3)(0)(1)(1) <= inter_incr_out(3)(0+1)(1)(3);
|
||
|
|
|
||
|
|
inter_vc_write_in(3)(0)(1)(1) <= inter_vc_write_out(3)(0+1)(1)(3);
|
||
|
|
data_in301(2) <= inter_data_in(3)(0)(1)(4);
|
||
|
|
inter_data_out(3)(0)(1)(4) <= data_out301(2);
|
||
|
|
incr_rx_vec301(12-1 downto 8) <= inter_incr_in(3)(0)(1)(4)(4-1 downto 0);
|
||
|
|
inter_incr_out(3)(0)(1)(4)(4-1 downto 0) <= incr_tx_pl_vec301(12-1 downto 8);
|
||
|
|
vc_write_rx_vec301(12-1 downto 8) <= inter_vc_write_in(3)(0)(1)(4)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(3)(0)(1)(4)(4-1 downto 0) <= vc_write_tx_pl_vec301(12-1 downto 8);
|
||
|
|
|
||
|
|
inter_data_in(3)(0)(1)(4) <= inter_data_out(3-1)(0)(1)(2);
|
||
|
|
|
||
|
|
inter_incr_in(3)(0)(1)(4) <= inter_incr_out(3-1)(0)(1)(2);
|
||
|
|
|
||
|
|
inter_vc_write_in(3)(0)(1)(4) <= inter_vc_write_out(3-1)(0)(1)(2);
|
||
|
|
data_in301(3) <= inter_data_in(3)(0)(1)(5);
|
||
|
|
inter_data_out(3)(0)(1)(5) <= data_out301(3);
|
||
|
|
incr_rx_vec301(16-1 downto 12) <= inter_incr_in(3)(0)(1)(5)(4-1 downto 0);
|
||
|
|
inter_incr_out(3)(0)(1)(5)(4-1 downto 0) <= incr_tx_pl_vec301(16-1 downto 12);
|
||
|
|
vc_write_rx_vec301(16-1 downto 12) <= inter_vc_write_in(3)(0)(1)(5)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(3)(0)(1)(5)(4-1 downto 0) <= vc_write_tx_pl_vec301(16-1 downto 12);
|
||
|
|
|
||
|
|
inter_data_in(3)(0)(1)(5) <= inter_data_out(3)(0)(1+1)(6);
|
||
|
|
|
||
|
|
inter_incr_in(3)(0)(1)(5) <= inter_incr_out(3)(0)(1+1)(6);
|
||
|
|
|
||
|
|
inter_vc_write_in(3)(0)(1)(5) <= inter_vc_write_out(3)(0)(1+1)(6);
|
||
|
|
data_in301(4) <= inter_data_in(3)(0)(1)(6);
|
||
|
|
inter_data_out(3)(0)(1)(6) <= data_out301(4);
|
||
|
|
incr_rx_vec301(20-1 downto 16) <= inter_incr_in(3)(0)(1)(6)(4-1 downto 0);
|
||
|
|
inter_incr_out(3)(0)(1)(6)(4-1 downto 0) <= incr_tx_pl_vec301(20-1 downto 16);
|
||
|
|
vc_write_rx_vec301(20-1 downto 16) <= inter_vc_write_in(3)(0)(1)(6)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(3)(0)(1)(6)(4-1 downto 0) <= vc_write_tx_pl_vec301(20-1 downto 16);
|
||
|
|
|
||
|
|
inter_data_in(3)(0)(1)(6) <= inter_data_out(3)(0)(1-1)(5);
|
||
|
|
|
||
|
|
inter_incr_in(3)(0)(1)(6) <= inter_incr_out(3)(0)(1-1)(5);
|
||
|
|
|
||
|
|
inter_vc_write_in(3)(0)(1)(6) <= inter_vc_write_out(3)(0)(1-1)(5);
|
||
|
|
|
||
|
|
inter_data_in(3)(0)(1)(0) <= local_rx(19);
|
||
|
|
local_tx(19) <= inter_data_out(3)(0)(1)(0);
|
||
|
|
|
||
|
|
inter_incr_in(3)(0)(1)(0)(4-1 downto 0) <= local_incr_rx_vec(80-1 downto 76);
|
||
|
|
local_incr_tx_vec(80-1 downto 76) <= inter_incr_out(3)(0)(1)(0)(4-1 downto 0);
|
||
|
|
|
||
|
|
inter_vc_write_in(3)(0)(1)(0)(4-1 downto 0) <= local_vc_write_rx(80-1 downto 76);
|
||
|
|
local_vc_write_tx(80-1 downto 76) <= inter_vc_write_out(3)(0)(1)(0)(4-1 downto 0);
|
||
|
|
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
-- Router at x= 3 y=0 z=1
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
router_301: entity work.router_pl
|
||
|
|
generic map (
|
||
|
|
port_num => 5,
|
||
|
|
Xis => 3,
|
||
|
|
Yis => 0,
|
||
|
|
Zis => 1,
|
||
|
|
header_incl_in_packet_length => true,
|
||
|
|
port_exist => (0,1,4,5,6),
|
||
|
|
vc_num_vec => (4, 4, 4, 4, 4),
|
||
|
|
vc_num_out_vec => (4, 4, 4, 4, 4),
|
||
|
|
vc_depth_array => ((4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4)),
|
||
|
|
vc_depth_out_array => ((4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4)),
|
||
|
|
rout_algo => "DXYU"
|
||
|
|
)
|
||
|
|
port map (
|
||
|
|
clk => clk,
|
||
|
|
rst => rst,
|
||
|
|
data_rx => data_in301,
|
||
|
|
vc_write_rx_vec => vc_write_rx_vec301,
|
||
|
|
incr_rx_vec => incr_rx_vec301,
|
||
|
|
data_tx_pl => data_out301,
|
||
|
|
vc_write_tx_pl_vec => vc_write_tx_pl_vec301,
|
||
|
|
incr_tx_pl_vec => incr_tx_pl_vec301
|
||
|
|
);
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
-- Router port connections to adjacent routers
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
data_in011(0) <= inter_data_in(0)(1)(1)(0);
|
||
|
|
inter_data_out(0)(1)(1)(0) <= data_out011(0);
|
||
|
|
incr_rx_vec011(4-1 downto 0) <= inter_incr_in(0)(1)(1)(0)(4-1 downto 0);
|
||
|
|
inter_incr_out(0)(1)(1)(0)(4-1 downto 0) <= incr_tx_pl_vec011(4-1 downto 0);
|
||
|
|
vc_write_rx_vec011(4-1 downto 0) <= inter_vc_write_in(0)(1)(1)(0)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(0)(1)(1)(0)(4-1 downto 0) <= vc_write_tx_pl_vec011(4-1 downto 0);
|
||
|
|
data_in011(1) <= inter_data_in(0)(1)(1)(1);
|
||
|
|
inter_data_out(0)(1)(1)(1) <= data_out011(1);
|
||
|
|
incr_rx_vec011(8-1 downto 4) <= inter_incr_in(0)(1)(1)(1)(4-1 downto 0);
|
||
|
|
inter_incr_out(0)(1)(1)(1)(4-1 downto 0) <= incr_tx_pl_vec011(8-1 downto 4);
|
||
|
|
vc_write_rx_vec011(8-1 downto 4) <= inter_vc_write_in(0)(1)(1)(1)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(0)(1)(1)(1)(4-1 downto 0) <= vc_write_tx_pl_vec011(8-1 downto 4);
|
||
|
|
|
||
|
|
inter_data_in(0)(1)(1)(1) <= inter_data_out(0)(1+1)(1)(3);
|
||
|
|
|
||
|
|
inter_incr_in(0)(1)(1)(1) <= inter_incr_out(0)(1+1)(1)(3);
|
||
|
|
|
||
|
|
inter_vc_write_in(0)(1)(1)(1) <= inter_vc_write_out(0)(1+1)(1)(3);
|
||
|
|
data_in011(2) <= inter_data_in(0)(1)(1)(2);
|
||
|
|
inter_data_out(0)(1)(1)(2) <= data_out011(2);
|
||
|
|
incr_rx_vec011(12-1 downto 8) <= inter_incr_in(0)(1)(1)(2)(4-1 downto 0);
|
||
|
|
inter_incr_out(0)(1)(1)(2)(4-1 downto 0) <= incr_tx_pl_vec011(12-1 downto 8);
|
||
|
|
vc_write_rx_vec011(12-1 downto 8) <= inter_vc_write_in(0)(1)(1)(2)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(0)(1)(1)(2)(4-1 downto 0) <= vc_write_tx_pl_vec011(12-1 downto 8);
|
||
|
|
|
||
|
|
inter_data_in(0)(1)(1)(2) <= inter_data_out(0+1)(1)(1)(4);
|
||
|
|
|
||
|
|
inter_incr_in(0)(1)(1)(2) <= inter_incr_out(0+1)(1)(1)(4);
|
||
|
|
|
||
|
|
inter_vc_write_in(0)(1)(1)(2) <= inter_vc_write_out(0+1)(1)(1)(4);
|
||
|
|
data_in011(3) <= inter_data_in(0)(1)(1)(3);
|
||
|
|
inter_data_out(0)(1)(1)(3) <= data_out011(3);
|
||
|
|
incr_rx_vec011(16-1 downto 12) <= inter_incr_in(0)(1)(1)(3)(4-1 downto 0);
|
||
|
|
inter_incr_out(0)(1)(1)(3)(4-1 downto 0) <= incr_tx_pl_vec011(16-1 downto 12);
|
||
|
|
vc_write_rx_vec011(16-1 downto 12) <= inter_vc_write_in(0)(1)(1)(3)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(0)(1)(1)(3)(4-1 downto 0) <= vc_write_tx_pl_vec011(16-1 downto 12);
|
||
|
|
|
||
|
|
inter_data_in(0)(1)(1)(3) <= inter_data_out(0)(1-1)(1)(1);
|
||
|
|
|
||
|
|
inter_incr_in(0)(1)(1)(3) <= inter_incr_out(0)(1-1)(1)(1);
|
||
|
|
|
||
|
|
inter_vc_write_in(0)(1)(1)(3) <= inter_vc_write_out(0)(1-1)(1)(1);
|
||
|
|
data_in011(4) <= inter_data_in(0)(1)(1)(5);
|
||
|
|
inter_data_out(0)(1)(1)(5) <= data_out011(4);
|
||
|
|
incr_rx_vec011(20-1 downto 16) <= inter_incr_in(0)(1)(1)(5)(4-1 downto 0);
|
||
|
|
inter_incr_out(0)(1)(1)(5)(4-1 downto 0) <= incr_tx_pl_vec011(20-1 downto 16);
|
||
|
|
vc_write_rx_vec011(20-1 downto 16) <= inter_vc_write_in(0)(1)(1)(5)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(0)(1)(1)(5)(4-1 downto 0) <= vc_write_tx_pl_vec011(20-1 downto 16);
|
||
|
|
|
||
|
|
inter_data_in(0)(1)(1)(5) <= inter_data_out(0)(1)(1+1)(6);
|
||
|
|
|
||
|
|
inter_incr_in(0)(1)(1)(5) <= inter_incr_out(0)(1)(1+1)(6);
|
||
|
|
|
||
|
|
inter_vc_write_in(0)(1)(1)(5) <= inter_vc_write_out(0)(1)(1+1)(6);
|
||
|
|
data_in011(5) <= inter_data_in(0)(1)(1)(6);
|
||
|
|
inter_data_out(0)(1)(1)(6) <= data_out011(5);
|
||
|
|
incr_rx_vec011(24-1 downto 20) <= inter_incr_in(0)(1)(1)(6)(4-1 downto 0);
|
||
|
|
inter_incr_out(0)(1)(1)(6)(4-1 downto 0) <= incr_tx_pl_vec011(24-1 downto 20);
|
||
|
|
vc_write_rx_vec011(24-1 downto 20) <= inter_vc_write_in(0)(1)(1)(6)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(0)(1)(1)(6)(4-1 downto 0) <= vc_write_tx_pl_vec011(24-1 downto 20);
|
||
|
|
|
||
|
|
inter_data_in(0)(1)(1)(6) <= inter_data_out(0)(1)(1-1)(5);
|
||
|
|
|
||
|
|
inter_incr_in(0)(1)(1)(6) <= inter_incr_out(0)(1)(1-1)(5);
|
||
|
|
|
||
|
|
inter_vc_write_in(0)(1)(1)(6) <= inter_vc_write_out(0)(1)(1-1)(5);
|
||
|
|
|
||
|
|
inter_data_in(0)(1)(1)(0) <= local_rx(20);
|
||
|
|
local_tx(20) <= inter_data_out(0)(1)(1)(0);
|
||
|
|
|
||
|
|
inter_incr_in(0)(1)(1)(0)(4-1 downto 0) <= local_incr_rx_vec(84-1 downto 80);
|
||
|
|
local_incr_tx_vec(84-1 downto 80) <= inter_incr_out(0)(1)(1)(0)(4-1 downto 0);
|
||
|
|
|
||
|
|
inter_vc_write_in(0)(1)(1)(0)(4-1 downto 0) <= local_vc_write_rx(84-1 downto 80);
|
||
|
|
local_vc_write_tx(84-1 downto 80) <= inter_vc_write_out(0)(1)(1)(0)(4-1 downto 0);
|
||
|
|
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
-- Router at x= 0 y=1 z=1
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
router_011: entity work.router_pl
|
||
|
|
generic map (
|
||
|
|
port_num => 6,
|
||
|
|
Xis => 0,
|
||
|
|
Yis => 1,
|
||
|
|
Zis => 1,
|
||
|
|
header_incl_in_packet_length => true,
|
||
|
|
port_exist => (0,1,2,3,5,6),
|
||
|
|
vc_num_vec => (4, 4, 4, 4, 4, 4),
|
||
|
|
vc_num_out_vec => (4, 4, 4, 4, 4, 4),
|
||
|
|
vc_depth_array => ((4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4)),
|
||
|
|
vc_depth_out_array => ((4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4)),
|
||
|
|
rout_algo => "DXYU"
|
||
|
|
)
|
||
|
|
port map (
|
||
|
|
clk => clk,
|
||
|
|
rst => rst,
|
||
|
|
data_rx => data_in011,
|
||
|
|
vc_write_rx_vec => vc_write_rx_vec011,
|
||
|
|
incr_rx_vec => incr_rx_vec011,
|
||
|
|
data_tx_pl => data_out011,
|
||
|
|
vc_write_tx_pl_vec => vc_write_tx_pl_vec011,
|
||
|
|
incr_tx_pl_vec => incr_tx_pl_vec011
|
||
|
|
);
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
-- Router port connections to adjacent routers
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
data_in111(0) <= inter_data_in(1)(1)(1)(0);
|
||
|
|
inter_data_out(1)(1)(1)(0) <= data_out111(0);
|
||
|
|
incr_rx_vec111(4-1 downto 0) <= inter_incr_in(1)(1)(1)(0)(4-1 downto 0);
|
||
|
|
inter_incr_out(1)(1)(1)(0)(4-1 downto 0) <= incr_tx_pl_vec111(4-1 downto 0);
|
||
|
|
vc_write_rx_vec111(4-1 downto 0) <= inter_vc_write_in(1)(1)(1)(0)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(1)(1)(1)(0)(4-1 downto 0) <= vc_write_tx_pl_vec111(4-1 downto 0);
|
||
|
|
data_in111(1) <= inter_data_in(1)(1)(1)(1);
|
||
|
|
inter_data_out(1)(1)(1)(1) <= data_out111(1);
|
||
|
|
incr_rx_vec111(8-1 downto 4) <= inter_incr_in(1)(1)(1)(1)(4-1 downto 0);
|
||
|
|
inter_incr_out(1)(1)(1)(1)(4-1 downto 0) <= incr_tx_pl_vec111(8-1 downto 4);
|
||
|
|
vc_write_rx_vec111(8-1 downto 4) <= inter_vc_write_in(1)(1)(1)(1)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(1)(1)(1)(1)(4-1 downto 0) <= vc_write_tx_pl_vec111(8-1 downto 4);
|
||
|
|
|
||
|
|
inter_data_in(1)(1)(1)(1) <= inter_data_out(1)(1+1)(1)(3);
|
||
|
|
|
||
|
|
inter_incr_in(1)(1)(1)(1) <= inter_incr_out(1)(1+1)(1)(3);
|
||
|
|
|
||
|
|
inter_vc_write_in(1)(1)(1)(1) <= inter_vc_write_out(1)(1+1)(1)(3);
|
||
|
|
data_in111(2) <= inter_data_in(1)(1)(1)(2);
|
||
|
|
inter_data_out(1)(1)(1)(2) <= data_out111(2);
|
||
|
|
incr_rx_vec111(12-1 downto 8) <= inter_incr_in(1)(1)(1)(2)(4-1 downto 0);
|
||
|
|
inter_incr_out(1)(1)(1)(2)(4-1 downto 0) <= incr_tx_pl_vec111(12-1 downto 8);
|
||
|
|
vc_write_rx_vec111(12-1 downto 8) <= inter_vc_write_in(1)(1)(1)(2)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(1)(1)(1)(2)(4-1 downto 0) <= vc_write_tx_pl_vec111(12-1 downto 8);
|
||
|
|
|
||
|
|
inter_data_in(1)(1)(1)(2) <= inter_data_out(1+1)(1)(1)(4);
|
||
|
|
|
||
|
|
inter_incr_in(1)(1)(1)(2) <= inter_incr_out(1+1)(1)(1)(4);
|
||
|
|
|
||
|
|
inter_vc_write_in(1)(1)(1)(2) <= inter_vc_write_out(1+1)(1)(1)(4);
|
||
|
|
data_in111(3) <= inter_data_in(1)(1)(1)(3);
|
||
|
|
inter_data_out(1)(1)(1)(3) <= data_out111(3);
|
||
|
|
incr_rx_vec111(16-1 downto 12) <= inter_incr_in(1)(1)(1)(3)(4-1 downto 0);
|
||
|
|
inter_incr_out(1)(1)(1)(3)(4-1 downto 0) <= incr_tx_pl_vec111(16-1 downto 12);
|
||
|
|
vc_write_rx_vec111(16-1 downto 12) <= inter_vc_write_in(1)(1)(1)(3)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(1)(1)(1)(3)(4-1 downto 0) <= vc_write_tx_pl_vec111(16-1 downto 12);
|
||
|
|
|
||
|
|
inter_data_in(1)(1)(1)(3) <= inter_data_out(1)(1-1)(1)(1);
|
||
|
|
|
||
|
|
inter_incr_in(1)(1)(1)(3) <= inter_incr_out(1)(1-1)(1)(1);
|
||
|
|
|
||
|
|
inter_vc_write_in(1)(1)(1)(3) <= inter_vc_write_out(1)(1-1)(1)(1);
|
||
|
|
data_in111(4) <= inter_data_in(1)(1)(1)(4);
|
||
|
|
inter_data_out(1)(1)(1)(4) <= data_out111(4);
|
||
|
|
incr_rx_vec111(20-1 downto 16) <= inter_incr_in(1)(1)(1)(4)(4-1 downto 0);
|
||
|
|
inter_incr_out(1)(1)(1)(4)(4-1 downto 0) <= incr_tx_pl_vec111(20-1 downto 16);
|
||
|
|
vc_write_rx_vec111(20-1 downto 16) <= inter_vc_write_in(1)(1)(1)(4)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(1)(1)(1)(4)(4-1 downto 0) <= vc_write_tx_pl_vec111(20-1 downto 16);
|
||
|
|
|
||
|
|
inter_data_in(1)(1)(1)(4) <= inter_data_out(1-1)(1)(1)(2);
|
||
|
|
|
||
|
|
inter_incr_in(1)(1)(1)(4) <= inter_incr_out(1-1)(1)(1)(2);
|
||
|
|
|
||
|
|
inter_vc_write_in(1)(1)(1)(4) <= inter_vc_write_out(1-1)(1)(1)(2);
|
||
|
|
data_in111(5) <= inter_data_in(1)(1)(1)(5);
|
||
|
|
inter_data_out(1)(1)(1)(5) <= data_out111(5);
|
||
|
|
incr_rx_vec111(24-1 downto 20) <= inter_incr_in(1)(1)(1)(5)(4-1 downto 0);
|
||
|
|
inter_incr_out(1)(1)(1)(5)(4-1 downto 0) <= incr_tx_pl_vec111(24-1 downto 20);
|
||
|
|
vc_write_rx_vec111(24-1 downto 20) <= inter_vc_write_in(1)(1)(1)(5)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(1)(1)(1)(5)(4-1 downto 0) <= vc_write_tx_pl_vec111(24-1 downto 20);
|
||
|
|
|
||
|
|
inter_data_in(1)(1)(1)(5) <= inter_data_out(1)(1)(1+1)(6);
|
||
|
|
|
||
|
|
inter_incr_in(1)(1)(1)(5) <= inter_incr_out(1)(1)(1+1)(6);
|
||
|
|
|
||
|
|
inter_vc_write_in(1)(1)(1)(5) <= inter_vc_write_out(1)(1)(1+1)(6);
|
||
|
|
data_in111(6) <= inter_data_in(1)(1)(1)(6);
|
||
|
|
inter_data_out(1)(1)(1)(6) <= data_out111(6);
|
||
|
|
incr_rx_vec111(28-1 downto 24) <= inter_incr_in(1)(1)(1)(6)(4-1 downto 0);
|
||
|
|
inter_incr_out(1)(1)(1)(6)(4-1 downto 0) <= incr_tx_pl_vec111(28-1 downto 24);
|
||
|
|
vc_write_rx_vec111(28-1 downto 24) <= inter_vc_write_in(1)(1)(1)(6)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(1)(1)(1)(6)(4-1 downto 0) <= vc_write_tx_pl_vec111(28-1 downto 24);
|
||
|
|
|
||
|
|
inter_data_in(1)(1)(1)(6) <= inter_data_out(1)(1)(1-1)(5);
|
||
|
|
|
||
|
|
inter_incr_in(1)(1)(1)(6) <= inter_incr_out(1)(1)(1-1)(5);
|
||
|
|
|
||
|
|
inter_vc_write_in(1)(1)(1)(6) <= inter_vc_write_out(1)(1)(1-1)(5);
|
||
|
|
|
||
|
|
inter_data_in(1)(1)(1)(0) <= local_rx(21);
|
||
|
|
local_tx(21) <= inter_data_out(1)(1)(1)(0);
|
||
|
|
|
||
|
|
inter_incr_in(1)(1)(1)(0)(4-1 downto 0) <= local_incr_rx_vec(88-1 downto 84);
|
||
|
|
local_incr_tx_vec(88-1 downto 84) <= inter_incr_out(1)(1)(1)(0)(4-1 downto 0);
|
||
|
|
|
||
|
|
inter_vc_write_in(1)(1)(1)(0)(4-1 downto 0) <= local_vc_write_rx(88-1 downto 84);
|
||
|
|
local_vc_write_tx(88-1 downto 84) <= inter_vc_write_out(1)(1)(1)(0)(4-1 downto 0);
|
||
|
|
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
-- Router at x= 1 y=1 z=1
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
router_111: entity work.router_pl
|
||
|
|
generic map (
|
||
|
|
port_num => 7,
|
||
|
|
Xis => 1,
|
||
|
|
Yis => 1,
|
||
|
|
Zis => 1,
|
||
|
|
header_incl_in_packet_length => true,
|
||
|
|
port_exist => (0,1,2,3,4,5,6),
|
||
|
|
vc_num_vec => (4, 4, 4, 4, 4, 4, 4),
|
||
|
|
vc_num_out_vec => (4, 4, 4, 4, 4, 4, 4),
|
||
|
|
vc_depth_array => ((4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4)),
|
||
|
|
vc_depth_out_array => ((4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4)),
|
||
|
|
rout_algo => "DXYU"
|
||
|
|
)
|
||
|
|
port map (
|
||
|
|
clk => clk,
|
||
|
|
rst => rst,
|
||
|
|
data_rx => data_in111,
|
||
|
|
vc_write_rx_vec => vc_write_rx_vec111,
|
||
|
|
incr_rx_vec => incr_rx_vec111,
|
||
|
|
data_tx_pl => data_out111,
|
||
|
|
vc_write_tx_pl_vec => vc_write_tx_pl_vec111,
|
||
|
|
incr_tx_pl_vec => incr_tx_pl_vec111
|
||
|
|
);
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
-- Router port connections to adjacent routers
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
data_in211(0) <= inter_data_in(2)(1)(1)(0);
|
||
|
|
inter_data_out(2)(1)(1)(0) <= data_out211(0);
|
||
|
|
incr_rx_vec211(4-1 downto 0) <= inter_incr_in(2)(1)(1)(0)(4-1 downto 0);
|
||
|
|
inter_incr_out(2)(1)(1)(0)(4-1 downto 0) <= incr_tx_pl_vec211(4-1 downto 0);
|
||
|
|
vc_write_rx_vec211(4-1 downto 0) <= inter_vc_write_in(2)(1)(1)(0)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(2)(1)(1)(0)(4-1 downto 0) <= vc_write_tx_pl_vec211(4-1 downto 0);
|
||
|
|
data_in211(1) <= inter_data_in(2)(1)(1)(1);
|
||
|
|
inter_data_out(2)(1)(1)(1) <= data_out211(1);
|
||
|
|
incr_rx_vec211(8-1 downto 4) <= inter_incr_in(2)(1)(1)(1)(4-1 downto 0);
|
||
|
|
inter_incr_out(2)(1)(1)(1)(4-1 downto 0) <= incr_tx_pl_vec211(8-1 downto 4);
|
||
|
|
vc_write_rx_vec211(8-1 downto 4) <= inter_vc_write_in(2)(1)(1)(1)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(2)(1)(1)(1)(4-1 downto 0) <= vc_write_tx_pl_vec211(8-1 downto 4);
|
||
|
|
|
||
|
|
inter_data_in(2)(1)(1)(1) <= inter_data_out(2)(1+1)(1)(3);
|
||
|
|
|
||
|
|
inter_incr_in(2)(1)(1)(1) <= inter_incr_out(2)(1+1)(1)(3);
|
||
|
|
|
||
|
|
inter_vc_write_in(2)(1)(1)(1) <= inter_vc_write_out(2)(1+1)(1)(3);
|
||
|
|
data_in211(2) <= inter_data_in(2)(1)(1)(2);
|
||
|
|
inter_data_out(2)(1)(1)(2) <= data_out211(2);
|
||
|
|
incr_rx_vec211(12-1 downto 8) <= inter_incr_in(2)(1)(1)(2)(4-1 downto 0);
|
||
|
|
inter_incr_out(2)(1)(1)(2)(4-1 downto 0) <= incr_tx_pl_vec211(12-1 downto 8);
|
||
|
|
vc_write_rx_vec211(12-1 downto 8) <= inter_vc_write_in(2)(1)(1)(2)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(2)(1)(1)(2)(4-1 downto 0) <= vc_write_tx_pl_vec211(12-1 downto 8);
|
||
|
|
|
||
|
|
inter_data_in(2)(1)(1)(2) <= inter_data_out(2+1)(1)(1)(4);
|
||
|
|
|
||
|
|
inter_incr_in(2)(1)(1)(2) <= inter_incr_out(2+1)(1)(1)(4);
|
||
|
|
|
||
|
|
inter_vc_write_in(2)(1)(1)(2) <= inter_vc_write_out(2+1)(1)(1)(4);
|
||
|
|
data_in211(3) <= inter_data_in(2)(1)(1)(3);
|
||
|
|
inter_data_out(2)(1)(1)(3) <= data_out211(3);
|
||
|
|
incr_rx_vec211(16-1 downto 12) <= inter_incr_in(2)(1)(1)(3)(4-1 downto 0);
|
||
|
|
inter_incr_out(2)(1)(1)(3)(4-1 downto 0) <= incr_tx_pl_vec211(16-1 downto 12);
|
||
|
|
vc_write_rx_vec211(16-1 downto 12) <= inter_vc_write_in(2)(1)(1)(3)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(2)(1)(1)(3)(4-1 downto 0) <= vc_write_tx_pl_vec211(16-1 downto 12);
|
||
|
|
|
||
|
|
inter_data_in(2)(1)(1)(3) <= inter_data_out(2)(1-1)(1)(1);
|
||
|
|
|
||
|
|
inter_incr_in(2)(1)(1)(3) <= inter_incr_out(2)(1-1)(1)(1);
|
||
|
|
|
||
|
|
inter_vc_write_in(2)(1)(1)(3) <= inter_vc_write_out(2)(1-1)(1)(1);
|
||
|
|
data_in211(4) <= inter_data_in(2)(1)(1)(4);
|
||
|
|
inter_data_out(2)(1)(1)(4) <= data_out211(4);
|
||
|
|
incr_rx_vec211(20-1 downto 16) <= inter_incr_in(2)(1)(1)(4)(4-1 downto 0);
|
||
|
|
inter_incr_out(2)(1)(1)(4)(4-1 downto 0) <= incr_tx_pl_vec211(20-1 downto 16);
|
||
|
|
vc_write_rx_vec211(20-1 downto 16) <= inter_vc_write_in(2)(1)(1)(4)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(2)(1)(1)(4)(4-1 downto 0) <= vc_write_tx_pl_vec211(20-1 downto 16);
|
||
|
|
|
||
|
|
inter_data_in(2)(1)(1)(4) <= inter_data_out(2-1)(1)(1)(2);
|
||
|
|
|
||
|
|
inter_incr_in(2)(1)(1)(4) <= inter_incr_out(2-1)(1)(1)(2);
|
||
|
|
|
||
|
|
inter_vc_write_in(2)(1)(1)(4) <= inter_vc_write_out(2-1)(1)(1)(2);
|
||
|
|
data_in211(5) <= inter_data_in(2)(1)(1)(5);
|
||
|
|
inter_data_out(2)(1)(1)(5) <= data_out211(5);
|
||
|
|
incr_rx_vec211(24-1 downto 20) <= inter_incr_in(2)(1)(1)(5)(4-1 downto 0);
|
||
|
|
inter_incr_out(2)(1)(1)(5)(4-1 downto 0) <= incr_tx_pl_vec211(24-1 downto 20);
|
||
|
|
vc_write_rx_vec211(24-1 downto 20) <= inter_vc_write_in(2)(1)(1)(5)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(2)(1)(1)(5)(4-1 downto 0) <= vc_write_tx_pl_vec211(24-1 downto 20);
|
||
|
|
|
||
|
|
inter_data_in(2)(1)(1)(5) <= inter_data_out(2)(1)(1+1)(6);
|
||
|
|
|
||
|
|
inter_incr_in(2)(1)(1)(5) <= inter_incr_out(2)(1)(1+1)(6);
|
||
|
|
|
||
|
|
inter_vc_write_in(2)(1)(1)(5) <= inter_vc_write_out(2)(1)(1+1)(6);
|
||
|
|
data_in211(6) <= inter_data_in(2)(1)(1)(6);
|
||
|
|
inter_data_out(2)(1)(1)(6) <= data_out211(6);
|
||
|
|
incr_rx_vec211(28-1 downto 24) <= inter_incr_in(2)(1)(1)(6)(4-1 downto 0);
|
||
|
|
inter_incr_out(2)(1)(1)(6)(4-1 downto 0) <= incr_tx_pl_vec211(28-1 downto 24);
|
||
|
|
vc_write_rx_vec211(28-1 downto 24) <= inter_vc_write_in(2)(1)(1)(6)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(2)(1)(1)(6)(4-1 downto 0) <= vc_write_tx_pl_vec211(28-1 downto 24);
|
||
|
|
|
||
|
|
inter_data_in(2)(1)(1)(6) <= inter_data_out(2)(1)(1-1)(5);
|
||
|
|
|
||
|
|
inter_incr_in(2)(1)(1)(6) <= inter_incr_out(2)(1)(1-1)(5);
|
||
|
|
|
||
|
|
inter_vc_write_in(2)(1)(1)(6) <= inter_vc_write_out(2)(1)(1-1)(5);
|
||
|
|
|
||
|
|
inter_data_in(2)(1)(1)(0) <= local_rx(22);
|
||
|
|
local_tx(22) <= inter_data_out(2)(1)(1)(0);
|
||
|
|
|
||
|
|
inter_incr_in(2)(1)(1)(0)(4-1 downto 0) <= local_incr_rx_vec(92-1 downto 88);
|
||
|
|
local_incr_tx_vec(92-1 downto 88) <= inter_incr_out(2)(1)(1)(0)(4-1 downto 0);
|
||
|
|
|
||
|
|
inter_vc_write_in(2)(1)(1)(0)(4-1 downto 0) <= local_vc_write_rx(92-1 downto 88);
|
||
|
|
local_vc_write_tx(92-1 downto 88) <= inter_vc_write_out(2)(1)(1)(0)(4-1 downto 0);
|
||
|
|
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
-- Router at x= 2 y=1 z=1
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
router_211: entity work.router_pl
|
||
|
|
generic map (
|
||
|
|
port_num => 7,
|
||
|
|
Xis => 2,
|
||
|
|
Yis => 1,
|
||
|
|
Zis => 1,
|
||
|
|
header_incl_in_packet_length => true,
|
||
|
|
port_exist => (0,1,2,3,4,5,6),
|
||
|
|
vc_num_vec => (4, 4, 4, 4, 4, 4, 4),
|
||
|
|
vc_num_out_vec => (4, 4, 4, 4, 4, 4, 4),
|
||
|
|
vc_depth_array => ((4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4)),
|
||
|
|
vc_depth_out_array => ((4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4)),
|
||
|
|
rout_algo => "DXYU"
|
||
|
|
)
|
||
|
|
port map (
|
||
|
|
clk => clk,
|
||
|
|
rst => rst,
|
||
|
|
data_rx => data_in211,
|
||
|
|
vc_write_rx_vec => vc_write_rx_vec211,
|
||
|
|
incr_rx_vec => incr_rx_vec211,
|
||
|
|
data_tx_pl => data_out211,
|
||
|
|
vc_write_tx_pl_vec => vc_write_tx_pl_vec211,
|
||
|
|
incr_tx_pl_vec => incr_tx_pl_vec211
|
||
|
|
);
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
-- Router port connections to adjacent routers
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
data_in311(0) <= inter_data_in(3)(1)(1)(0);
|
||
|
|
inter_data_out(3)(1)(1)(0) <= data_out311(0);
|
||
|
|
incr_rx_vec311(4-1 downto 0) <= inter_incr_in(3)(1)(1)(0)(4-1 downto 0);
|
||
|
|
inter_incr_out(3)(1)(1)(0)(4-1 downto 0) <= incr_tx_pl_vec311(4-1 downto 0);
|
||
|
|
vc_write_rx_vec311(4-1 downto 0) <= inter_vc_write_in(3)(1)(1)(0)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(3)(1)(1)(0)(4-1 downto 0) <= vc_write_tx_pl_vec311(4-1 downto 0);
|
||
|
|
data_in311(1) <= inter_data_in(3)(1)(1)(1);
|
||
|
|
inter_data_out(3)(1)(1)(1) <= data_out311(1);
|
||
|
|
incr_rx_vec311(8-1 downto 4) <= inter_incr_in(3)(1)(1)(1)(4-1 downto 0);
|
||
|
|
inter_incr_out(3)(1)(1)(1)(4-1 downto 0) <= incr_tx_pl_vec311(8-1 downto 4);
|
||
|
|
vc_write_rx_vec311(8-1 downto 4) <= inter_vc_write_in(3)(1)(1)(1)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(3)(1)(1)(1)(4-1 downto 0) <= vc_write_tx_pl_vec311(8-1 downto 4);
|
||
|
|
|
||
|
|
inter_data_in(3)(1)(1)(1) <= inter_data_out(3)(1+1)(1)(3);
|
||
|
|
|
||
|
|
inter_incr_in(3)(1)(1)(1) <= inter_incr_out(3)(1+1)(1)(3);
|
||
|
|
|
||
|
|
inter_vc_write_in(3)(1)(1)(1) <= inter_vc_write_out(3)(1+1)(1)(3);
|
||
|
|
data_in311(2) <= inter_data_in(3)(1)(1)(3);
|
||
|
|
inter_data_out(3)(1)(1)(3) <= data_out311(2);
|
||
|
|
incr_rx_vec311(12-1 downto 8) <= inter_incr_in(3)(1)(1)(3)(4-1 downto 0);
|
||
|
|
inter_incr_out(3)(1)(1)(3)(4-1 downto 0) <= incr_tx_pl_vec311(12-1 downto 8);
|
||
|
|
vc_write_rx_vec311(12-1 downto 8) <= inter_vc_write_in(3)(1)(1)(3)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(3)(1)(1)(3)(4-1 downto 0) <= vc_write_tx_pl_vec311(12-1 downto 8);
|
||
|
|
|
||
|
|
inter_data_in(3)(1)(1)(3) <= inter_data_out(3)(1-1)(1)(1);
|
||
|
|
|
||
|
|
inter_incr_in(3)(1)(1)(3) <= inter_incr_out(3)(1-1)(1)(1);
|
||
|
|
|
||
|
|
inter_vc_write_in(3)(1)(1)(3) <= inter_vc_write_out(3)(1-1)(1)(1);
|
||
|
|
data_in311(3) <= inter_data_in(3)(1)(1)(4);
|
||
|
|
inter_data_out(3)(1)(1)(4) <= data_out311(3);
|
||
|
|
incr_rx_vec311(16-1 downto 12) <= inter_incr_in(3)(1)(1)(4)(4-1 downto 0);
|
||
|
|
inter_incr_out(3)(1)(1)(4)(4-1 downto 0) <= incr_tx_pl_vec311(16-1 downto 12);
|
||
|
|
vc_write_rx_vec311(16-1 downto 12) <= inter_vc_write_in(3)(1)(1)(4)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(3)(1)(1)(4)(4-1 downto 0) <= vc_write_tx_pl_vec311(16-1 downto 12);
|
||
|
|
|
||
|
|
inter_data_in(3)(1)(1)(4) <= inter_data_out(3-1)(1)(1)(2);
|
||
|
|
|
||
|
|
inter_incr_in(3)(1)(1)(4) <= inter_incr_out(3-1)(1)(1)(2);
|
||
|
|
|
||
|
|
inter_vc_write_in(3)(1)(1)(4) <= inter_vc_write_out(3-1)(1)(1)(2);
|
||
|
|
data_in311(4) <= inter_data_in(3)(1)(1)(5);
|
||
|
|
inter_data_out(3)(1)(1)(5) <= data_out311(4);
|
||
|
|
incr_rx_vec311(20-1 downto 16) <= inter_incr_in(3)(1)(1)(5)(4-1 downto 0);
|
||
|
|
inter_incr_out(3)(1)(1)(5)(4-1 downto 0) <= incr_tx_pl_vec311(20-1 downto 16);
|
||
|
|
vc_write_rx_vec311(20-1 downto 16) <= inter_vc_write_in(3)(1)(1)(5)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(3)(1)(1)(5)(4-1 downto 0) <= vc_write_tx_pl_vec311(20-1 downto 16);
|
||
|
|
|
||
|
|
inter_data_in(3)(1)(1)(5) <= inter_data_out(3)(1)(1+1)(6);
|
||
|
|
|
||
|
|
inter_incr_in(3)(1)(1)(5) <= inter_incr_out(3)(1)(1+1)(6);
|
||
|
|
|
||
|
|
inter_vc_write_in(3)(1)(1)(5) <= inter_vc_write_out(3)(1)(1+1)(6);
|
||
|
|
data_in311(5) <= inter_data_in(3)(1)(1)(6);
|
||
|
|
inter_data_out(3)(1)(1)(6) <= data_out311(5);
|
||
|
|
incr_rx_vec311(24-1 downto 20) <= inter_incr_in(3)(1)(1)(6)(4-1 downto 0);
|
||
|
|
inter_incr_out(3)(1)(1)(6)(4-1 downto 0) <= incr_tx_pl_vec311(24-1 downto 20);
|
||
|
|
vc_write_rx_vec311(24-1 downto 20) <= inter_vc_write_in(3)(1)(1)(6)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(3)(1)(1)(6)(4-1 downto 0) <= vc_write_tx_pl_vec311(24-1 downto 20);
|
||
|
|
|
||
|
|
inter_data_in(3)(1)(1)(6) <= inter_data_out(3)(1)(1-1)(5);
|
||
|
|
|
||
|
|
inter_incr_in(3)(1)(1)(6) <= inter_incr_out(3)(1)(1-1)(5);
|
||
|
|
|
||
|
|
inter_vc_write_in(3)(1)(1)(6) <= inter_vc_write_out(3)(1)(1-1)(5);
|
||
|
|
|
||
|
|
inter_data_in(3)(1)(1)(0) <= local_rx(23);
|
||
|
|
local_tx(23) <= inter_data_out(3)(1)(1)(0);
|
||
|
|
|
||
|
|
inter_incr_in(3)(1)(1)(0)(4-1 downto 0) <= local_incr_rx_vec(96-1 downto 92);
|
||
|
|
local_incr_tx_vec(96-1 downto 92) <= inter_incr_out(3)(1)(1)(0)(4-1 downto 0);
|
||
|
|
|
||
|
|
inter_vc_write_in(3)(1)(1)(0)(4-1 downto 0) <= local_vc_write_rx(96-1 downto 92);
|
||
|
|
local_vc_write_tx(96-1 downto 92) <= inter_vc_write_out(3)(1)(1)(0)(4-1 downto 0);
|
||
|
|
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
-- Router at x= 3 y=1 z=1
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
router_311: entity work.router_pl
|
||
|
|
generic map (
|
||
|
|
port_num => 6,
|
||
|
|
Xis => 3,
|
||
|
|
Yis => 1,
|
||
|
|
Zis => 1,
|
||
|
|
header_incl_in_packet_length => true,
|
||
|
|
port_exist => (0,1,3,4,5,6),
|
||
|
|
vc_num_vec => (4, 4, 4, 4, 4, 4),
|
||
|
|
vc_num_out_vec => (4, 4, 4, 4, 4, 4),
|
||
|
|
vc_depth_array => ((4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4)),
|
||
|
|
vc_depth_out_array => ((4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4)),
|
||
|
|
rout_algo => "DXYU"
|
||
|
|
)
|
||
|
|
port map (
|
||
|
|
clk => clk,
|
||
|
|
rst => rst,
|
||
|
|
data_rx => data_in311,
|
||
|
|
vc_write_rx_vec => vc_write_rx_vec311,
|
||
|
|
incr_rx_vec => incr_rx_vec311,
|
||
|
|
data_tx_pl => data_out311,
|
||
|
|
vc_write_tx_pl_vec => vc_write_tx_pl_vec311,
|
||
|
|
incr_tx_pl_vec => incr_tx_pl_vec311
|
||
|
|
);
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
-- Router port connections to adjacent routers
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
data_in021(0) <= inter_data_in(0)(2)(1)(0);
|
||
|
|
inter_data_out(0)(2)(1)(0) <= data_out021(0);
|
||
|
|
incr_rx_vec021(4-1 downto 0) <= inter_incr_in(0)(2)(1)(0)(4-1 downto 0);
|
||
|
|
inter_incr_out(0)(2)(1)(0)(4-1 downto 0) <= incr_tx_pl_vec021(4-1 downto 0);
|
||
|
|
vc_write_rx_vec021(4-1 downto 0) <= inter_vc_write_in(0)(2)(1)(0)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(0)(2)(1)(0)(4-1 downto 0) <= vc_write_tx_pl_vec021(4-1 downto 0);
|
||
|
|
data_in021(1) <= inter_data_in(0)(2)(1)(1);
|
||
|
|
inter_data_out(0)(2)(1)(1) <= data_out021(1);
|
||
|
|
incr_rx_vec021(8-1 downto 4) <= inter_incr_in(0)(2)(1)(1)(4-1 downto 0);
|
||
|
|
inter_incr_out(0)(2)(1)(1)(4-1 downto 0) <= incr_tx_pl_vec021(8-1 downto 4);
|
||
|
|
vc_write_rx_vec021(8-1 downto 4) <= inter_vc_write_in(0)(2)(1)(1)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(0)(2)(1)(1)(4-1 downto 0) <= vc_write_tx_pl_vec021(8-1 downto 4);
|
||
|
|
|
||
|
|
inter_data_in(0)(2)(1)(1) <= inter_data_out(0)(2+1)(1)(3);
|
||
|
|
|
||
|
|
inter_incr_in(0)(2)(1)(1) <= inter_incr_out(0)(2+1)(1)(3);
|
||
|
|
|
||
|
|
inter_vc_write_in(0)(2)(1)(1) <= inter_vc_write_out(0)(2+1)(1)(3);
|
||
|
|
data_in021(2) <= inter_data_in(0)(2)(1)(2);
|
||
|
|
inter_data_out(0)(2)(1)(2) <= data_out021(2);
|
||
|
|
incr_rx_vec021(12-1 downto 8) <= inter_incr_in(0)(2)(1)(2)(4-1 downto 0);
|
||
|
|
inter_incr_out(0)(2)(1)(2)(4-1 downto 0) <= incr_tx_pl_vec021(12-1 downto 8);
|
||
|
|
vc_write_rx_vec021(12-1 downto 8) <= inter_vc_write_in(0)(2)(1)(2)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(0)(2)(1)(2)(4-1 downto 0) <= vc_write_tx_pl_vec021(12-1 downto 8);
|
||
|
|
|
||
|
|
inter_data_in(0)(2)(1)(2) <= inter_data_out(0+1)(2)(1)(4);
|
||
|
|
|
||
|
|
inter_incr_in(0)(2)(1)(2) <= inter_incr_out(0+1)(2)(1)(4);
|
||
|
|
|
||
|
|
inter_vc_write_in(0)(2)(1)(2) <= inter_vc_write_out(0+1)(2)(1)(4);
|
||
|
|
data_in021(3) <= inter_data_in(0)(2)(1)(3);
|
||
|
|
inter_data_out(0)(2)(1)(3) <= data_out021(3);
|
||
|
|
incr_rx_vec021(16-1 downto 12) <= inter_incr_in(0)(2)(1)(3)(4-1 downto 0);
|
||
|
|
inter_incr_out(0)(2)(1)(3)(4-1 downto 0) <= incr_tx_pl_vec021(16-1 downto 12);
|
||
|
|
vc_write_rx_vec021(16-1 downto 12) <= inter_vc_write_in(0)(2)(1)(3)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(0)(2)(1)(3)(4-1 downto 0) <= vc_write_tx_pl_vec021(16-1 downto 12);
|
||
|
|
|
||
|
|
inter_data_in(0)(2)(1)(3) <= inter_data_out(0)(2-1)(1)(1);
|
||
|
|
|
||
|
|
inter_incr_in(0)(2)(1)(3) <= inter_incr_out(0)(2-1)(1)(1);
|
||
|
|
|
||
|
|
inter_vc_write_in(0)(2)(1)(3) <= inter_vc_write_out(0)(2-1)(1)(1);
|
||
|
|
data_in021(4) <= inter_data_in(0)(2)(1)(5);
|
||
|
|
inter_data_out(0)(2)(1)(5) <= data_out021(4);
|
||
|
|
incr_rx_vec021(20-1 downto 16) <= inter_incr_in(0)(2)(1)(5)(4-1 downto 0);
|
||
|
|
inter_incr_out(0)(2)(1)(5)(4-1 downto 0) <= incr_tx_pl_vec021(20-1 downto 16);
|
||
|
|
vc_write_rx_vec021(20-1 downto 16) <= inter_vc_write_in(0)(2)(1)(5)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(0)(2)(1)(5)(4-1 downto 0) <= vc_write_tx_pl_vec021(20-1 downto 16);
|
||
|
|
|
||
|
|
inter_data_in(0)(2)(1)(5) <= inter_data_out(0)(2)(1+1)(6);
|
||
|
|
|
||
|
|
inter_incr_in(0)(2)(1)(5) <= inter_incr_out(0)(2)(1+1)(6);
|
||
|
|
|
||
|
|
inter_vc_write_in(0)(2)(1)(5) <= inter_vc_write_out(0)(2)(1+1)(6);
|
||
|
|
data_in021(5) <= inter_data_in(0)(2)(1)(6);
|
||
|
|
inter_data_out(0)(2)(1)(6) <= data_out021(5);
|
||
|
|
incr_rx_vec021(24-1 downto 20) <= inter_incr_in(0)(2)(1)(6)(4-1 downto 0);
|
||
|
|
inter_incr_out(0)(2)(1)(6)(4-1 downto 0) <= incr_tx_pl_vec021(24-1 downto 20);
|
||
|
|
vc_write_rx_vec021(24-1 downto 20) <= inter_vc_write_in(0)(2)(1)(6)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(0)(2)(1)(6)(4-1 downto 0) <= vc_write_tx_pl_vec021(24-1 downto 20);
|
||
|
|
|
||
|
|
inter_data_in(0)(2)(1)(6) <= inter_data_out(0)(2)(1-1)(5);
|
||
|
|
|
||
|
|
inter_incr_in(0)(2)(1)(6) <= inter_incr_out(0)(2)(1-1)(5);
|
||
|
|
|
||
|
|
inter_vc_write_in(0)(2)(1)(6) <= inter_vc_write_out(0)(2)(1-1)(5);
|
||
|
|
|
||
|
|
inter_data_in(0)(2)(1)(0) <= local_rx(24);
|
||
|
|
local_tx(24) <= inter_data_out(0)(2)(1)(0);
|
||
|
|
|
||
|
|
inter_incr_in(0)(2)(1)(0)(4-1 downto 0) <= local_incr_rx_vec(100-1 downto 96);
|
||
|
|
local_incr_tx_vec(100-1 downto 96) <= inter_incr_out(0)(2)(1)(0)(4-1 downto 0);
|
||
|
|
|
||
|
|
inter_vc_write_in(0)(2)(1)(0)(4-1 downto 0) <= local_vc_write_rx(100-1 downto 96);
|
||
|
|
local_vc_write_tx(100-1 downto 96) <= inter_vc_write_out(0)(2)(1)(0)(4-1 downto 0);
|
||
|
|
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
-- Router at x= 0 y=2 z=1
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
router_021: entity work.router_pl
|
||
|
|
generic map (
|
||
|
|
port_num => 6,
|
||
|
|
Xis => 0,
|
||
|
|
Yis => 2,
|
||
|
|
Zis => 1,
|
||
|
|
header_incl_in_packet_length => true,
|
||
|
|
port_exist => (0,1,2,3,5,6),
|
||
|
|
vc_num_vec => (4, 4, 4, 4, 4, 4),
|
||
|
|
vc_num_out_vec => (4, 4, 4, 4, 4, 4),
|
||
|
|
vc_depth_array => ((4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4)),
|
||
|
|
vc_depth_out_array => ((4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4)),
|
||
|
|
rout_algo => "DXYU"
|
||
|
|
)
|
||
|
|
port map (
|
||
|
|
clk => clk,
|
||
|
|
rst => rst,
|
||
|
|
data_rx => data_in021,
|
||
|
|
vc_write_rx_vec => vc_write_rx_vec021,
|
||
|
|
incr_rx_vec => incr_rx_vec021,
|
||
|
|
data_tx_pl => data_out021,
|
||
|
|
vc_write_tx_pl_vec => vc_write_tx_pl_vec021,
|
||
|
|
incr_tx_pl_vec => incr_tx_pl_vec021
|
||
|
|
);
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
-- Router port connections to adjacent routers
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
data_in121(0) <= inter_data_in(1)(2)(1)(0);
|
||
|
|
inter_data_out(1)(2)(1)(0) <= data_out121(0);
|
||
|
|
incr_rx_vec121(4-1 downto 0) <= inter_incr_in(1)(2)(1)(0)(4-1 downto 0);
|
||
|
|
inter_incr_out(1)(2)(1)(0)(4-1 downto 0) <= incr_tx_pl_vec121(4-1 downto 0);
|
||
|
|
vc_write_rx_vec121(4-1 downto 0) <= inter_vc_write_in(1)(2)(1)(0)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(1)(2)(1)(0)(4-1 downto 0) <= vc_write_tx_pl_vec121(4-1 downto 0);
|
||
|
|
data_in121(1) <= inter_data_in(1)(2)(1)(1);
|
||
|
|
inter_data_out(1)(2)(1)(1) <= data_out121(1);
|
||
|
|
incr_rx_vec121(8-1 downto 4) <= inter_incr_in(1)(2)(1)(1)(4-1 downto 0);
|
||
|
|
inter_incr_out(1)(2)(1)(1)(4-1 downto 0) <= incr_tx_pl_vec121(8-1 downto 4);
|
||
|
|
vc_write_rx_vec121(8-1 downto 4) <= inter_vc_write_in(1)(2)(1)(1)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(1)(2)(1)(1)(4-1 downto 0) <= vc_write_tx_pl_vec121(8-1 downto 4);
|
||
|
|
|
||
|
|
inter_data_in(1)(2)(1)(1) <= inter_data_out(1)(2+1)(1)(3);
|
||
|
|
|
||
|
|
inter_incr_in(1)(2)(1)(1) <= inter_incr_out(1)(2+1)(1)(3);
|
||
|
|
|
||
|
|
inter_vc_write_in(1)(2)(1)(1) <= inter_vc_write_out(1)(2+1)(1)(3);
|
||
|
|
data_in121(2) <= inter_data_in(1)(2)(1)(2);
|
||
|
|
inter_data_out(1)(2)(1)(2) <= data_out121(2);
|
||
|
|
incr_rx_vec121(12-1 downto 8) <= inter_incr_in(1)(2)(1)(2)(4-1 downto 0);
|
||
|
|
inter_incr_out(1)(2)(1)(2)(4-1 downto 0) <= incr_tx_pl_vec121(12-1 downto 8);
|
||
|
|
vc_write_rx_vec121(12-1 downto 8) <= inter_vc_write_in(1)(2)(1)(2)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(1)(2)(1)(2)(4-1 downto 0) <= vc_write_tx_pl_vec121(12-1 downto 8);
|
||
|
|
|
||
|
|
inter_data_in(1)(2)(1)(2) <= inter_data_out(1+1)(2)(1)(4);
|
||
|
|
|
||
|
|
inter_incr_in(1)(2)(1)(2) <= inter_incr_out(1+1)(2)(1)(4);
|
||
|
|
|
||
|
|
inter_vc_write_in(1)(2)(1)(2) <= inter_vc_write_out(1+1)(2)(1)(4);
|
||
|
|
data_in121(3) <= inter_data_in(1)(2)(1)(3);
|
||
|
|
inter_data_out(1)(2)(1)(3) <= data_out121(3);
|
||
|
|
incr_rx_vec121(16-1 downto 12) <= inter_incr_in(1)(2)(1)(3)(4-1 downto 0);
|
||
|
|
inter_incr_out(1)(2)(1)(3)(4-1 downto 0) <= incr_tx_pl_vec121(16-1 downto 12);
|
||
|
|
vc_write_rx_vec121(16-1 downto 12) <= inter_vc_write_in(1)(2)(1)(3)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(1)(2)(1)(3)(4-1 downto 0) <= vc_write_tx_pl_vec121(16-1 downto 12);
|
||
|
|
|
||
|
|
inter_data_in(1)(2)(1)(3) <= inter_data_out(1)(2-1)(1)(1);
|
||
|
|
|
||
|
|
inter_incr_in(1)(2)(1)(3) <= inter_incr_out(1)(2-1)(1)(1);
|
||
|
|
|
||
|
|
inter_vc_write_in(1)(2)(1)(3) <= inter_vc_write_out(1)(2-1)(1)(1);
|
||
|
|
data_in121(4) <= inter_data_in(1)(2)(1)(4);
|
||
|
|
inter_data_out(1)(2)(1)(4) <= data_out121(4);
|
||
|
|
incr_rx_vec121(20-1 downto 16) <= inter_incr_in(1)(2)(1)(4)(4-1 downto 0);
|
||
|
|
inter_incr_out(1)(2)(1)(4)(4-1 downto 0) <= incr_tx_pl_vec121(20-1 downto 16);
|
||
|
|
vc_write_rx_vec121(20-1 downto 16) <= inter_vc_write_in(1)(2)(1)(4)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(1)(2)(1)(4)(4-1 downto 0) <= vc_write_tx_pl_vec121(20-1 downto 16);
|
||
|
|
|
||
|
|
inter_data_in(1)(2)(1)(4) <= inter_data_out(1-1)(2)(1)(2);
|
||
|
|
|
||
|
|
inter_incr_in(1)(2)(1)(4) <= inter_incr_out(1-1)(2)(1)(2);
|
||
|
|
|
||
|
|
inter_vc_write_in(1)(2)(1)(4) <= inter_vc_write_out(1-1)(2)(1)(2);
|
||
|
|
data_in121(5) <= inter_data_in(1)(2)(1)(5);
|
||
|
|
inter_data_out(1)(2)(1)(5) <= data_out121(5);
|
||
|
|
incr_rx_vec121(24-1 downto 20) <= inter_incr_in(1)(2)(1)(5)(4-1 downto 0);
|
||
|
|
inter_incr_out(1)(2)(1)(5)(4-1 downto 0) <= incr_tx_pl_vec121(24-1 downto 20);
|
||
|
|
vc_write_rx_vec121(24-1 downto 20) <= inter_vc_write_in(1)(2)(1)(5)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(1)(2)(1)(5)(4-1 downto 0) <= vc_write_tx_pl_vec121(24-1 downto 20);
|
||
|
|
|
||
|
|
inter_data_in(1)(2)(1)(5) <= inter_data_out(1)(2)(1+1)(6);
|
||
|
|
|
||
|
|
inter_incr_in(1)(2)(1)(5) <= inter_incr_out(1)(2)(1+1)(6);
|
||
|
|
|
||
|
|
inter_vc_write_in(1)(2)(1)(5) <= inter_vc_write_out(1)(2)(1+1)(6);
|
||
|
|
data_in121(6) <= inter_data_in(1)(2)(1)(6);
|
||
|
|
inter_data_out(1)(2)(1)(6) <= data_out121(6);
|
||
|
|
incr_rx_vec121(28-1 downto 24) <= inter_incr_in(1)(2)(1)(6)(4-1 downto 0);
|
||
|
|
inter_incr_out(1)(2)(1)(6)(4-1 downto 0) <= incr_tx_pl_vec121(28-1 downto 24);
|
||
|
|
vc_write_rx_vec121(28-1 downto 24) <= inter_vc_write_in(1)(2)(1)(6)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(1)(2)(1)(6)(4-1 downto 0) <= vc_write_tx_pl_vec121(28-1 downto 24);
|
||
|
|
|
||
|
|
inter_data_in(1)(2)(1)(6) <= inter_data_out(1)(2)(1-1)(5);
|
||
|
|
|
||
|
|
inter_incr_in(1)(2)(1)(6) <= inter_incr_out(1)(2)(1-1)(5);
|
||
|
|
|
||
|
|
inter_vc_write_in(1)(2)(1)(6) <= inter_vc_write_out(1)(2)(1-1)(5);
|
||
|
|
|
||
|
|
inter_data_in(1)(2)(1)(0) <= local_rx(25);
|
||
|
|
local_tx(25) <= inter_data_out(1)(2)(1)(0);
|
||
|
|
|
||
|
|
inter_incr_in(1)(2)(1)(0)(4-1 downto 0) <= local_incr_rx_vec(104-1 downto 100);
|
||
|
|
local_incr_tx_vec(104-1 downto 100) <= inter_incr_out(1)(2)(1)(0)(4-1 downto 0);
|
||
|
|
|
||
|
|
inter_vc_write_in(1)(2)(1)(0)(4-1 downto 0) <= local_vc_write_rx(104-1 downto 100);
|
||
|
|
local_vc_write_tx(104-1 downto 100) <= inter_vc_write_out(1)(2)(1)(0)(4-1 downto 0);
|
||
|
|
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
-- Router at x= 1 y=2 z=1
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
router_121: entity work.router_pl
|
||
|
|
generic map (
|
||
|
|
port_num => 7,
|
||
|
|
Xis => 1,
|
||
|
|
Yis => 2,
|
||
|
|
Zis => 1,
|
||
|
|
header_incl_in_packet_length => true,
|
||
|
|
port_exist => (0,1,2,3,4,5,6),
|
||
|
|
vc_num_vec => (4, 4, 4, 4, 4, 4, 4),
|
||
|
|
vc_num_out_vec => (4, 4, 4, 4, 4, 4, 4),
|
||
|
|
vc_depth_array => ((4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4)),
|
||
|
|
vc_depth_out_array => ((4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4)),
|
||
|
|
rout_algo => "DXYU"
|
||
|
|
)
|
||
|
|
port map (
|
||
|
|
clk => clk,
|
||
|
|
rst => rst,
|
||
|
|
data_rx => data_in121,
|
||
|
|
vc_write_rx_vec => vc_write_rx_vec121,
|
||
|
|
incr_rx_vec => incr_rx_vec121,
|
||
|
|
data_tx_pl => data_out121,
|
||
|
|
vc_write_tx_pl_vec => vc_write_tx_pl_vec121,
|
||
|
|
incr_tx_pl_vec => incr_tx_pl_vec121
|
||
|
|
);
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
-- Router port connections to adjacent routers
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
data_in221(0) <= inter_data_in(2)(2)(1)(0);
|
||
|
|
inter_data_out(2)(2)(1)(0) <= data_out221(0);
|
||
|
|
incr_rx_vec221(4-1 downto 0) <= inter_incr_in(2)(2)(1)(0)(4-1 downto 0);
|
||
|
|
inter_incr_out(2)(2)(1)(0)(4-1 downto 0) <= incr_tx_pl_vec221(4-1 downto 0);
|
||
|
|
vc_write_rx_vec221(4-1 downto 0) <= inter_vc_write_in(2)(2)(1)(0)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(2)(2)(1)(0)(4-1 downto 0) <= vc_write_tx_pl_vec221(4-1 downto 0);
|
||
|
|
data_in221(1) <= inter_data_in(2)(2)(1)(1);
|
||
|
|
inter_data_out(2)(2)(1)(1) <= data_out221(1);
|
||
|
|
incr_rx_vec221(8-1 downto 4) <= inter_incr_in(2)(2)(1)(1)(4-1 downto 0);
|
||
|
|
inter_incr_out(2)(2)(1)(1)(4-1 downto 0) <= incr_tx_pl_vec221(8-1 downto 4);
|
||
|
|
vc_write_rx_vec221(8-1 downto 4) <= inter_vc_write_in(2)(2)(1)(1)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(2)(2)(1)(1)(4-1 downto 0) <= vc_write_tx_pl_vec221(8-1 downto 4);
|
||
|
|
|
||
|
|
inter_data_in(2)(2)(1)(1) <= inter_data_out(2)(2+1)(1)(3);
|
||
|
|
|
||
|
|
inter_incr_in(2)(2)(1)(1) <= inter_incr_out(2)(2+1)(1)(3);
|
||
|
|
|
||
|
|
inter_vc_write_in(2)(2)(1)(1) <= inter_vc_write_out(2)(2+1)(1)(3);
|
||
|
|
data_in221(2) <= inter_data_in(2)(2)(1)(2);
|
||
|
|
inter_data_out(2)(2)(1)(2) <= data_out221(2);
|
||
|
|
incr_rx_vec221(12-1 downto 8) <= inter_incr_in(2)(2)(1)(2)(4-1 downto 0);
|
||
|
|
inter_incr_out(2)(2)(1)(2)(4-1 downto 0) <= incr_tx_pl_vec221(12-1 downto 8);
|
||
|
|
vc_write_rx_vec221(12-1 downto 8) <= inter_vc_write_in(2)(2)(1)(2)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(2)(2)(1)(2)(4-1 downto 0) <= vc_write_tx_pl_vec221(12-1 downto 8);
|
||
|
|
|
||
|
|
inter_data_in(2)(2)(1)(2) <= inter_data_out(2+1)(2)(1)(4);
|
||
|
|
|
||
|
|
inter_incr_in(2)(2)(1)(2) <= inter_incr_out(2+1)(2)(1)(4);
|
||
|
|
|
||
|
|
inter_vc_write_in(2)(2)(1)(2) <= inter_vc_write_out(2+1)(2)(1)(4);
|
||
|
|
data_in221(3) <= inter_data_in(2)(2)(1)(3);
|
||
|
|
inter_data_out(2)(2)(1)(3) <= data_out221(3);
|
||
|
|
incr_rx_vec221(16-1 downto 12) <= inter_incr_in(2)(2)(1)(3)(4-1 downto 0);
|
||
|
|
inter_incr_out(2)(2)(1)(3)(4-1 downto 0) <= incr_tx_pl_vec221(16-1 downto 12);
|
||
|
|
vc_write_rx_vec221(16-1 downto 12) <= inter_vc_write_in(2)(2)(1)(3)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(2)(2)(1)(3)(4-1 downto 0) <= vc_write_tx_pl_vec221(16-1 downto 12);
|
||
|
|
|
||
|
|
inter_data_in(2)(2)(1)(3) <= inter_data_out(2)(2-1)(1)(1);
|
||
|
|
|
||
|
|
inter_incr_in(2)(2)(1)(3) <= inter_incr_out(2)(2-1)(1)(1);
|
||
|
|
|
||
|
|
inter_vc_write_in(2)(2)(1)(3) <= inter_vc_write_out(2)(2-1)(1)(1);
|
||
|
|
data_in221(4) <= inter_data_in(2)(2)(1)(4);
|
||
|
|
inter_data_out(2)(2)(1)(4) <= data_out221(4);
|
||
|
|
incr_rx_vec221(20-1 downto 16) <= inter_incr_in(2)(2)(1)(4)(4-1 downto 0);
|
||
|
|
inter_incr_out(2)(2)(1)(4)(4-1 downto 0) <= incr_tx_pl_vec221(20-1 downto 16);
|
||
|
|
vc_write_rx_vec221(20-1 downto 16) <= inter_vc_write_in(2)(2)(1)(4)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(2)(2)(1)(4)(4-1 downto 0) <= vc_write_tx_pl_vec221(20-1 downto 16);
|
||
|
|
|
||
|
|
inter_data_in(2)(2)(1)(4) <= inter_data_out(2-1)(2)(1)(2);
|
||
|
|
|
||
|
|
inter_incr_in(2)(2)(1)(4) <= inter_incr_out(2-1)(2)(1)(2);
|
||
|
|
|
||
|
|
inter_vc_write_in(2)(2)(1)(4) <= inter_vc_write_out(2-1)(2)(1)(2);
|
||
|
|
data_in221(5) <= inter_data_in(2)(2)(1)(5);
|
||
|
|
inter_data_out(2)(2)(1)(5) <= data_out221(5);
|
||
|
|
incr_rx_vec221(24-1 downto 20) <= inter_incr_in(2)(2)(1)(5)(4-1 downto 0);
|
||
|
|
inter_incr_out(2)(2)(1)(5)(4-1 downto 0) <= incr_tx_pl_vec221(24-1 downto 20);
|
||
|
|
vc_write_rx_vec221(24-1 downto 20) <= inter_vc_write_in(2)(2)(1)(5)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(2)(2)(1)(5)(4-1 downto 0) <= vc_write_tx_pl_vec221(24-1 downto 20);
|
||
|
|
|
||
|
|
inter_data_in(2)(2)(1)(5) <= inter_data_out(2)(2)(1+1)(6);
|
||
|
|
|
||
|
|
inter_incr_in(2)(2)(1)(5) <= inter_incr_out(2)(2)(1+1)(6);
|
||
|
|
|
||
|
|
inter_vc_write_in(2)(2)(1)(5) <= inter_vc_write_out(2)(2)(1+1)(6);
|
||
|
|
data_in221(6) <= inter_data_in(2)(2)(1)(6);
|
||
|
|
inter_data_out(2)(2)(1)(6) <= data_out221(6);
|
||
|
|
incr_rx_vec221(28-1 downto 24) <= inter_incr_in(2)(2)(1)(6)(4-1 downto 0);
|
||
|
|
inter_incr_out(2)(2)(1)(6)(4-1 downto 0) <= incr_tx_pl_vec221(28-1 downto 24);
|
||
|
|
vc_write_rx_vec221(28-1 downto 24) <= inter_vc_write_in(2)(2)(1)(6)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(2)(2)(1)(6)(4-1 downto 0) <= vc_write_tx_pl_vec221(28-1 downto 24);
|
||
|
|
|
||
|
|
inter_data_in(2)(2)(1)(6) <= inter_data_out(2)(2)(1-1)(5);
|
||
|
|
|
||
|
|
inter_incr_in(2)(2)(1)(6) <= inter_incr_out(2)(2)(1-1)(5);
|
||
|
|
|
||
|
|
inter_vc_write_in(2)(2)(1)(6) <= inter_vc_write_out(2)(2)(1-1)(5);
|
||
|
|
|
||
|
|
inter_data_in(2)(2)(1)(0) <= local_rx(26);
|
||
|
|
local_tx(26) <= inter_data_out(2)(2)(1)(0);
|
||
|
|
|
||
|
|
inter_incr_in(2)(2)(1)(0)(4-1 downto 0) <= local_incr_rx_vec(108-1 downto 104);
|
||
|
|
local_incr_tx_vec(108-1 downto 104) <= inter_incr_out(2)(2)(1)(0)(4-1 downto 0);
|
||
|
|
|
||
|
|
inter_vc_write_in(2)(2)(1)(0)(4-1 downto 0) <= local_vc_write_rx(108-1 downto 104);
|
||
|
|
local_vc_write_tx(108-1 downto 104) <= inter_vc_write_out(2)(2)(1)(0)(4-1 downto 0);
|
||
|
|
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
-- Router at x= 2 y=2 z=1
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
router_221: entity work.router_pl
|
||
|
|
generic map (
|
||
|
|
port_num => 7,
|
||
|
|
Xis => 2,
|
||
|
|
Yis => 2,
|
||
|
|
Zis => 1,
|
||
|
|
header_incl_in_packet_length => true,
|
||
|
|
port_exist => (0,1,2,3,4,5,6),
|
||
|
|
vc_num_vec => (4, 4, 4, 4, 4, 4, 4),
|
||
|
|
vc_num_out_vec => (4, 4, 4, 4, 4, 4, 4),
|
||
|
|
vc_depth_array => ((4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4)),
|
||
|
|
vc_depth_out_array => ((4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4)),
|
||
|
|
rout_algo => "DXYU"
|
||
|
|
)
|
||
|
|
port map (
|
||
|
|
clk => clk,
|
||
|
|
rst => rst,
|
||
|
|
data_rx => data_in221,
|
||
|
|
vc_write_rx_vec => vc_write_rx_vec221,
|
||
|
|
incr_rx_vec => incr_rx_vec221,
|
||
|
|
data_tx_pl => data_out221,
|
||
|
|
vc_write_tx_pl_vec => vc_write_tx_pl_vec221,
|
||
|
|
incr_tx_pl_vec => incr_tx_pl_vec221
|
||
|
|
);
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
-- Router port connections to adjacent routers
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
data_in321(0) <= inter_data_in(3)(2)(1)(0);
|
||
|
|
inter_data_out(3)(2)(1)(0) <= data_out321(0);
|
||
|
|
incr_rx_vec321(4-1 downto 0) <= inter_incr_in(3)(2)(1)(0)(4-1 downto 0);
|
||
|
|
inter_incr_out(3)(2)(1)(0)(4-1 downto 0) <= incr_tx_pl_vec321(4-1 downto 0);
|
||
|
|
vc_write_rx_vec321(4-1 downto 0) <= inter_vc_write_in(3)(2)(1)(0)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(3)(2)(1)(0)(4-1 downto 0) <= vc_write_tx_pl_vec321(4-1 downto 0);
|
||
|
|
data_in321(1) <= inter_data_in(3)(2)(1)(1);
|
||
|
|
inter_data_out(3)(2)(1)(1) <= data_out321(1);
|
||
|
|
incr_rx_vec321(8-1 downto 4) <= inter_incr_in(3)(2)(1)(1)(4-1 downto 0);
|
||
|
|
inter_incr_out(3)(2)(1)(1)(4-1 downto 0) <= incr_tx_pl_vec321(8-1 downto 4);
|
||
|
|
vc_write_rx_vec321(8-1 downto 4) <= inter_vc_write_in(3)(2)(1)(1)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(3)(2)(1)(1)(4-1 downto 0) <= vc_write_tx_pl_vec321(8-1 downto 4);
|
||
|
|
|
||
|
|
inter_data_in(3)(2)(1)(1) <= inter_data_out(3)(2+1)(1)(3);
|
||
|
|
|
||
|
|
inter_incr_in(3)(2)(1)(1) <= inter_incr_out(3)(2+1)(1)(3);
|
||
|
|
|
||
|
|
inter_vc_write_in(3)(2)(1)(1) <= inter_vc_write_out(3)(2+1)(1)(3);
|
||
|
|
data_in321(2) <= inter_data_in(3)(2)(1)(3);
|
||
|
|
inter_data_out(3)(2)(1)(3) <= data_out321(2);
|
||
|
|
incr_rx_vec321(12-1 downto 8) <= inter_incr_in(3)(2)(1)(3)(4-1 downto 0);
|
||
|
|
inter_incr_out(3)(2)(1)(3)(4-1 downto 0) <= incr_tx_pl_vec321(12-1 downto 8);
|
||
|
|
vc_write_rx_vec321(12-1 downto 8) <= inter_vc_write_in(3)(2)(1)(3)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(3)(2)(1)(3)(4-1 downto 0) <= vc_write_tx_pl_vec321(12-1 downto 8);
|
||
|
|
|
||
|
|
inter_data_in(3)(2)(1)(3) <= inter_data_out(3)(2-1)(1)(1);
|
||
|
|
|
||
|
|
inter_incr_in(3)(2)(1)(3) <= inter_incr_out(3)(2-1)(1)(1);
|
||
|
|
|
||
|
|
inter_vc_write_in(3)(2)(1)(3) <= inter_vc_write_out(3)(2-1)(1)(1);
|
||
|
|
data_in321(3) <= inter_data_in(3)(2)(1)(4);
|
||
|
|
inter_data_out(3)(2)(1)(4) <= data_out321(3);
|
||
|
|
incr_rx_vec321(16-1 downto 12) <= inter_incr_in(3)(2)(1)(4)(4-1 downto 0);
|
||
|
|
inter_incr_out(3)(2)(1)(4)(4-1 downto 0) <= incr_tx_pl_vec321(16-1 downto 12);
|
||
|
|
vc_write_rx_vec321(16-1 downto 12) <= inter_vc_write_in(3)(2)(1)(4)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(3)(2)(1)(4)(4-1 downto 0) <= vc_write_tx_pl_vec321(16-1 downto 12);
|
||
|
|
|
||
|
|
inter_data_in(3)(2)(1)(4) <= inter_data_out(3-1)(2)(1)(2);
|
||
|
|
|
||
|
|
inter_incr_in(3)(2)(1)(4) <= inter_incr_out(3-1)(2)(1)(2);
|
||
|
|
|
||
|
|
inter_vc_write_in(3)(2)(1)(4) <= inter_vc_write_out(3-1)(2)(1)(2);
|
||
|
|
data_in321(4) <= inter_data_in(3)(2)(1)(5);
|
||
|
|
inter_data_out(3)(2)(1)(5) <= data_out321(4);
|
||
|
|
incr_rx_vec321(20-1 downto 16) <= inter_incr_in(3)(2)(1)(5)(4-1 downto 0);
|
||
|
|
inter_incr_out(3)(2)(1)(5)(4-1 downto 0) <= incr_tx_pl_vec321(20-1 downto 16);
|
||
|
|
vc_write_rx_vec321(20-1 downto 16) <= inter_vc_write_in(3)(2)(1)(5)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(3)(2)(1)(5)(4-1 downto 0) <= vc_write_tx_pl_vec321(20-1 downto 16);
|
||
|
|
|
||
|
|
inter_data_in(3)(2)(1)(5) <= inter_data_out(3)(2)(1+1)(6);
|
||
|
|
|
||
|
|
inter_incr_in(3)(2)(1)(5) <= inter_incr_out(3)(2)(1+1)(6);
|
||
|
|
|
||
|
|
inter_vc_write_in(3)(2)(1)(5) <= inter_vc_write_out(3)(2)(1+1)(6);
|
||
|
|
data_in321(5) <= inter_data_in(3)(2)(1)(6);
|
||
|
|
inter_data_out(3)(2)(1)(6) <= data_out321(5);
|
||
|
|
incr_rx_vec321(24-1 downto 20) <= inter_incr_in(3)(2)(1)(6)(4-1 downto 0);
|
||
|
|
inter_incr_out(3)(2)(1)(6)(4-1 downto 0) <= incr_tx_pl_vec321(24-1 downto 20);
|
||
|
|
vc_write_rx_vec321(24-1 downto 20) <= inter_vc_write_in(3)(2)(1)(6)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(3)(2)(1)(6)(4-1 downto 0) <= vc_write_tx_pl_vec321(24-1 downto 20);
|
||
|
|
|
||
|
|
inter_data_in(3)(2)(1)(6) <= inter_data_out(3)(2)(1-1)(5);
|
||
|
|
|
||
|
|
inter_incr_in(3)(2)(1)(6) <= inter_incr_out(3)(2)(1-1)(5);
|
||
|
|
|
||
|
|
inter_vc_write_in(3)(2)(1)(6) <= inter_vc_write_out(3)(2)(1-1)(5);
|
||
|
|
|
||
|
|
inter_data_in(3)(2)(1)(0) <= local_rx(27);
|
||
|
|
local_tx(27) <= inter_data_out(3)(2)(1)(0);
|
||
|
|
|
||
|
|
inter_incr_in(3)(2)(1)(0)(4-1 downto 0) <= local_incr_rx_vec(112-1 downto 108);
|
||
|
|
local_incr_tx_vec(112-1 downto 108) <= inter_incr_out(3)(2)(1)(0)(4-1 downto 0);
|
||
|
|
|
||
|
|
inter_vc_write_in(3)(2)(1)(0)(4-1 downto 0) <= local_vc_write_rx(112-1 downto 108);
|
||
|
|
local_vc_write_tx(112-1 downto 108) <= inter_vc_write_out(3)(2)(1)(0)(4-1 downto 0);
|
||
|
|
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
-- Router at x= 3 y=2 z=1
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
router_321: entity work.router_pl
|
||
|
|
generic map (
|
||
|
|
port_num => 6,
|
||
|
|
Xis => 3,
|
||
|
|
Yis => 2,
|
||
|
|
Zis => 1,
|
||
|
|
header_incl_in_packet_length => true,
|
||
|
|
port_exist => (0,1,3,4,5,6),
|
||
|
|
vc_num_vec => (4, 4, 4, 4, 4, 4),
|
||
|
|
vc_num_out_vec => (4, 4, 4, 4, 4, 4),
|
||
|
|
vc_depth_array => ((4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4)),
|
||
|
|
vc_depth_out_array => ((4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4)),
|
||
|
|
rout_algo => "DXYU"
|
||
|
|
)
|
||
|
|
port map (
|
||
|
|
clk => clk,
|
||
|
|
rst => rst,
|
||
|
|
data_rx => data_in321,
|
||
|
|
vc_write_rx_vec => vc_write_rx_vec321,
|
||
|
|
incr_rx_vec => incr_rx_vec321,
|
||
|
|
data_tx_pl => data_out321,
|
||
|
|
vc_write_tx_pl_vec => vc_write_tx_pl_vec321,
|
||
|
|
incr_tx_pl_vec => incr_tx_pl_vec321
|
||
|
|
);
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
-- Router port connections to adjacent routers
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
data_in031(0) <= inter_data_in(0)(3)(1)(0);
|
||
|
|
inter_data_out(0)(3)(1)(0) <= data_out031(0);
|
||
|
|
incr_rx_vec031(4-1 downto 0) <= inter_incr_in(0)(3)(1)(0)(4-1 downto 0);
|
||
|
|
inter_incr_out(0)(3)(1)(0)(4-1 downto 0) <= incr_tx_pl_vec031(4-1 downto 0);
|
||
|
|
vc_write_rx_vec031(4-1 downto 0) <= inter_vc_write_in(0)(3)(1)(0)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(0)(3)(1)(0)(4-1 downto 0) <= vc_write_tx_pl_vec031(4-1 downto 0);
|
||
|
|
data_in031(1) <= inter_data_in(0)(3)(1)(2);
|
||
|
|
inter_data_out(0)(3)(1)(2) <= data_out031(1);
|
||
|
|
incr_rx_vec031(8-1 downto 4) <= inter_incr_in(0)(3)(1)(2)(4-1 downto 0);
|
||
|
|
inter_incr_out(0)(3)(1)(2)(4-1 downto 0) <= incr_tx_pl_vec031(8-1 downto 4);
|
||
|
|
vc_write_rx_vec031(8-1 downto 4) <= inter_vc_write_in(0)(3)(1)(2)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(0)(3)(1)(2)(4-1 downto 0) <= vc_write_tx_pl_vec031(8-1 downto 4);
|
||
|
|
|
||
|
|
inter_data_in(0)(3)(1)(2) <= inter_data_out(0+1)(3)(1)(4);
|
||
|
|
|
||
|
|
inter_incr_in(0)(3)(1)(2) <= inter_incr_out(0+1)(3)(1)(4);
|
||
|
|
|
||
|
|
inter_vc_write_in(0)(3)(1)(2) <= inter_vc_write_out(0+1)(3)(1)(4);
|
||
|
|
data_in031(2) <= inter_data_in(0)(3)(1)(3);
|
||
|
|
inter_data_out(0)(3)(1)(3) <= data_out031(2);
|
||
|
|
incr_rx_vec031(12-1 downto 8) <= inter_incr_in(0)(3)(1)(3)(4-1 downto 0);
|
||
|
|
inter_incr_out(0)(3)(1)(3)(4-1 downto 0) <= incr_tx_pl_vec031(12-1 downto 8);
|
||
|
|
vc_write_rx_vec031(12-1 downto 8) <= inter_vc_write_in(0)(3)(1)(3)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(0)(3)(1)(3)(4-1 downto 0) <= vc_write_tx_pl_vec031(12-1 downto 8);
|
||
|
|
|
||
|
|
inter_data_in(0)(3)(1)(3) <= inter_data_out(0)(3-1)(1)(1);
|
||
|
|
|
||
|
|
inter_incr_in(0)(3)(1)(3) <= inter_incr_out(0)(3-1)(1)(1);
|
||
|
|
|
||
|
|
inter_vc_write_in(0)(3)(1)(3) <= inter_vc_write_out(0)(3-1)(1)(1);
|
||
|
|
data_in031(3) <= inter_data_in(0)(3)(1)(5);
|
||
|
|
inter_data_out(0)(3)(1)(5) <= data_out031(3);
|
||
|
|
incr_rx_vec031(16-1 downto 12) <= inter_incr_in(0)(3)(1)(5)(4-1 downto 0);
|
||
|
|
inter_incr_out(0)(3)(1)(5)(4-1 downto 0) <= incr_tx_pl_vec031(16-1 downto 12);
|
||
|
|
vc_write_rx_vec031(16-1 downto 12) <= inter_vc_write_in(0)(3)(1)(5)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(0)(3)(1)(5)(4-1 downto 0) <= vc_write_tx_pl_vec031(16-1 downto 12);
|
||
|
|
|
||
|
|
inter_data_in(0)(3)(1)(5) <= inter_data_out(0)(3)(1+1)(6);
|
||
|
|
|
||
|
|
inter_incr_in(0)(3)(1)(5) <= inter_incr_out(0)(3)(1+1)(6);
|
||
|
|
|
||
|
|
inter_vc_write_in(0)(3)(1)(5) <= inter_vc_write_out(0)(3)(1+1)(6);
|
||
|
|
data_in031(4) <= inter_data_in(0)(3)(1)(6);
|
||
|
|
inter_data_out(0)(3)(1)(6) <= data_out031(4);
|
||
|
|
incr_rx_vec031(20-1 downto 16) <= inter_incr_in(0)(3)(1)(6)(4-1 downto 0);
|
||
|
|
inter_incr_out(0)(3)(1)(6)(4-1 downto 0) <= incr_tx_pl_vec031(20-1 downto 16);
|
||
|
|
vc_write_rx_vec031(20-1 downto 16) <= inter_vc_write_in(0)(3)(1)(6)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(0)(3)(1)(6)(4-1 downto 0) <= vc_write_tx_pl_vec031(20-1 downto 16);
|
||
|
|
|
||
|
|
inter_data_in(0)(3)(1)(6) <= inter_data_out(0)(3)(1-1)(5);
|
||
|
|
|
||
|
|
inter_incr_in(0)(3)(1)(6) <= inter_incr_out(0)(3)(1-1)(5);
|
||
|
|
|
||
|
|
inter_vc_write_in(0)(3)(1)(6) <= inter_vc_write_out(0)(3)(1-1)(5);
|
||
|
|
|
||
|
|
inter_data_in(0)(3)(1)(0) <= local_rx(28);
|
||
|
|
local_tx(28) <= inter_data_out(0)(3)(1)(0);
|
||
|
|
|
||
|
|
inter_incr_in(0)(3)(1)(0)(4-1 downto 0) <= local_incr_rx_vec(116-1 downto 112);
|
||
|
|
local_incr_tx_vec(116-1 downto 112) <= inter_incr_out(0)(3)(1)(0)(4-1 downto 0);
|
||
|
|
|
||
|
|
inter_vc_write_in(0)(3)(1)(0)(4-1 downto 0) <= local_vc_write_rx(116-1 downto 112);
|
||
|
|
local_vc_write_tx(116-1 downto 112) <= inter_vc_write_out(0)(3)(1)(0)(4-1 downto 0);
|
||
|
|
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
-- Router at x= 0 y=3 z=1
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
router_031: entity work.router_pl
|
||
|
|
generic map (
|
||
|
|
port_num => 5,
|
||
|
|
Xis => 0,
|
||
|
|
Yis => 3,
|
||
|
|
Zis => 1,
|
||
|
|
header_incl_in_packet_length => true,
|
||
|
|
port_exist => (0,2,3,5,6),
|
||
|
|
vc_num_vec => (4, 4, 4, 4, 4),
|
||
|
|
vc_num_out_vec => (4, 4, 4, 4, 4),
|
||
|
|
vc_depth_array => ((4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4)),
|
||
|
|
vc_depth_out_array => ((4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4)),
|
||
|
|
rout_algo => "DXYU"
|
||
|
|
)
|
||
|
|
port map (
|
||
|
|
clk => clk,
|
||
|
|
rst => rst,
|
||
|
|
data_rx => data_in031,
|
||
|
|
vc_write_rx_vec => vc_write_rx_vec031,
|
||
|
|
incr_rx_vec => incr_rx_vec031,
|
||
|
|
data_tx_pl => data_out031,
|
||
|
|
vc_write_tx_pl_vec => vc_write_tx_pl_vec031,
|
||
|
|
incr_tx_pl_vec => incr_tx_pl_vec031
|
||
|
|
);
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
-- Router port connections to adjacent routers
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
data_in131(0) <= inter_data_in(1)(3)(1)(0);
|
||
|
|
inter_data_out(1)(3)(1)(0) <= data_out131(0);
|
||
|
|
incr_rx_vec131(4-1 downto 0) <= inter_incr_in(1)(3)(1)(0)(4-1 downto 0);
|
||
|
|
inter_incr_out(1)(3)(1)(0)(4-1 downto 0) <= incr_tx_pl_vec131(4-1 downto 0);
|
||
|
|
vc_write_rx_vec131(4-1 downto 0) <= inter_vc_write_in(1)(3)(1)(0)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(1)(3)(1)(0)(4-1 downto 0) <= vc_write_tx_pl_vec131(4-1 downto 0);
|
||
|
|
data_in131(1) <= inter_data_in(1)(3)(1)(2);
|
||
|
|
inter_data_out(1)(3)(1)(2) <= data_out131(1);
|
||
|
|
incr_rx_vec131(8-1 downto 4) <= inter_incr_in(1)(3)(1)(2)(4-1 downto 0);
|
||
|
|
inter_incr_out(1)(3)(1)(2)(4-1 downto 0) <= incr_tx_pl_vec131(8-1 downto 4);
|
||
|
|
vc_write_rx_vec131(8-1 downto 4) <= inter_vc_write_in(1)(3)(1)(2)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(1)(3)(1)(2)(4-1 downto 0) <= vc_write_tx_pl_vec131(8-1 downto 4);
|
||
|
|
|
||
|
|
inter_data_in(1)(3)(1)(2) <= inter_data_out(1+1)(3)(1)(4);
|
||
|
|
|
||
|
|
inter_incr_in(1)(3)(1)(2) <= inter_incr_out(1+1)(3)(1)(4);
|
||
|
|
|
||
|
|
inter_vc_write_in(1)(3)(1)(2) <= inter_vc_write_out(1+1)(3)(1)(4);
|
||
|
|
data_in131(2) <= inter_data_in(1)(3)(1)(3);
|
||
|
|
inter_data_out(1)(3)(1)(3) <= data_out131(2);
|
||
|
|
incr_rx_vec131(12-1 downto 8) <= inter_incr_in(1)(3)(1)(3)(4-1 downto 0);
|
||
|
|
inter_incr_out(1)(3)(1)(3)(4-1 downto 0) <= incr_tx_pl_vec131(12-1 downto 8);
|
||
|
|
vc_write_rx_vec131(12-1 downto 8) <= inter_vc_write_in(1)(3)(1)(3)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(1)(3)(1)(3)(4-1 downto 0) <= vc_write_tx_pl_vec131(12-1 downto 8);
|
||
|
|
|
||
|
|
inter_data_in(1)(3)(1)(3) <= inter_data_out(1)(3-1)(1)(1);
|
||
|
|
|
||
|
|
inter_incr_in(1)(3)(1)(3) <= inter_incr_out(1)(3-1)(1)(1);
|
||
|
|
|
||
|
|
inter_vc_write_in(1)(3)(1)(3) <= inter_vc_write_out(1)(3-1)(1)(1);
|
||
|
|
data_in131(3) <= inter_data_in(1)(3)(1)(4);
|
||
|
|
inter_data_out(1)(3)(1)(4) <= data_out131(3);
|
||
|
|
incr_rx_vec131(16-1 downto 12) <= inter_incr_in(1)(3)(1)(4)(4-1 downto 0);
|
||
|
|
inter_incr_out(1)(3)(1)(4)(4-1 downto 0) <= incr_tx_pl_vec131(16-1 downto 12);
|
||
|
|
vc_write_rx_vec131(16-1 downto 12) <= inter_vc_write_in(1)(3)(1)(4)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(1)(3)(1)(4)(4-1 downto 0) <= vc_write_tx_pl_vec131(16-1 downto 12);
|
||
|
|
|
||
|
|
inter_data_in(1)(3)(1)(4) <= inter_data_out(1-1)(3)(1)(2);
|
||
|
|
|
||
|
|
inter_incr_in(1)(3)(1)(4) <= inter_incr_out(1-1)(3)(1)(2);
|
||
|
|
|
||
|
|
inter_vc_write_in(1)(3)(1)(4) <= inter_vc_write_out(1-1)(3)(1)(2);
|
||
|
|
data_in131(4) <= inter_data_in(1)(3)(1)(5);
|
||
|
|
inter_data_out(1)(3)(1)(5) <= data_out131(4);
|
||
|
|
incr_rx_vec131(20-1 downto 16) <= inter_incr_in(1)(3)(1)(5)(4-1 downto 0);
|
||
|
|
inter_incr_out(1)(3)(1)(5)(4-1 downto 0) <= incr_tx_pl_vec131(20-1 downto 16);
|
||
|
|
vc_write_rx_vec131(20-1 downto 16) <= inter_vc_write_in(1)(3)(1)(5)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(1)(3)(1)(5)(4-1 downto 0) <= vc_write_tx_pl_vec131(20-1 downto 16);
|
||
|
|
|
||
|
|
inter_data_in(1)(3)(1)(5) <= inter_data_out(1)(3)(1+1)(6);
|
||
|
|
|
||
|
|
inter_incr_in(1)(3)(1)(5) <= inter_incr_out(1)(3)(1+1)(6);
|
||
|
|
|
||
|
|
inter_vc_write_in(1)(3)(1)(5) <= inter_vc_write_out(1)(3)(1+1)(6);
|
||
|
|
data_in131(5) <= inter_data_in(1)(3)(1)(6);
|
||
|
|
inter_data_out(1)(3)(1)(6) <= data_out131(5);
|
||
|
|
incr_rx_vec131(24-1 downto 20) <= inter_incr_in(1)(3)(1)(6)(4-1 downto 0);
|
||
|
|
inter_incr_out(1)(3)(1)(6)(4-1 downto 0) <= incr_tx_pl_vec131(24-1 downto 20);
|
||
|
|
vc_write_rx_vec131(24-1 downto 20) <= inter_vc_write_in(1)(3)(1)(6)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(1)(3)(1)(6)(4-1 downto 0) <= vc_write_tx_pl_vec131(24-1 downto 20);
|
||
|
|
|
||
|
|
inter_data_in(1)(3)(1)(6) <= inter_data_out(1)(3)(1-1)(5);
|
||
|
|
|
||
|
|
inter_incr_in(1)(3)(1)(6) <= inter_incr_out(1)(3)(1-1)(5);
|
||
|
|
|
||
|
|
inter_vc_write_in(1)(3)(1)(6) <= inter_vc_write_out(1)(3)(1-1)(5);
|
||
|
|
|
||
|
|
inter_data_in(1)(3)(1)(0) <= local_rx(29);
|
||
|
|
local_tx(29) <= inter_data_out(1)(3)(1)(0);
|
||
|
|
|
||
|
|
inter_incr_in(1)(3)(1)(0)(4-1 downto 0) <= local_incr_rx_vec(120-1 downto 116);
|
||
|
|
local_incr_tx_vec(120-1 downto 116) <= inter_incr_out(1)(3)(1)(0)(4-1 downto 0);
|
||
|
|
|
||
|
|
inter_vc_write_in(1)(3)(1)(0)(4-1 downto 0) <= local_vc_write_rx(120-1 downto 116);
|
||
|
|
local_vc_write_tx(120-1 downto 116) <= inter_vc_write_out(1)(3)(1)(0)(4-1 downto 0);
|
||
|
|
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
-- Router at x= 1 y=3 z=1
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
router_131: entity work.router_pl
|
||
|
|
generic map (
|
||
|
|
port_num => 6,
|
||
|
|
Xis => 1,
|
||
|
|
Yis => 3,
|
||
|
|
Zis => 1,
|
||
|
|
header_incl_in_packet_length => true,
|
||
|
|
port_exist => (0,2,3,4,5,6),
|
||
|
|
vc_num_vec => (4, 4, 4, 4, 4, 4),
|
||
|
|
vc_num_out_vec => (4, 4, 4, 4, 4, 4),
|
||
|
|
vc_depth_array => ((4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4)),
|
||
|
|
vc_depth_out_array => ((4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4)),
|
||
|
|
rout_algo => "DXYU"
|
||
|
|
)
|
||
|
|
port map (
|
||
|
|
clk => clk,
|
||
|
|
rst => rst,
|
||
|
|
data_rx => data_in131,
|
||
|
|
vc_write_rx_vec => vc_write_rx_vec131,
|
||
|
|
incr_rx_vec => incr_rx_vec131,
|
||
|
|
data_tx_pl => data_out131,
|
||
|
|
vc_write_tx_pl_vec => vc_write_tx_pl_vec131,
|
||
|
|
incr_tx_pl_vec => incr_tx_pl_vec131
|
||
|
|
);
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
-- Router port connections to adjacent routers
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
data_in231(0) <= inter_data_in(2)(3)(1)(0);
|
||
|
|
inter_data_out(2)(3)(1)(0) <= data_out231(0);
|
||
|
|
incr_rx_vec231(4-1 downto 0) <= inter_incr_in(2)(3)(1)(0)(4-1 downto 0);
|
||
|
|
inter_incr_out(2)(3)(1)(0)(4-1 downto 0) <= incr_tx_pl_vec231(4-1 downto 0);
|
||
|
|
vc_write_rx_vec231(4-1 downto 0) <= inter_vc_write_in(2)(3)(1)(0)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(2)(3)(1)(0)(4-1 downto 0) <= vc_write_tx_pl_vec231(4-1 downto 0);
|
||
|
|
data_in231(1) <= inter_data_in(2)(3)(1)(2);
|
||
|
|
inter_data_out(2)(3)(1)(2) <= data_out231(1);
|
||
|
|
incr_rx_vec231(8-1 downto 4) <= inter_incr_in(2)(3)(1)(2)(4-1 downto 0);
|
||
|
|
inter_incr_out(2)(3)(1)(2)(4-1 downto 0) <= incr_tx_pl_vec231(8-1 downto 4);
|
||
|
|
vc_write_rx_vec231(8-1 downto 4) <= inter_vc_write_in(2)(3)(1)(2)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(2)(3)(1)(2)(4-1 downto 0) <= vc_write_tx_pl_vec231(8-1 downto 4);
|
||
|
|
|
||
|
|
inter_data_in(2)(3)(1)(2) <= inter_data_out(2+1)(3)(1)(4);
|
||
|
|
|
||
|
|
inter_incr_in(2)(3)(1)(2) <= inter_incr_out(2+1)(3)(1)(4);
|
||
|
|
|
||
|
|
inter_vc_write_in(2)(3)(1)(2) <= inter_vc_write_out(2+1)(3)(1)(4);
|
||
|
|
data_in231(2) <= inter_data_in(2)(3)(1)(3);
|
||
|
|
inter_data_out(2)(3)(1)(3) <= data_out231(2);
|
||
|
|
incr_rx_vec231(12-1 downto 8) <= inter_incr_in(2)(3)(1)(3)(4-1 downto 0);
|
||
|
|
inter_incr_out(2)(3)(1)(3)(4-1 downto 0) <= incr_tx_pl_vec231(12-1 downto 8);
|
||
|
|
vc_write_rx_vec231(12-1 downto 8) <= inter_vc_write_in(2)(3)(1)(3)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(2)(3)(1)(3)(4-1 downto 0) <= vc_write_tx_pl_vec231(12-1 downto 8);
|
||
|
|
|
||
|
|
inter_data_in(2)(3)(1)(3) <= inter_data_out(2)(3-1)(1)(1);
|
||
|
|
|
||
|
|
inter_incr_in(2)(3)(1)(3) <= inter_incr_out(2)(3-1)(1)(1);
|
||
|
|
|
||
|
|
inter_vc_write_in(2)(3)(1)(3) <= inter_vc_write_out(2)(3-1)(1)(1);
|
||
|
|
data_in231(3) <= inter_data_in(2)(3)(1)(4);
|
||
|
|
inter_data_out(2)(3)(1)(4) <= data_out231(3);
|
||
|
|
incr_rx_vec231(16-1 downto 12) <= inter_incr_in(2)(3)(1)(4)(4-1 downto 0);
|
||
|
|
inter_incr_out(2)(3)(1)(4)(4-1 downto 0) <= incr_tx_pl_vec231(16-1 downto 12);
|
||
|
|
vc_write_rx_vec231(16-1 downto 12) <= inter_vc_write_in(2)(3)(1)(4)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(2)(3)(1)(4)(4-1 downto 0) <= vc_write_tx_pl_vec231(16-1 downto 12);
|
||
|
|
|
||
|
|
inter_data_in(2)(3)(1)(4) <= inter_data_out(2-1)(3)(1)(2);
|
||
|
|
|
||
|
|
inter_incr_in(2)(3)(1)(4) <= inter_incr_out(2-1)(3)(1)(2);
|
||
|
|
|
||
|
|
inter_vc_write_in(2)(3)(1)(4) <= inter_vc_write_out(2-1)(3)(1)(2);
|
||
|
|
data_in231(4) <= inter_data_in(2)(3)(1)(5);
|
||
|
|
inter_data_out(2)(3)(1)(5) <= data_out231(4);
|
||
|
|
incr_rx_vec231(20-1 downto 16) <= inter_incr_in(2)(3)(1)(5)(4-1 downto 0);
|
||
|
|
inter_incr_out(2)(3)(1)(5)(4-1 downto 0) <= incr_tx_pl_vec231(20-1 downto 16);
|
||
|
|
vc_write_rx_vec231(20-1 downto 16) <= inter_vc_write_in(2)(3)(1)(5)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(2)(3)(1)(5)(4-1 downto 0) <= vc_write_tx_pl_vec231(20-1 downto 16);
|
||
|
|
|
||
|
|
inter_data_in(2)(3)(1)(5) <= inter_data_out(2)(3)(1+1)(6);
|
||
|
|
|
||
|
|
inter_incr_in(2)(3)(1)(5) <= inter_incr_out(2)(3)(1+1)(6);
|
||
|
|
|
||
|
|
inter_vc_write_in(2)(3)(1)(5) <= inter_vc_write_out(2)(3)(1+1)(6);
|
||
|
|
data_in231(5) <= inter_data_in(2)(3)(1)(6);
|
||
|
|
inter_data_out(2)(3)(1)(6) <= data_out231(5);
|
||
|
|
incr_rx_vec231(24-1 downto 20) <= inter_incr_in(2)(3)(1)(6)(4-1 downto 0);
|
||
|
|
inter_incr_out(2)(3)(1)(6)(4-1 downto 0) <= incr_tx_pl_vec231(24-1 downto 20);
|
||
|
|
vc_write_rx_vec231(24-1 downto 20) <= inter_vc_write_in(2)(3)(1)(6)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(2)(3)(1)(6)(4-1 downto 0) <= vc_write_tx_pl_vec231(24-1 downto 20);
|
||
|
|
|
||
|
|
inter_data_in(2)(3)(1)(6) <= inter_data_out(2)(3)(1-1)(5);
|
||
|
|
|
||
|
|
inter_incr_in(2)(3)(1)(6) <= inter_incr_out(2)(3)(1-1)(5);
|
||
|
|
|
||
|
|
inter_vc_write_in(2)(3)(1)(6) <= inter_vc_write_out(2)(3)(1-1)(5);
|
||
|
|
|
||
|
|
inter_data_in(2)(3)(1)(0) <= local_rx(30);
|
||
|
|
local_tx(30) <= inter_data_out(2)(3)(1)(0);
|
||
|
|
|
||
|
|
inter_incr_in(2)(3)(1)(0)(4-1 downto 0) <= local_incr_rx_vec(124-1 downto 120);
|
||
|
|
local_incr_tx_vec(124-1 downto 120) <= inter_incr_out(2)(3)(1)(0)(4-1 downto 0);
|
||
|
|
|
||
|
|
inter_vc_write_in(2)(3)(1)(0)(4-1 downto 0) <= local_vc_write_rx(124-1 downto 120);
|
||
|
|
local_vc_write_tx(124-1 downto 120) <= inter_vc_write_out(2)(3)(1)(0)(4-1 downto 0);
|
||
|
|
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
-- Router at x= 2 y=3 z=1
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
router_231: entity work.router_pl
|
||
|
|
generic map (
|
||
|
|
port_num => 6,
|
||
|
|
Xis => 2,
|
||
|
|
Yis => 3,
|
||
|
|
Zis => 1,
|
||
|
|
header_incl_in_packet_length => true,
|
||
|
|
port_exist => (0,2,3,4,5,6),
|
||
|
|
vc_num_vec => (4, 4, 4, 4, 4, 4),
|
||
|
|
vc_num_out_vec => (4, 4, 4, 4, 4, 4),
|
||
|
|
vc_depth_array => ((4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4)),
|
||
|
|
vc_depth_out_array => ((4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4)),
|
||
|
|
rout_algo => "DXYU"
|
||
|
|
)
|
||
|
|
port map (
|
||
|
|
clk => clk,
|
||
|
|
rst => rst,
|
||
|
|
data_rx => data_in231,
|
||
|
|
vc_write_rx_vec => vc_write_rx_vec231,
|
||
|
|
incr_rx_vec => incr_rx_vec231,
|
||
|
|
data_tx_pl => data_out231,
|
||
|
|
vc_write_tx_pl_vec => vc_write_tx_pl_vec231,
|
||
|
|
incr_tx_pl_vec => incr_tx_pl_vec231
|
||
|
|
);
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
-- Router port connections to adjacent routers
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
data_in331(0) <= inter_data_in(3)(3)(1)(0);
|
||
|
|
inter_data_out(3)(3)(1)(0) <= data_out331(0);
|
||
|
|
incr_rx_vec331(4-1 downto 0) <= inter_incr_in(3)(3)(1)(0)(4-1 downto 0);
|
||
|
|
inter_incr_out(3)(3)(1)(0)(4-1 downto 0) <= incr_tx_pl_vec331(4-1 downto 0);
|
||
|
|
vc_write_rx_vec331(4-1 downto 0) <= inter_vc_write_in(3)(3)(1)(0)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(3)(3)(1)(0)(4-1 downto 0) <= vc_write_tx_pl_vec331(4-1 downto 0);
|
||
|
|
data_in331(1) <= inter_data_in(3)(3)(1)(3);
|
||
|
|
inter_data_out(3)(3)(1)(3) <= data_out331(1);
|
||
|
|
incr_rx_vec331(8-1 downto 4) <= inter_incr_in(3)(3)(1)(3)(4-1 downto 0);
|
||
|
|
inter_incr_out(3)(3)(1)(3)(4-1 downto 0) <= incr_tx_pl_vec331(8-1 downto 4);
|
||
|
|
vc_write_rx_vec331(8-1 downto 4) <= inter_vc_write_in(3)(3)(1)(3)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(3)(3)(1)(3)(4-1 downto 0) <= vc_write_tx_pl_vec331(8-1 downto 4);
|
||
|
|
|
||
|
|
inter_data_in(3)(3)(1)(3) <= inter_data_out(3)(3-1)(1)(1);
|
||
|
|
|
||
|
|
inter_incr_in(3)(3)(1)(3) <= inter_incr_out(3)(3-1)(1)(1);
|
||
|
|
|
||
|
|
inter_vc_write_in(3)(3)(1)(3) <= inter_vc_write_out(3)(3-1)(1)(1);
|
||
|
|
data_in331(2) <= inter_data_in(3)(3)(1)(4);
|
||
|
|
inter_data_out(3)(3)(1)(4) <= data_out331(2);
|
||
|
|
incr_rx_vec331(12-1 downto 8) <= inter_incr_in(3)(3)(1)(4)(4-1 downto 0);
|
||
|
|
inter_incr_out(3)(3)(1)(4)(4-1 downto 0) <= incr_tx_pl_vec331(12-1 downto 8);
|
||
|
|
vc_write_rx_vec331(12-1 downto 8) <= inter_vc_write_in(3)(3)(1)(4)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(3)(3)(1)(4)(4-1 downto 0) <= vc_write_tx_pl_vec331(12-1 downto 8);
|
||
|
|
|
||
|
|
inter_data_in(3)(3)(1)(4) <= inter_data_out(3-1)(3)(1)(2);
|
||
|
|
|
||
|
|
inter_incr_in(3)(3)(1)(4) <= inter_incr_out(3-1)(3)(1)(2);
|
||
|
|
|
||
|
|
inter_vc_write_in(3)(3)(1)(4) <= inter_vc_write_out(3-1)(3)(1)(2);
|
||
|
|
data_in331(3) <= inter_data_in(3)(3)(1)(5);
|
||
|
|
inter_data_out(3)(3)(1)(5) <= data_out331(3);
|
||
|
|
incr_rx_vec331(16-1 downto 12) <= inter_incr_in(3)(3)(1)(5)(4-1 downto 0);
|
||
|
|
inter_incr_out(3)(3)(1)(5)(4-1 downto 0) <= incr_tx_pl_vec331(16-1 downto 12);
|
||
|
|
vc_write_rx_vec331(16-1 downto 12) <= inter_vc_write_in(3)(3)(1)(5)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(3)(3)(1)(5)(4-1 downto 0) <= vc_write_tx_pl_vec331(16-1 downto 12);
|
||
|
|
|
||
|
|
inter_data_in(3)(3)(1)(5) <= inter_data_out(3)(3)(1+1)(6);
|
||
|
|
|
||
|
|
inter_incr_in(3)(3)(1)(5) <= inter_incr_out(3)(3)(1+1)(6);
|
||
|
|
|
||
|
|
inter_vc_write_in(3)(3)(1)(5) <= inter_vc_write_out(3)(3)(1+1)(6);
|
||
|
|
data_in331(4) <= inter_data_in(3)(3)(1)(6);
|
||
|
|
inter_data_out(3)(3)(1)(6) <= data_out331(4);
|
||
|
|
incr_rx_vec331(20-1 downto 16) <= inter_incr_in(3)(3)(1)(6)(4-1 downto 0);
|
||
|
|
inter_incr_out(3)(3)(1)(6)(4-1 downto 0) <= incr_tx_pl_vec331(20-1 downto 16);
|
||
|
|
vc_write_rx_vec331(20-1 downto 16) <= inter_vc_write_in(3)(3)(1)(6)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(3)(3)(1)(6)(4-1 downto 0) <= vc_write_tx_pl_vec331(20-1 downto 16);
|
||
|
|
|
||
|
|
inter_data_in(3)(3)(1)(6) <= inter_data_out(3)(3)(1-1)(5);
|
||
|
|
|
||
|
|
inter_incr_in(3)(3)(1)(6) <= inter_incr_out(3)(3)(1-1)(5);
|
||
|
|
|
||
|
|
inter_vc_write_in(3)(3)(1)(6) <= inter_vc_write_out(3)(3)(1-1)(5);
|
||
|
|
|
||
|
|
inter_data_in(3)(3)(1)(0) <= local_rx(31);
|
||
|
|
local_tx(31) <= inter_data_out(3)(3)(1)(0);
|
||
|
|
|
||
|
|
inter_incr_in(3)(3)(1)(0)(4-1 downto 0) <= local_incr_rx_vec(128-1 downto 124);
|
||
|
|
local_incr_tx_vec(128-1 downto 124) <= inter_incr_out(3)(3)(1)(0)(4-1 downto 0);
|
||
|
|
|
||
|
|
inter_vc_write_in(3)(3)(1)(0)(4-1 downto 0) <= local_vc_write_rx(128-1 downto 124);
|
||
|
|
local_vc_write_tx(128-1 downto 124) <= inter_vc_write_out(3)(3)(1)(0)(4-1 downto 0);
|
||
|
|
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
-- Router at x= 3 y=3 z=1
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
router_331: entity work.router_pl
|
||
|
|
generic map (
|
||
|
|
port_num => 5,
|
||
|
|
Xis => 3,
|
||
|
|
Yis => 3,
|
||
|
|
Zis => 1,
|
||
|
|
header_incl_in_packet_length => true,
|
||
|
|
port_exist => (0,3,4,5,6),
|
||
|
|
vc_num_vec => (4, 4, 4, 4, 4),
|
||
|
|
vc_num_out_vec => (4, 4, 4, 4, 4),
|
||
|
|
vc_depth_array => ((4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4)),
|
||
|
|
vc_depth_out_array => ((4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4)),
|
||
|
|
rout_algo => "DXYU"
|
||
|
|
)
|
||
|
|
port map (
|
||
|
|
clk => clk,
|
||
|
|
rst => rst,
|
||
|
|
data_rx => data_in331,
|
||
|
|
vc_write_rx_vec => vc_write_rx_vec331,
|
||
|
|
incr_rx_vec => incr_rx_vec331,
|
||
|
|
data_tx_pl => data_out331,
|
||
|
|
vc_write_tx_pl_vec => vc_write_tx_pl_vec331,
|
||
|
|
incr_tx_pl_vec => incr_tx_pl_vec331
|
||
|
|
);
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
-- Router port connections to adjacent routers
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
data_in002(0) <= inter_data_in(0)(0)(2)(0);
|
||
|
|
inter_data_out(0)(0)(2)(0) <= data_out002(0);
|
||
|
|
incr_rx_vec002(4-1 downto 0) <= inter_incr_in(0)(0)(2)(0)(4-1 downto 0);
|
||
|
|
inter_incr_out(0)(0)(2)(0)(4-1 downto 0) <= incr_tx_pl_vec002(4-1 downto 0);
|
||
|
|
vc_write_rx_vec002(4-1 downto 0) <= inter_vc_write_in(0)(0)(2)(0)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(0)(0)(2)(0)(4-1 downto 0) <= vc_write_tx_pl_vec002(4-1 downto 0);
|
||
|
|
data_in002(1) <= inter_data_in(0)(0)(2)(1);
|
||
|
|
inter_data_out(0)(0)(2)(1) <= data_out002(1);
|
||
|
|
incr_rx_vec002(8-1 downto 4) <= inter_incr_in(0)(0)(2)(1)(4-1 downto 0);
|
||
|
|
inter_incr_out(0)(0)(2)(1)(4-1 downto 0) <= incr_tx_pl_vec002(8-1 downto 4);
|
||
|
|
vc_write_rx_vec002(8-1 downto 4) <= inter_vc_write_in(0)(0)(2)(1)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(0)(0)(2)(1)(4-1 downto 0) <= vc_write_tx_pl_vec002(8-1 downto 4);
|
||
|
|
|
||
|
|
inter_data_in(0)(0)(2)(1) <= inter_data_out(0)(0+1)(2)(3);
|
||
|
|
|
||
|
|
inter_incr_in(0)(0)(2)(1) <= inter_incr_out(0)(0+1)(2)(3);
|
||
|
|
|
||
|
|
inter_vc_write_in(0)(0)(2)(1) <= inter_vc_write_out(0)(0+1)(2)(3);
|
||
|
|
data_in002(2) <= inter_data_in(0)(0)(2)(2);
|
||
|
|
inter_data_out(0)(0)(2)(2) <= data_out002(2);
|
||
|
|
incr_rx_vec002(12-1 downto 8) <= inter_incr_in(0)(0)(2)(2)(4-1 downto 0);
|
||
|
|
inter_incr_out(0)(0)(2)(2)(4-1 downto 0) <= incr_tx_pl_vec002(12-1 downto 8);
|
||
|
|
vc_write_rx_vec002(12-1 downto 8) <= inter_vc_write_in(0)(0)(2)(2)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(0)(0)(2)(2)(4-1 downto 0) <= vc_write_tx_pl_vec002(12-1 downto 8);
|
||
|
|
|
||
|
|
inter_data_in(0)(0)(2)(2) <= inter_data_out(0+1)(0)(2)(4);
|
||
|
|
|
||
|
|
inter_incr_in(0)(0)(2)(2) <= inter_incr_out(0+1)(0)(2)(4);
|
||
|
|
|
||
|
|
inter_vc_write_in(0)(0)(2)(2) <= inter_vc_write_out(0+1)(0)(2)(4);
|
||
|
|
data_in002(3) <= inter_data_in(0)(0)(2)(6);
|
||
|
|
inter_data_out(0)(0)(2)(6) <= data_out002(3);
|
||
|
|
incr_rx_vec002(16-1 downto 12) <= inter_incr_in(0)(0)(2)(6)(4-1 downto 0);
|
||
|
|
inter_incr_out(0)(0)(2)(6)(4-1 downto 0) <= incr_tx_pl_vec002(16-1 downto 12);
|
||
|
|
vc_write_rx_vec002(16-1 downto 12) <= inter_vc_write_in(0)(0)(2)(6)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(0)(0)(2)(6)(4-1 downto 0) <= vc_write_tx_pl_vec002(16-1 downto 12);
|
||
|
|
|
||
|
|
inter_data_in(0)(0)(2)(6) <= inter_data_out(0)(0)(2-1)(5);
|
||
|
|
|
||
|
|
inter_incr_in(0)(0)(2)(6) <= inter_incr_out(0)(0)(2-1)(5);
|
||
|
|
|
||
|
|
inter_vc_write_in(0)(0)(2)(6) <= inter_vc_write_out(0)(0)(2-1)(5);
|
||
|
|
|
||
|
|
inter_data_in(0)(0)(2)(0) <= local_rx(32);
|
||
|
|
local_tx(32) <= inter_data_out(0)(0)(2)(0);
|
||
|
|
|
||
|
|
inter_incr_in(0)(0)(2)(0)(4-1 downto 0) <= local_incr_rx_vec(132-1 downto 128);
|
||
|
|
local_incr_tx_vec(132-1 downto 128) <= inter_incr_out(0)(0)(2)(0)(4-1 downto 0);
|
||
|
|
|
||
|
|
inter_vc_write_in(0)(0)(2)(0)(4-1 downto 0) <= local_vc_write_rx(132-1 downto 128);
|
||
|
|
local_vc_write_tx(132-1 downto 128) <= inter_vc_write_out(0)(0)(2)(0)(4-1 downto 0);
|
||
|
|
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
-- Router at x= 0 y=0 z=2
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
router_002: entity work.router_pl
|
||
|
|
generic map (
|
||
|
|
port_num => 4,
|
||
|
|
Xis => 0,
|
||
|
|
Yis => 0,
|
||
|
|
Zis => 2,
|
||
|
|
header_incl_in_packet_length => true,
|
||
|
|
port_exist => (0,1,2,6),
|
||
|
|
vc_num_vec => (4, 4, 4, 4),
|
||
|
|
vc_num_out_vec => (4, 4, 4, 4),
|
||
|
|
vc_depth_array => ((4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4)),
|
||
|
|
vc_depth_out_array => ((4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4)),
|
||
|
|
rout_algo => "DXYU"
|
||
|
|
)
|
||
|
|
port map (
|
||
|
|
clk => clk,
|
||
|
|
rst => rst,
|
||
|
|
data_rx => data_in002,
|
||
|
|
vc_write_rx_vec => vc_write_rx_vec002,
|
||
|
|
incr_rx_vec => incr_rx_vec002,
|
||
|
|
data_tx_pl => data_out002,
|
||
|
|
vc_write_tx_pl_vec => vc_write_tx_pl_vec002,
|
||
|
|
incr_tx_pl_vec => incr_tx_pl_vec002
|
||
|
|
);
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
-- Router port connections to adjacent routers
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
data_in102(0) <= inter_data_in(1)(0)(2)(0);
|
||
|
|
inter_data_out(1)(0)(2)(0) <= data_out102(0);
|
||
|
|
incr_rx_vec102(4-1 downto 0) <= inter_incr_in(1)(0)(2)(0)(4-1 downto 0);
|
||
|
|
inter_incr_out(1)(0)(2)(0)(4-1 downto 0) <= incr_tx_pl_vec102(4-1 downto 0);
|
||
|
|
vc_write_rx_vec102(4-1 downto 0) <= inter_vc_write_in(1)(0)(2)(0)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(1)(0)(2)(0)(4-1 downto 0) <= vc_write_tx_pl_vec102(4-1 downto 0);
|
||
|
|
data_in102(1) <= inter_data_in(1)(0)(2)(1);
|
||
|
|
inter_data_out(1)(0)(2)(1) <= data_out102(1);
|
||
|
|
incr_rx_vec102(8-1 downto 4) <= inter_incr_in(1)(0)(2)(1)(4-1 downto 0);
|
||
|
|
inter_incr_out(1)(0)(2)(1)(4-1 downto 0) <= incr_tx_pl_vec102(8-1 downto 4);
|
||
|
|
vc_write_rx_vec102(8-1 downto 4) <= inter_vc_write_in(1)(0)(2)(1)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(1)(0)(2)(1)(4-1 downto 0) <= vc_write_tx_pl_vec102(8-1 downto 4);
|
||
|
|
|
||
|
|
inter_data_in(1)(0)(2)(1) <= inter_data_out(1)(0+1)(2)(3);
|
||
|
|
|
||
|
|
inter_incr_in(1)(0)(2)(1) <= inter_incr_out(1)(0+1)(2)(3);
|
||
|
|
|
||
|
|
inter_vc_write_in(1)(0)(2)(1) <= inter_vc_write_out(1)(0+1)(2)(3);
|
||
|
|
data_in102(2) <= inter_data_in(1)(0)(2)(2);
|
||
|
|
inter_data_out(1)(0)(2)(2) <= data_out102(2);
|
||
|
|
incr_rx_vec102(12-1 downto 8) <= inter_incr_in(1)(0)(2)(2)(4-1 downto 0);
|
||
|
|
inter_incr_out(1)(0)(2)(2)(4-1 downto 0) <= incr_tx_pl_vec102(12-1 downto 8);
|
||
|
|
vc_write_rx_vec102(12-1 downto 8) <= inter_vc_write_in(1)(0)(2)(2)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(1)(0)(2)(2)(4-1 downto 0) <= vc_write_tx_pl_vec102(12-1 downto 8);
|
||
|
|
|
||
|
|
inter_data_in(1)(0)(2)(2) <= inter_data_out(1+1)(0)(2)(4);
|
||
|
|
|
||
|
|
inter_incr_in(1)(0)(2)(2) <= inter_incr_out(1+1)(0)(2)(4);
|
||
|
|
|
||
|
|
inter_vc_write_in(1)(0)(2)(2) <= inter_vc_write_out(1+1)(0)(2)(4);
|
||
|
|
data_in102(3) <= inter_data_in(1)(0)(2)(4);
|
||
|
|
inter_data_out(1)(0)(2)(4) <= data_out102(3);
|
||
|
|
incr_rx_vec102(16-1 downto 12) <= inter_incr_in(1)(0)(2)(4)(4-1 downto 0);
|
||
|
|
inter_incr_out(1)(0)(2)(4)(4-1 downto 0) <= incr_tx_pl_vec102(16-1 downto 12);
|
||
|
|
vc_write_rx_vec102(16-1 downto 12) <= inter_vc_write_in(1)(0)(2)(4)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(1)(0)(2)(4)(4-1 downto 0) <= vc_write_tx_pl_vec102(16-1 downto 12);
|
||
|
|
|
||
|
|
inter_data_in(1)(0)(2)(4) <= inter_data_out(1-1)(0)(2)(2);
|
||
|
|
|
||
|
|
inter_incr_in(1)(0)(2)(4) <= inter_incr_out(1-1)(0)(2)(2);
|
||
|
|
|
||
|
|
inter_vc_write_in(1)(0)(2)(4) <= inter_vc_write_out(1-1)(0)(2)(2);
|
||
|
|
data_in102(4) <= inter_data_in(1)(0)(2)(6);
|
||
|
|
inter_data_out(1)(0)(2)(6) <= data_out102(4);
|
||
|
|
incr_rx_vec102(20-1 downto 16) <= inter_incr_in(1)(0)(2)(6)(4-1 downto 0);
|
||
|
|
inter_incr_out(1)(0)(2)(6)(4-1 downto 0) <= incr_tx_pl_vec102(20-1 downto 16);
|
||
|
|
vc_write_rx_vec102(20-1 downto 16) <= inter_vc_write_in(1)(0)(2)(6)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(1)(0)(2)(6)(4-1 downto 0) <= vc_write_tx_pl_vec102(20-1 downto 16);
|
||
|
|
|
||
|
|
inter_data_in(1)(0)(2)(6) <= inter_data_out(1)(0)(2-1)(5);
|
||
|
|
|
||
|
|
inter_incr_in(1)(0)(2)(6) <= inter_incr_out(1)(0)(2-1)(5);
|
||
|
|
|
||
|
|
inter_vc_write_in(1)(0)(2)(6) <= inter_vc_write_out(1)(0)(2-1)(5);
|
||
|
|
|
||
|
|
inter_data_in(1)(0)(2)(0) <= local_rx(33);
|
||
|
|
local_tx(33) <= inter_data_out(1)(0)(2)(0);
|
||
|
|
|
||
|
|
inter_incr_in(1)(0)(2)(0)(4-1 downto 0) <= local_incr_rx_vec(136-1 downto 132);
|
||
|
|
local_incr_tx_vec(136-1 downto 132) <= inter_incr_out(1)(0)(2)(0)(4-1 downto 0);
|
||
|
|
|
||
|
|
inter_vc_write_in(1)(0)(2)(0)(4-1 downto 0) <= local_vc_write_rx(136-1 downto 132);
|
||
|
|
local_vc_write_tx(136-1 downto 132) <= inter_vc_write_out(1)(0)(2)(0)(4-1 downto 0);
|
||
|
|
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
-- Router at x= 1 y=0 z=2
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
router_102: entity work.router_pl
|
||
|
|
generic map (
|
||
|
|
port_num => 5,
|
||
|
|
Xis => 1,
|
||
|
|
Yis => 0,
|
||
|
|
Zis => 2,
|
||
|
|
header_incl_in_packet_length => true,
|
||
|
|
port_exist => (0,1,2,4,6),
|
||
|
|
vc_num_vec => (4, 4, 4, 4, 4),
|
||
|
|
vc_num_out_vec => (4, 4, 4, 4, 4),
|
||
|
|
vc_depth_array => ((4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4)),
|
||
|
|
vc_depth_out_array => ((4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4)),
|
||
|
|
rout_algo => "DXYU"
|
||
|
|
)
|
||
|
|
port map (
|
||
|
|
clk => clk,
|
||
|
|
rst => rst,
|
||
|
|
data_rx => data_in102,
|
||
|
|
vc_write_rx_vec => vc_write_rx_vec102,
|
||
|
|
incr_rx_vec => incr_rx_vec102,
|
||
|
|
data_tx_pl => data_out102,
|
||
|
|
vc_write_tx_pl_vec => vc_write_tx_pl_vec102,
|
||
|
|
incr_tx_pl_vec => incr_tx_pl_vec102
|
||
|
|
);
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
-- Router port connections to adjacent routers
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
data_in202(0) <= inter_data_in(2)(0)(2)(0);
|
||
|
|
inter_data_out(2)(0)(2)(0) <= data_out202(0);
|
||
|
|
incr_rx_vec202(4-1 downto 0) <= inter_incr_in(2)(0)(2)(0)(4-1 downto 0);
|
||
|
|
inter_incr_out(2)(0)(2)(0)(4-1 downto 0) <= incr_tx_pl_vec202(4-1 downto 0);
|
||
|
|
vc_write_rx_vec202(4-1 downto 0) <= inter_vc_write_in(2)(0)(2)(0)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(2)(0)(2)(0)(4-1 downto 0) <= vc_write_tx_pl_vec202(4-1 downto 0);
|
||
|
|
data_in202(1) <= inter_data_in(2)(0)(2)(1);
|
||
|
|
inter_data_out(2)(0)(2)(1) <= data_out202(1);
|
||
|
|
incr_rx_vec202(8-1 downto 4) <= inter_incr_in(2)(0)(2)(1)(4-1 downto 0);
|
||
|
|
inter_incr_out(2)(0)(2)(1)(4-1 downto 0) <= incr_tx_pl_vec202(8-1 downto 4);
|
||
|
|
vc_write_rx_vec202(8-1 downto 4) <= inter_vc_write_in(2)(0)(2)(1)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(2)(0)(2)(1)(4-1 downto 0) <= vc_write_tx_pl_vec202(8-1 downto 4);
|
||
|
|
|
||
|
|
inter_data_in(2)(0)(2)(1) <= inter_data_out(2)(0+1)(2)(3);
|
||
|
|
|
||
|
|
inter_incr_in(2)(0)(2)(1) <= inter_incr_out(2)(0+1)(2)(3);
|
||
|
|
|
||
|
|
inter_vc_write_in(2)(0)(2)(1) <= inter_vc_write_out(2)(0+1)(2)(3);
|
||
|
|
data_in202(2) <= inter_data_in(2)(0)(2)(2);
|
||
|
|
inter_data_out(2)(0)(2)(2) <= data_out202(2);
|
||
|
|
incr_rx_vec202(12-1 downto 8) <= inter_incr_in(2)(0)(2)(2)(4-1 downto 0);
|
||
|
|
inter_incr_out(2)(0)(2)(2)(4-1 downto 0) <= incr_tx_pl_vec202(12-1 downto 8);
|
||
|
|
vc_write_rx_vec202(12-1 downto 8) <= inter_vc_write_in(2)(0)(2)(2)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(2)(0)(2)(2)(4-1 downto 0) <= vc_write_tx_pl_vec202(12-1 downto 8);
|
||
|
|
|
||
|
|
inter_data_in(2)(0)(2)(2) <= inter_data_out(2+1)(0)(2)(4);
|
||
|
|
|
||
|
|
inter_incr_in(2)(0)(2)(2) <= inter_incr_out(2+1)(0)(2)(4);
|
||
|
|
|
||
|
|
inter_vc_write_in(2)(0)(2)(2) <= inter_vc_write_out(2+1)(0)(2)(4);
|
||
|
|
data_in202(3) <= inter_data_in(2)(0)(2)(4);
|
||
|
|
inter_data_out(2)(0)(2)(4) <= data_out202(3);
|
||
|
|
incr_rx_vec202(16-1 downto 12) <= inter_incr_in(2)(0)(2)(4)(4-1 downto 0);
|
||
|
|
inter_incr_out(2)(0)(2)(4)(4-1 downto 0) <= incr_tx_pl_vec202(16-1 downto 12);
|
||
|
|
vc_write_rx_vec202(16-1 downto 12) <= inter_vc_write_in(2)(0)(2)(4)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(2)(0)(2)(4)(4-1 downto 0) <= vc_write_tx_pl_vec202(16-1 downto 12);
|
||
|
|
|
||
|
|
inter_data_in(2)(0)(2)(4) <= inter_data_out(2-1)(0)(2)(2);
|
||
|
|
|
||
|
|
inter_incr_in(2)(0)(2)(4) <= inter_incr_out(2-1)(0)(2)(2);
|
||
|
|
|
||
|
|
inter_vc_write_in(2)(0)(2)(4) <= inter_vc_write_out(2-1)(0)(2)(2);
|
||
|
|
data_in202(4) <= inter_data_in(2)(0)(2)(6);
|
||
|
|
inter_data_out(2)(0)(2)(6) <= data_out202(4);
|
||
|
|
incr_rx_vec202(20-1 downto 16) <= inter_incr_in(2)(0)(2)(6)(4-1 downto 0);
|
||
|
|
inter_incr_out(2)(0)(2)(6)(4-1 downto 0) <= incr_tx_pl_vec202(20-1 downto 16);
|
||
|
|
vc_write_rx_vec202(20-1 downto 16) <= inter_vc_write_in(2)(0)(2)(6)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(2)(0)(2)(6)(4-1 downto 0) <= vc_write_tx_pl_vec202(20-1 downto 16);
|
||
|
|
|
||
|
|
inter_data_in(2)(0)(2)(6) <= inter_data_out(2)(0)(2-1)(5);
|
||
|
|
|
||
|
|
inter_incr_in(2)(0)(2)(6) <= inter_incr_out(2)(0)(2-1)(5);
|
||
|
|
|
||
|
|
inter_vc_write_in(2)(0)(2)(6) <= inter_vc_write_out(2)(0)(2-1)(5);
|
||
|
|
|
||
|
|
inter_data_in(2)(0)(2)(0) <= local_rx(34);
|
||
|
|
local_tx(34) <= inter_data_out(2)(0)(2)(0);
|
||
|
|
|
||
|
|
inter_incr_in(2)(0)(2)(0)(4-1 downto 0) <= local_incr_rx_vec(140-1 downto 136);
|
||
|
|
local_incr_tx_vec(140-1 downto 136) <= inter_incr_out(2)(0)(2)(0)(4-1 downto 0);
|
||
|
|
|
||
|
|
inter_vc_write_in(2)(0)(2)(0)(4-1 downto 0) <= local_vc_write_rx(140-1 downto 136);
|
||
|
|
local_vc_write_tx(140-1 downto 136) <= inter_vc_write_out(2)(0)(2)(0)(4-1 downto 0);
|
||
|
|
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
-- Router at x= 2 y=0 z=2
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
router_202: entity work.router_pl
|
||
|
|
generic map (
|
||
|
|
port_num => 5,
|
||
|
|
Xis => 2,
|
||
|
|
Yis => 0,
|
||
|
|
Zis => 2,
|
||
|
|
header_incl_in_packet_length => true,
|
||
|
|
port_exist => (0,1,2,4,6),
|
||
|
|
vc_num_vec => (4, 4, 4, 4, 4),
|
||
|
|
vc_num_out_vec => (4, 4, 4, 4, 4),
|
||
|
|
vc_depth_array => ((4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4)),
|
||
|
|
vc_depth_out_array => ((4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4)),
|
||
|
|
rout_algo => "DXYU"
|
||
|
|
)
|
||
|
|
port map (
|
||
|
|
clk => clk,
|
||
|
|
rst => rst,
|
||
|
|
data_rx => data_in202,
|
||
|
|
vc_write_rx_vec => vc_write_rx_vec202,
|
||
|
|
incr_rx_vec => incr_rx_vec202,
|
||
|
|
data_tx_pl => data_out202,
|
||
|
|
vc_write_tx_pl_vec => vc_write_tx_pl_vec202,
|
||
|
|
incr_tx_pl_vec => incr_tx_pl_vec202
|
||
|
|
);
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
-- Router port connections to adjacent routers
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
data_in302(0) <= inter_data_in(3)(0)(2)(0);
|
||
|
|
inter_data_out(3)(0)(2)(0) <= data_out302(0);
|
||
|
|
incr_rx_vec302(4-1 downto 0) <= inter_incr_in(3)(0)(2)(0)(4-1 downto 0);
|
||
|
|
inter_incr_out(3)(0)(2)(0)(4-1 downto 0) <= incr_tx_pl_vec302(4-1 downto 0);
|
||
|
|
vc_write_rx_vec302(4-1 downto 0) <= inter_vc_write_in(3)(0)(2)(0)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(3)(0)(2)(0)(4-1 downto 0) <= vc_write_tx_pl_vec302(4-1 downto 0);
|
||
|
|
data_in302(1) <= inter_data_in(3)(0)(2)(1);
|
||
|
|
inter_data_out(3)(0)(2)(1) <= data_out302(1);
|
||
|
|
incr_rx_vec302(8-1 downto 4) <= inter_incr_in(3)(0)(2)(1)(4-1 downto 0);
|
||
|
|
inter_incr_out(3)(0)(2)(1)(4-1 downto 0) <= incr_tx_pl_vec302(8-1 downto 4);
|
||
|
|
vc_write_rx_vec302(8-1 downto 4) <= inter_vc_write_in(3)(0)(2)(1)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(3)(0)(2)(1)(4-1 downto 0) <= vc_write_tx_pl_vec302(8-1 downto 4);
|
||
|
|
|
||
|
|
inter_data_in(3)(0)(2)(1) <= inter_data_out(3)(0+1)(2)(3);
|
||
|
|
|
||
|
|
inter_incr_in(3)(0)(2)(1) <= inter_incr_out(3)(0+1)(2)(3);
|
||
|
|
|
||
|
|
inter_vc_write_in(3)(0)(2)(1) <= inter_vc_write_out(3)(0+1)(2)(3);
|
||
|
|
data_in302(2) <= inter_data_in(3)(0)(2)(4);
|
||
|
|
inter_data_out(3)(0)(2)(4) <= data_out302(2);
|
||
|
|
incr_rx_vec302(12-1 downto 8) <= inter_incr_in(3)(0)(2)(4)(4-1 downto 0);
|
||
|
|
inter_incr_out(3)(0)(2)(4)(4-1 downto 0) <= incr_tx_pl_vec302(12-1 downto 8);
|
||
|
|
vc_write_rx_vec302(12-1 downto 8) <= inter_vc_write_in(3)(0)(2)(4)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(3)(0)(2)(4)(4-1 downto 0) <= vc_write_tx_pl_vec302(12-1 downto 8);
|
||
|
|
|
||
|
|
inter_data_in(3)(0)(2)(4) <= inter_data_out(3-1)(0)(2)(2);
|
||
|
|
|
||
|
|
inter_incr_in(3)(0)(2)(4) <= inter_incr_out(3-1)(0)(2)(2);
|
||
|
|
|
||
|
|
inter_vc_write_in(3)(0)(2)(4) <= inter_vc_write_out(3-1)(0)(2)(2);
|
||
|
|
data_in302(3) <= inter_data_in(3)(0)(2)(6);
|
||
|
|
inter_data_out(3)(0)(2)(6) <= data_out302(3);
|
||
|
|
incr_rx_vec302(16-1 downto 12) <= inter_incr_in(3)(0)(2)(6)(4-1 downto 0);
|
||
|
|
inter_incr_out(3)(0)(2)(6)(4-1 downto 0) <= incr_tx_pl_vec302(16-1 downto 12);
|
||
|
|
vc_write_rx_vec302(16-1 downto 12) <= inter_vc_write_in(3)(0)(2)(6)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(3)(0)(2)(6)(4-1 downto 0) <= vc_write_tx_pl_vec302(16-1 downto 12);
|
||
|
|
|
||
|
|
inter_data_in(3)(0)(2)(6) <= inter_data_out(3)(0)(2-1)(5);
|
||
|
|
|
||
|
|
inter_incr_in(3)(0)(2)(6) <= inter_incr_out(3)(0)(2-1)(5);
|
||
|
|
|
||
|
|
inter_vc_write_in(3)(0)(2)(6) <= inter_vc_write_out(3)(0)(2-1)(5);
|
||
|
|
|
||
|
|
inter_data_in(3)(0)(2)(0) <= local_rx(35);
|
||
|
|
local_tx(35) <= inter_data_out(3)(0)(2)(0);
|
||
|
|
|
||
|
|
inter_incr_in(3)(0)(2)(0)(4-1 downto 0) <= local_incr_rx_vec(144-1 downto 140);
|
||
|
|
local_incr_tx_vec(144-1 downto 140) <= inter_incr_out(3)(0)(2)(0)(4-1 downto 0);
|
||
|
|
|
||
|
|
inter_vc_write_in(3)(0)(2)(0)(4-1 downto 0) <= local_vc_write_rx(144-1 downto 140);
|
||
|
|
local_vc_write_tx(144-1 downto 140) <= inter_vc_write_out(3)(0)(2)(0)(4-1 downto 0);
|
||
|
|
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
-- Router at x= 3 y=0 z=2
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
router_302: entity work.router_pl
|
||
|
|
generic map (
|
||
|
|
port_num => 4,
|
||
|
|
Xis => 3,
|
||
|
|
Yis => 0,
|
||
|
|
Zis => 2,
|
||
|
|
header_incl_in_packet_length => true,
|
||
|
|
port_exist => (0,1,4,6),
|
||
|
|
vc_num_vec => (4, 4, 4, 4),
|
||
|
|
vc_num_out_vec => (4, 4, 4, 4),
|
||
|
|
vc_depth_array => ((4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4)),
|
||
|
|
vc_depth_out_array => ((4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4)),
|
||
|
|
rout_algo => "DXYU"
|
||
|
|
)
|
||
|
|
port map (
|
||
|
|
clk => clk,
|
||
|
|
rst => rst,
|
||
|
|
data_rx => data_in302,
|
||
|
|
vc_write_rx_vec => vc_write_rx_vec302,
|
||
|
|
incr_rx_vec => incr_rx_vec302,
|
||
|
|
data_tx_pl => data_out302,
|
||
|
|
vc_write_tx_pl_vec => vc_write_tx_pl_vec302,
|
||
|
|
incr_tx_pl_vec => incr_tx_pl_vec302
|
||
|
|
);
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
-- Router port connections to adjacent routers
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
data_in012(0) <= inter_data_in(0)(1)(2)(0);
|
||
|
|
inter_data_out(0)(1)(2)(0) <= data_out012(0);
|
||
|
|
incr_rx_vec012(4-1 downto 0) <= inter_incr_in(0)(1)(2)(0)(4-1 downto 0);
|
||
|
|
inter_incr_out(0)(1)(2)(0)(4-1 downto 0) <= incr_tx_pl_vec012(4-1 downto 0);
|
||
|
|
vc_write_rx_vec012(4-1 downto 0) <= inter_vc_write_in(0)(1)(2)(0)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(0)(1)(2)(0)(4-1 downto 0) <= vc_write_tx_pl_vec012(4-1 downto 0);
|
||
|
|
data_in012(1) <= inter_data_in(0)(1)(2)(1);
|
||
|
|
inter_data_out(0)(1)(2)(1) <= data_out012(1);
|
||
|
|
incr_rx_vec012(8-1 downto 4) <= inter_incr_in(0)(1)(2)(1)(4-1 downto 0);
|
||
|
|
inter_incr_out(0)(1)(2)(1)(4-1 downto 0) <= incr_tx_pl_vec012(8-1 downto 4);
|
||
|
|
vc_write_rx_vec012(8-1 downto 4) <= inter_vc_write_in(0)(1)(2)(1)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(0)(1)(2)(1)(4-1 downto 0) <= vc_write_tx_pl_vec012(8-1 downto 4);
|
||
|
|
|
||
|
|
inter_data_in(0)(1)(2)(1) <= inter_data_out(0)(1+1)(2)(3);
|
||
|
|
|
||
|
|
inter_incr_in(0)(1)(2)(1) <= inter_incr_out(0)(1+1)(2)(3);
|
||
|
|
|
||
|
|
inter_vc_write_in(0)(1)(2)(1) <= inter_vc_write_out(0)(1+1)(2)(3);
|
||
|
|
data_in012(2) <= inter_data_in(0)(1)(2)(2);
|
||
|
|
inter_data_out(0)(1)(2)(2) <= data_out012(2);
|
||
|
|
incr_rx_vec012(12-1 downto 8) <= inter_incr_in(0)(1)(2)(2)(4-1 downto 0);
|
||
|
|
inter_incr_out(0)(1)(2)(2)(4-1 downto 0) <= incr_tx_pl_vec012(12-1 downto 8);
|
||
|
|
vc_write_rx_vec012(12-1 downto 8) <= inter_vc_write_in(0)(1)(2)(2)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(0)(1)(2)(2)(4-1 downto 0) <= vc_write_tx_pl_vec012(12-1 downto 8);
|
||
|
|
|
||
|
|
inter_data_in(0)(1)(2)(2) <= inter_data_out(0+1)(1)(2)(4);
|
||
|
|
|
||
|
|
inter_incr_in(0)(1)(2)(2) <= inter_incr_out(0+1)(1)(2)(4);
|
||
|
|
|
||
|
|
inter_vc_write_in(0)(1)(2)(2) <= inter_vc_write_out(0+1)(1)(2)(4);
|
||
|
|
data_in012(3) <= inter_data_in(0)(1)(2)(3);
|
||
|
|
inter_data_out(0)(1)(2)(3) <= data_out012(3);
|
||
|
|
incr_rx_vec012(16-1 downto 12) <= inter_incr_in(0)(1)(2)(3)(4-1 downto 0);
|
||
|
|
inter_incr_out(0)(1)(2)(3)(4-1 downto 0) <= incr_tx_pl_vec012(16-1 downto 12);
|
||
|
|
vc_write_rx_vec012(16-1 downto 12) <= inter_vc_write_in(0)(1)(2)(3)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(0)(1)(2)(3)(4-1 downto 0) <= vc_write_tx_pl_vec012(16-1 downto 12);
|
||
|
|
|
||
|
|
inter_data_in(0)(1)(2)(3) <= inter_data_out(0)(1-1)(2)(1);
|
||
|
|
|
||
|
|
inter_incr_in(0)(1)(2)(3) <= inter_incr_out(0)(1-1)(2)(1);
|
||
|
|
|
||
|
|
inter_vc_write_in(0)(1)(2)(3) <= inter_vc_write_out(0)(1-1)(2)(1);
|
||
|
|
data_in012(4) <= inter_data_in(0)(1)(2)(6);
|
||
|
|
inter_data_out(0)(1)(2)(6) <= data_out012(4);
|
||
|
|
incr_rx_vec012(20-1 downto 16) <= inter_incr_in(0)(1)(2)(6)(4-1 downto 0);
|
||
|
|
inter_incr_out(0)(1)(2)(6)(4-1 downto 0) <= incr_tx_pl_vec012(20-1 downto 16);
|
||
|
|
vc_write_rx_vec012(20-1 downto 16) <= inter_vc_write_in(0)(1)(2)(6)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(0)(1)(2)(6)(4-1 downto 0) <= vc_write_tx_pl_vec012(20-1 downto 16);
|
||
|
|
|
||
|
|
inter_data_in(0)(1)(2)(6) <= inter_data_out(0)(1)(2-1)(5);
|
||
|
|
|
||
|
|
inter_incr_in(0)(1)(2)(6) <= inter_incr_out(0)(1)(2-1)(5);
|
||
|
|
|
||
|
|
inter_vc_write_in(0)(1)(2)(6) <= inter_vc_write_out(0)(1)(2-1)(5);
|
||
|
|
|
||
|
|
inter_data_in(0)(1)(2)(0) <= local_rx(36);
|
||
|
|
local_tx(36) <= inter_data_out(0)(1)(2)(0);
|
||
|
|
|
||
|
|
inter_incr_in(0)(1)(2)(0)(4-1 downto 0) <= local_incr_rx_vec(148-1 downto 144);
|
||
|
|
local_incr_tx_vec(148-1 downto 144) <= inter_incr_out(0)(1)(2)(0)(4-1 downto 0);
|
||
|
|
|
||
|
|
inter_vc_write_in(0)(1)(2)(0)(4-1 downto 0) <= local_vc_write_rx(148-1 downto 144);
|
||
|
|
local_vc_write_tx(148-1 downto 144) <= inter_vc_write_out(0)(1)(2)(0)(4-1 downto 0);
|
||
|
|
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
-- Router at x= 0 y=1 z=2
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
router_012: entity work.router_pl
|
||
|
|
generic map (
|
||
|
|
port_num => 5,
|
||
|
|
Xis => 0,
|
||
|
|
Yis => 1,
|
||
|
|
Zis => 2,
|
||
|
|
header_incl_in_packet_length => true,
|
||
|
|
port_exist => (0,1,2,3,6),
|
||
|
|
vc_num_vec => (4, 4, 4, 4, 4),
|
||
|
|
vc_num_out_vec => (4, 4, 4, 4, 4),
|
||
|
|
vc_depth_array => ((4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4)),
|
||
|
|
vc_depth_out_array => ((4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4)),
|
||
|
|
rout_algo => "DXYU"
|
||
|
|
)
|
||
|
|
port map (
|
||
|
|
clk => clk,
|
||
|
|
rst => rst,
|
||
|
|
data_rx => data_in012,
|
||
|
|
vc_write_rx_vec => vc_write_rx_vec012,
|
||
|
|
incr_rx_vec => incr_rx_vec012,
|
||
|
|
data_tx_pl => data_out012,
|
||
|
|
vc_write_tx_pl_vec => vc_write_tx_pl_vec012,
|
||
|
|
incr_tx_pl_vec => incr_tx_pl_vec012
|
||
|
|
);
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
-- Router port connections to adjacent routers
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
data_in112(0) <= inter_data_in(1)(1)(2)(0);
|
||
|
|
inter_data_out(1)(1)(2)(0) <= data_out112(0);
|
||
|
|
incr_rx_vec112(4-1 downto 0) <= inter_incr_in(1)(1)(2)(0)(4-1 downto 0);
|
||
|
|
inter_incr_out(1)(1)(2)(0)(4-1 downto 0) <= incr_tx_pl_vec112(4-1 downto 0);
|
||
|
|
vc_write_rx_vec112(4-1 downto 0) <= inter_vc_write_in(1)(1)(2)(0)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(1)(1)(2)(0)(4-1 downto 0) <= vc_write_tx_pl_vec112(4-1 downto 0);
|
||
|
|
data_in112(1) <= inter_data_in(1)(1)(2)(1);
|
||
|
|
inter_data_out(1)(1)(2)(1) <= data_out112(1);
|
||
|
|
incr_rx_vec112(8-1 downto 4) <= inter_incr_in(1)(1)(2)(1)(4-1 downto 0);
|
||
|
|
inter_incr_out(1)(1)(2)(1)(4-1 downto 0) <= incr_tx_pl_vec112(8-1 downto 4);
|
||
|
|
vc_write_rx_vec112(8-1 downto 4) <= inter_vc_write_in(1)(1)(2)(1)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(1)(1)(2)(1)(4-1 downto 0) <= vc_write_tx_pl_vec112(8-1 downto 4);
|
||
|
|
|
||
|
|
inter_data_in(1)(1)(2)(1) <= inter_data_out(1)(1+1)(2)(3);
|
||
|
|
|
||
|
|
inter_incr_in(1)(1)(2)(1) <= inter_incr_out(1)(1+1)(2)(3);
|
||
|
|
|
||
|
|
inter_vc_write_in(1)(1)(2)(1) <= inter_vc_write_out(1)(1+1)(2)(3);
|
||
|
|
data_in112(2) <= inter_data_in(1)(1)(2)(2);
|
||
|
|
inter_data_out(1)(1)(2)(2) <= data_out112(2);
|
||
|
|
incr_rx_vec112(12-1 downto 8) <= inter_incr_in(1)(1)(2)(2)(4-1 downto 0);
|
||
|
|
inter_incr_out(1)(1)(2)(2)(4-1 downto 0) <= incr_tx_pl_vec112(12-1 downto 8);
|
||
|
|
vc_write_rx_vec112(12-1 downto 8) <= inter_vc_write_in(1)(1)(2)(2)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(1)(1)(2)(2)(4-1 downto 0) <= vc_write_tx_pl_vec112(12-1 downto 8);
|
||
|
|
|
||
|
|
inter_data_in(1)(1)(2)(2) <= inter_data_out(1+1)(1)(2)(4);
|
||
|
|
|
||
|
|
inter_incr_in(1)(1)(2)(2) <= inter_incr_out(1+1)(1)(2)(4);
|
||
|
|
|
||
|
|
inter_vc_write_in(1)(1)(2)(2) <= inter_vc_write_out(1+1)(1)(2)(4);
|
||
|
|
data_in112(3) <= inter_data_in(1)(1)(2)(3);
|
||
|
|
inter_data_out(1)(1)(2)(3) <= data_out112(3);
|
||
|
|
incr_rx_vec112(16-1 downto 12) <= inter_incr_in(1)(1)(2)(3)(4-1 downto 0);
|
||
|
|
inter_incr_out(1)(1)(2)(3)(4-1 downto 0) <= incr_tx_pl_vec112(16-1 downto 12);
|
||
|
|
vc_write_rx_vec112(16-1 downto 12) <= inter_vc_write_in(1)(1)(2)(3)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(1)(1)(2)(3)(4-1 downto 0) <= vc_write_tx_pl_vec112(16-1 downto 12);
|
||
|
|
|
||
|
|
inter_data_in(1)(1)(2)(3) <= inter_data_out(1)(1-1)(2)(1);
|
||
|
|
|
||
|
|
inter_incr_in(1)(1)(2)(3) <= inter_incr_out(1)(1-1)(2)(1);
|
||
|
|
|
||
|
|
inter_vc_write_in(1)(1)(2)(3) <= inter_vc_write_out(1)(1-1)(2)(1);
|
||
|
|
data_in112(4) <= inter_data_in(1)(1)(2)(4);
|
||
|
|
inter_data_out(1)(1)(2)(4) <= data_out112(4);
|
||
|
|
incr_rx_vec112(20-1 downto 16) <= inter_incr_in(1)(1)(2)(4)(4-1 downto 0);
|
||
|
|
inter_incr_out(1)(1)(2)(4)(4-1 downto 0) <= incr_tx_pl_vec112(20-1 downto 16);
|
||
|
|
vc_write_rx_vec112(20-1 downto 16) <= inter_vc_write_in(1)(1)(2)(4)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(1)(1)(2)(4)(4-1 downto 0) <= vc_write_tx_pl_vec112(20-1 downto 16);
|
||
|
|
|
||
|
|
inter_data_in(1)(1)(2)(4) <= inter_data_out(1-1)(1)(2)(2);
|
||
|
|
|
||
|
|
inter_incr_in(1)(1)(2)(4) <= inter_incr_out(1-1)(1)(2)(2);
|
||
|
|
|
||
|
|
inter_vc_write_in(1)(1)(2)(4) <= inter_vc_write_out(1-1)(1)(2)(2);
|
||
|
|
data_in112(5) <= inter_data_in(1)(1)(2)(6);
|
||
|
|
inter_data_out(1)(1)(2)(6) <= data_out112(5);
|
||
|
|
incr_rx_vec112(24-1 downto 20) <= inter_incr_in(1)(1)(2)(6)(4-1 downto 0);
|
||
|
|
inter_incr_out(1)(1)(2)(6)(4-1 downto 0) <= incr_tx_pl_vec112(24-1 downto 20);
|
||
|
|
vc_write_rx_vec112(24-1 downto 20) <= inter_vc_write_in(1)(1)(2)(6)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(1)(1)(2)(6)(4-1 downto 0) <= vc_write_tx_pl_vec112(24-1 downto 20);
|
||
|
|
|
||
|
|
inter_data_in(1)(1)(2)(6) <= inter_data_out(1)(1)(2-1)(5);
|
||
|
|
|
||
|
|
inter_incr_in(1)(1)(2)(6) <= inter_incr_out(1)(1)(2-1)(5);
|
||
|
|
|
||
|
|
inter_vc_write_in(1)(1)(2)(6) <= inter_vc_write_out(1)(1)(2-1)(5);
|
||
|
|
|
||
|
|
inter_data_in(1)(1)(2)(0) <= local_rx(37);
|
||
|
|
local_tx(37) <= inter_data_out(1)(1)(2)(0);
|
||
|
|
|
||
|
|
inter_incr_in(1)(1)(2)(0)(4-1 downto 0) <= local_incr_rx_vec(152-1 downto 148);
|
||
|
|
local_incr_tx_vec(152-1 downto 148) <= inter_incr_out(1)(1)(2)(0)(4-1 downto 0);
|
||
|
|
|
||
|
|
inter_vc_write_in(1)(1)(2)(0)(4-1 downto 0) <= local_vc_write_rx(152-1 downto 148);
|
||
|
|
local_vc_write_tx(152-1 downto 148) <= inter_vc_write_out(1)(1)(2)(0)(4-1 downto 0);
|
||
|
|
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
-- Router at x= 1 y=1 z=2
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
router_112: entity work.router_pl
|
||
|
|
generic map (
|
||
|
|
port_num => 6,
|
||
|
|
Xis => 1,
|
||
|
|
Yis => 1,
|
||
|
|
Zis => 2,
|
||
|
|
header_incl_in_packet_length => true,
|
||
|
|
port_exist => (0,1,2,3,4,6),
|
||
|
|
vc_num_vec => (4, 4, 4, 4, 4, 4),
|
||
|
|
vc_num_out_vec => (4, 4, 4, 4, 4, 4),
|
||
|
|
vc_depth_array => ((4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4)),
|
||
|
|
vc_depth_out_array => ((4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4)),
|
||
|
|
rout_algo => "DXYU"
|
||
|
|
)
|
||
|
|
port map (
|
||
|
|
clk => clk,
|
||
|
|
rst => rst,
|
||
|
|
data_rx => data_in112,
|
||
|
|
vc_write_rx_vec => vc_write_rx_vec112,
|
||
|
|
incr_rx_vec => incr_rx_vec112,
|
||
|
|
data_tx_pl => data_out112,
|
||
|
|
vc_write_tx_pl_vec => vc_write_tx_pl_vec112,
|
||
|
|
incr_tx_pl_vec => incr_tx_pl_vec112
|
||
|
|
);
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
-- Router port connections to adjacent routers
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
data_in212(0) <= inter_data_in(2)(1)(2)(0);
|
||
|
|
inter_data_out(2)(1)(2)(0) <= data_out212(0);
|
||
|
|
incr_rx_vec212(4-1 downto 0) <= inter_incr_in(2)(1)(2)(0)(4-1 downto 0);
|
||
|
|
inter_incr_out(2)(1)(2)(0)(4-1 downto 0) <= incr_tx_pl_vec212(4-1 downto 0);
|
||
|
|
vc_write_rx_vec212(4-1 downto 0) <= inter_vc_write_in(2)(1)(2)(0)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(2)(1)(2)(0)(4-1 downto 0) <= vc_write_tx_pl_vec212(4-1 downto 0);
|
||
|
|
data_in212(1) <= inter_data_in(2)(1)(2)(1);
|
||
|
|
inter_data_out(2)(1)(2)(1) <= data_out212(1);
|
||
|
|
incr_rx_vec212(8-1 downto 4) <= inter_incr_in(2)(1)(2)(1)(4-1 downto 0);
|
||
|
|
inter_incr_out(2)(1)(2)(1)(4-1 downto 0) <= incr_tx_pl_vec212(8-1 downto 4);
|
||
|
|
vc_write_rx_vec212(8-1 downto 4) <= inter_vc_write_in(2)(1)(2)(1)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(2)(1)(2)(1)(4-1 downto 0) <= vc_write_tx_pl_vec212(8-1 downto 4);
|
||
|
|
|
||
|
|
inter_data_in(2)(1)(2)(1) <= inter_data_out(2)(1+1)(2)(3);
|
||
|
|
|
||
|
|
inter_incr_in(2)(1)(2)(1) <= inter_incr_out(2)(1+1)(2)(3);
|
||
|
|
|
||
|
|
inter_vc_write_in(2)(1)(2)(1) <= inter_vc_write_out(2)(1+1)(2)(3);
|
||
|
|
data_in212(2) <= inter_data_in(2)(1)(2)(2);
|
||
|
|
inter_data_out(2)(1)(2)(2) <= data_out212(2);
|
||
|
|
incr_rx_vec212(12-1 downto 8) <= inter_incr_in(2)(1)(2)(2)(4-1 downto 0);
|
||
|
|
inter_incr_out(2)(1)(2)(2)(4-1 downto 0) <= incr_tx_pl_vec212(12-1 downto 8);
|
||
|
|
vc_write_rx_vec212(12-1 downto 8) <= inter_vc_write_in(2)(1)(2)(2)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(2)(1)(2)(2)(4-1 downto 0) <= vc_write_tx_pl_vec212(12-1 downto 8);
|
||
|
|
|
||
|
|
inter_data_in(2)(1)(2)(2) <= inter_data_out(2+1)(1)(2)(4);
|
||
|
|
|
||
|
|
inter_incr_in(2)(1)(2)(2) <= inter_incr_out(2+1)(1)(2)(4);
|
||
|
|
|
||
|
|
inter_vc_write_in(2)(1)(2)(2) <= inter_vc_write_out(2+1)(1)(2)(4);
|
||
|
|
data_in212(3) <= inter_data_in(2)(1)(2)(3);
|
||
|
|
inter_data_out(2)(1)(2)(3) <= data_out212(3);
|
||
|
|
incr_rx_vec212(16-1 downto 12) <= inter_incr_in(2)(1)(2)(3)(4-1 downto 0);
|
||
|
|
inter_incr_out(2)(1)(2)(3)(4-1 downto 0) <= incr_tx_pl_vec212(16-1 downto 12);
|
||
|
|
vc_write_rx_vec212(16-1 downto 12) <= inter_vc_write_in(2)(1)(2)(3)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(2)(1)(2)(3)(4-1 downto 0) <= vc_write_tx_pl_vec212(16-1 downto 12);
|
||
|
|
|
||
|
|
inter_data_in(2)(1)(2)(3) <= inter_data_out(2)(1-1)(2)(1);
|
||
|
|
|
||
|
|
inter_incr_in(2)(1)(2)(3) <= inter_incr_out(2)(1-1)(2)(1);
|
||
|
|
|
||
|
|
inter_vc_write_in(2)(1)(2)(3) <= inter_vc_write_out(2)(1-1)(2)(1);
|
||
|
|
data_in212(4) <= inter_data_in(2)(1)(2)(4);
|
||
|
|
inter_data_out(2)(1)(2)(4) <= data_out212(4);
|
||
|
|
incr_rx_vec212(20-1 downto 16) <= inter_incr_in(2)(1)(2)(4)(4-1 downto 0);
|
||
|
|
inter_incr_out(2)(1)(2)(4)(4-1 downto 0) <= incr_tx_pl_vec212(20-1 downto 16);
|
||
|
|
vc_write_rx_vec212(20-1 downto 16) <= inter_vc_write_in(2)(1)(2)(4)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(2)(1)(2)(4)(4-1 downto 0) <= vc_write_tx_pl_vec212(20-1 downto 16);
|
||
|
|
|
||
|
|
inter_data_in(2)(1)(2)(4) <= inter_data_out(2-1)(1)(2)(2);
|
||
|
|
|
||
|
|
inter_incr_in(2)(1)(2)(4) <= inter_incr_out(2-1)(1)(2)(2);
|
||
|
|
|
||
|
|
inter_vc_write_in(2)(1)(2)(4) <= inter_vc_write_out(2-1)(1)(2)(2);
|
||
|
|
data_in212(5) <= inter_data_in(2)(1)(2)(6);
|
||
|
|
inter_data_out(2)(1)(2)(6) <= data_out212(5);
|
||
|
|
incr_rx_vec212(24-1 downto 20) <= inter_incr_in(2)(1)(2)(6)(4-1 downto 0);
|
||
|
|
inter_incr_out(2)(1)(2)(6)(4-1 downto 0) <= incr_tx_pl_vec212(24-1 downto 20);
|
||
|
|
vc_write_rx_vec212(24-1 downto 20) <= inter_vc_write_in(2)(1)(2)(6)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(2)(1)(2)(6)(4-1 downto 0) <= vc_write_tx_pl_vec212(24-1 downto 20);
|
||
|
|
|
||
|
|
inter_data_in(2)(1)(2)(6) <= inter_data_out(2)(1)(2-1)(5);
|
||
|
|
|
||
|
|
inter_incr_in(2)(1)(2)(6) <= inter_incr_out(2)(1)(2-1)(5);
|
||
|
|
|
||
|
|
inter_vc_write_in(2)(1)(2)(6) <= inter_vc_write_out(2)(1)(2-1)(5);
|
||
|
|
|
||
|
|
inter_data_in(2)(1)(2)(0) <= local_rx(38);
|
||
|
|
local_tx(38) <= inter_data_out(2)(1)(2)(0);
|
||
|
|
|
||
|
|
inter_incr_in(2)(1)(2)(0)(4-1 downto 0) <= local_incr_rx_vec(156-1 downto 152);
|
||
|
|
local_incr_tx_vec(156-1 downto 152) <= inter_incr_out(2)(1)(2)(0)(4-1 downto 0);
|
||
|
|
|
||
|
|
inter_vc_write_in(2)(1)(2)(0)(4-1 downto 0) <= local_vc_write_rx(156-1 downto 152);
|
||
|
|
local_vc_write_tx(156-1 downto 152) <= inter_vc_write_out(2)(1)(2)(0)(4-1 downto 0);
|
||
|
|
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
-- Router at x= 2 y=1 z=2
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
router_212: entity work.router_pl
|
||
|
|
generic map (
|
||
|
|
port_num => 6,
|
||
|
|
Xis => 2,
|
||
|
|
Yis => 1,
|
||
|
|
Zis => 2,
|
||
|
|
header_incl_in_packet_length => true,
|
||
|
|
port_exist => (0,1,2,3,4,6),
|
||
|
|
vc_num_vec => (4, 4, 4, 4, 4, 4),
|
||
|
|
vc_num_out_vec => (4, 4, 4, 4, 4, 4),
|
||
|
|
vc_depth_array => ((4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4)),
|
||
|
|
vc_depth_out_array => ((4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4)),
|
||
|
|
rout_algo => "DXYU"
|
||
|
|
)
|
||
|
|
port map (
|
||
|
|
clk => clk,
|
||
|
|
rst => rst,
|
||
|
|
data_rx => data_in212,
|
||
|
|
vc_write_rx_vec => vc_write_rx_vec212,
|
||
|
|
incr_rx_vec => incr_rx_vec212,
|
||
|
|
data_tx_pl => data_out212,
|
||
|
|
vc_write_tx_pl_vec => vc_write_tx_pl_vec212,
|
||
|
|
incr_tx_pl_vec => incr_tx_pl_vec212
|
||
|
|
);
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
-- Router port connections to adjacent routers
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
data_in312(0) <= inter_data_in(3)(1)(2)(0);
|
||
|
|
inter_data_out(3)(1)(2)(0) <= data_out312(0);
|
||
|
|
incr_rx_vec312(4-1 downto 0) <= inter_incr_in(3)(1)(2)(0)(4-1 downto 0);
|
||
|
|
inter_incr_out(3)(1)(2)(0)(4-1 downto 0) <= incr_tx_pl_vec312(4-1 downto 0);
|
||
|
|
vc_write_rx_vec312(4-1 downto 0) <= inter_vc_write_in(3)(1)(2)(0)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(3)(1)(2)(0)(4-1 downto 0) <= vc_write_tx_pl_vec312(4-1 downto 0);
|
||
|
|
data_in312(1) <= inter_data_in(3)(1)(2)(1);
|
||
|
|
inter_data_out(3)(1)(2)(1) <= data_out312(1);
|
||
|
|
incr_rx_vec312(8-1 downto 4) <= inter_incr_in(3)(1)(2)(1)(4-1 downto 0);
|
||
|
|
inter_incr_out(3)(1)(2)(1)(4-1 downto 0) <= incr_tx_pl_vec312(8-1 downto 4);
|
||
|
|
vc_write_rx_vec312(8-1 downto 4) <= inter_vc_write_in(3)(1)(2)(1)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(3)(1)(2)(1)(4-1 downto 0) <= vc_write_tx_pl_vec312(8-1 downto 4);
|
||
|
|
|
||
|
|
inter_data_in(3)(1)(2)(1) <= inter_data_out(3)(1+1)(2)(3);
|
||
|
|
|
||
|
|
inter_incr_in(3)(1)(2)(1) <= inter_incr_out(3)(1+1)(2)(3);
|
||
|
|
|
||
|
|
inter_vc_write_in(3)(1)(2)(1) <= inter_vc_write_out(3)(1+1)(2)(3);
|
||
|
|
data_in312(2) <= inter_data_in(3)(1)(2)(3);
|
||
|
|
inter_data_out(3)(1)(2)(3) <= data_out312(2);
|
||
|
|
incr_rx_vec312(12-1 downto 8) <= inter_incr_in(3)(1)(2)(3)(4-1 downto 0);
|
||
|
|
inter_incr_out(3)(1)(2)(3)(4-1 downto 0) <= incr_tx_pl_vec312(12-1 downto 8);
|
||
|
|
vc_write_rx_vec312(12-1 downto 8) <= inter_vc_write_in(3)(1)(2)(3)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(3)(1)(2)(3)(4-1 downto 0) <= vc_write_tx_pl_vec312(12-1 downto 8);
|
||
|
|
|
||
|
|
inter_data_in(3)(1)(2)(3) <= inter_data_out(3)(1-1)(2)(1);
|
||
|
|
|
||
|
|
inter_incr_in(3)(1)(2)(3) <= inter_incr_out(3)(1-1)(2)(1);
|
||
|
|
|
||
|
|
inter_vc_write_in(3)(1)(2)(3) <= inter_vc_write_out(3)(1-1)(2)(1);
|
||
|
|
data_in312(3) <= inter_data_in(3)(1)(2)(4);
|
||
|
|
inter_data_out(3)(1)(2)(4) <= data_out312(3);
|
||
|
|
incr_rx_vec312(16-1 downto 12) <= inter_incr_in(3)(1)(2)(4)(4-1 downto 0);
|
||
|
|
inter_incr_out(3)(1)(2)(4)(4-1 downto 0) <= incr_tx_pl_vec312(16-1 downto 12);
|
||
|
|
vc_write_rx_vec312(16-1 downto 12) <= inter_vc_write_in(3)(1)(2)(4)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(3)(1)(2)(4)(4-1 downto 0) <= vc_write_tx_pl_vec312(16-1 downto 12);
|
||
|
|
|
||
|
|
inter_data_in(3)(1)(2)(4) <= inter_data_out(3-1)(1)(2)(2);
|
||
|
|
|
||
|
|
inter_incr_in(3)(1)(2)(4) <= inter_incr_out(3-1)(1)(2)(2);
|
||
|
|
|
||
|
|
inter_vc_write_in(3)(1)(2)(4) <= inter_vc_write_out(3-1)(1)(2)(2);
|
||
|
|
data_in312(4) <= inter_data_in(3)(1)(2)(6);
|
||
|
|
inter_data_out(3)(1)(2)(6) <= data_out312(4);
|
||
|
|
incr_rx_vec312(20-1 downto 16) <= inter_incr_in(3)(1)(2)(6)(4-1 downto 0);
|
||
|
|
inter_incr_out(3)(1)(2)(6)(4-1 downto 0) <= incr_tx_pl_vec312(20-1 downto 16);
|
||
|
|
vc_write_rx_vec312(20-1 downto 16) <= inter_vc_write_in(3)(1)(2)(6)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(3)(1)(2)(6)(4-1 downto 0) <= vc_write_tx_pl_vec312(20-1 downto 16);
|
||
|
|
|
||
|
|
inter_data_in(3)(1)(2)(6) <= inter_data_out(3)(1)(2-1)(5);
|
||
|
|
|
||
|
|
inter_incr_in(3)(1)(2)(6) <= inter_incr_out(3)(1)(2-1)(5);
|
||
|
|
|
||
|
|
inter_vc_write_in(3)(1)(2)(6) <= inter_vc_write_out(3)(1)(2-1)(5);
|
||
|
|
|
||
|
|
inter_data_in(3)(1)(2)(0) <= local_rx(39);
|
||
|
|
local_tx(39) <= inter_data_out(3)(1)(2)(0);
|
||
|
|
|
||
|
|
inter_incr_in(3)(1)(2)(0)(4-1 downto 0) <= local_incr_rx_vec(160-1 downto 156);
|
||
|
|
local_incr_tx_vec(160-1 downto 156) <= inter_incr_out(3)(1)(2)(0)(4-1 downto 0);
|
||
|
|
|
||
|
|
inter_vc_write_in(3)(1)(2)(0)(4-1 downto 0) <= local_vc_write_rx(160-1 downto 156);
|
||
|
|
local_vc_write_tx(160-1 downto 156) <= inter_vc_write_out(3)(1)(2)(0)(4-1 downto 0);
|
||
|
|
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
-- Router at x= 3 y=1 z=2
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
router_312: entity work.router_pl
|
||
|
|
generic map (
|
||
|
|
port_num => 5,
|
||
|
|
Xis => 3,
|
||
|
|
Yis => 1,
|
||
|
|
Zis => 2,
|
||
|
|
header_incl_in_packet_length => true,
|
||
|
|
port_exist => (0,1,3,4,6),
|
||
|
|
vc_num_vec => (4, 4, 4, 4, 4),
|
||
|
|
vc_num_out_vec => (4, 4, 4, 4, 4),
|
||
|
|
vc_depth_array => ((4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4)),
|
||
|
|
vc_depth_out_array => ((4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4)),
|
||
|
|
rout_algo => "DXYU"
|
||
|
|
)
|
||
|
|
port map (
|
||
|
|
clk => clk,
|
||
|
|
rst => rst,
|
||
|
|
data_rx => data_in312,
|
||
|
|
vc_write_rx_vec => vc_write_rx_vec312,
|
||
|
|
incr_rx_vec => incr_rx_vec312,
|
||
|
|
data_tx_pl => data_out312,
|
||
|
|
vc_write_tx_pl_vec => vc_write_tx_pl_vec312,
|
||
|
|
incr_tx_pl_vec => incr_tx_pl_vec312
|
||
|
|
);
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
-- Router port connections to adjacent routers
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
data_in022(0) <= inter_data_in(0)(2)(2)(0);
|
||
|
|
inter_data_out(0)(2)(2)(0) <= data_out022(0);
|
||
|
|
incr_rx_vec022(4-1 downto 0) <= inter_incr_in(0)(2)(2)(0)(4-1 downto 0);
|
||
|
|
inter_incr_out(0)(2)(2)(0)(4-1 downto 0) <= incr_tx_pl_vec022(4-1 downto 0);
|
||
|
|
vc_write_rx_vec022(4-1 downto 0) <= inter_vc_write_in(0)(2)(2)(0)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(0)(2)(2)(0)(4-1 downto 0) <= vc_write_tx_pl_vec022(4-1 downto 0);
|
||
|
|
data_in022(1) <= inter_data_in(0)(2)(2)(1);
|
||
|
|
inter_data_out(0)(2)(2)(1) <= data_out022(1);
|
||
|
|
incr_rx_vec022(8-1 downto 4) <= inter_incr_in(0)(2)(2)(1)(4-1 downto 0);
|
||
|
|
inter_incr_out(0)(2)(2)(1)(4-1 downto 0) <= incr_tx_pl_vec022(8-1 downto 4);
|
||
|
|
vc_write_rx_vec022(8-1 downto 4) <= inter_vc_write_in(0)(2)(2)(1)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(0)(2)(2)(1)(4-1 downto 0) <= vc_write_tx_pl_vec022(8-1 downto 4);
|
||
|
|
|
||
|
|
inter_data_in(0)(2)(2)(1) <= inter_data_out(0)(2+1)(2)(3);
|
||
|
|
|
||
|
|
inter_incr_in(0)(2)(2)(1) <= inter_incr_out(0)(2+1)(2)(3);
|
||
|
|
|
||
|
|
inter_vc_write_in(0)(2)(2)(1) <= inter_vc_write_out(0)(2+1)(2)(3);
|
||
|
|
data_in022(2) <= inter_data_in(0)(2)(2)(2);
|
||
|
|
inter_data_out(0)(2)(2)(2) <= data_out022(2);
|
||
|
|
incr_rx_vec022(12-1 downto 8) <= inter_incr_in(0)(2)(2)(2)(4-1 downto 0);
|
||
|
|
inter_incr_out(0)(2)(2)(2)(4-1 downto 0) <= incr_tx_pl_vec022(12-1 downto 8);
|
||
|
|
vc_write_rx_vec022(12-1 downto 8) <= inter_vc_write_in(0)(2)(2)(2)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(0)(2)(2)(2)(4-1 downto 0) <= vc_write_tx_pl_vec022(12-1 downto 8);
|
||
|
|
|
||
|
|
inter_data_in(0)(2)(2)(2) <= inter_data_out(0+1)(2)(2)(4);
|
||
|
|
|
||
|
|
inter_incr_in(0)(2)(2)(2) <= inter_incr_out(0+1)(2)(2)(4);
|
||
|
|
|
||
|
|
inter_vc_write_in(0)(2)(2)(2) <= inter_vc_write_out(0+1)(2)(2)(4);
|
||
|
|
data_in022(3) <= inter_data_in(0)(2)(2)(3);
|
||
|
|
inter_data_out(0)(2)(2)(3) <= data_out022(3);
|
||
|
|
incr_rx_vec022(16-1 downto 12) <= inter_incr_in(0)(2)(2)(3)(4-1 downto 0);
|
||
|
|
inter_incr_out(0)(2)(2)(3)(4-1 downto 0) <= incr_tx_pl_vec022(16-1 downto 12);
|
||
|
|
vc_write_rx_vec022(16-1 downto 12) <= inter_vc_write_in(0)(2)(2)(3)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(0)(2)(2)(3)(4-1 downto 0) <= vc_write_tx_pl_vec022(16-1 downto 12);
|
||
|
|
|
||
|
|
inter_data_in(0)(2)(2)(3) <= inter_data_out(0)(2-1)(2)(1);
|
||
|
|
|
||
|
|
inter_incr_in(0)(2)(2)(3) <= inter_incr_out(0)(2-1)(2)(1);
|
||
|
|
|
||
|
|
inter_vc_write_in(0)(2)(2)(3) <= inter_vc_write_out(0)(2-1)(2)(1);
|
||
|
|
data_in022(4) <= inter_data_in(0)(2)(2)(6);
|
||
|
|
inter_data_out(0)(2)(2)(6) <= data_out022(4);
|
||
|
|
incr_rx_vec022(20-1 downto 16) <= inter_incr_in(0)(2)(2)(6)(4-1 downto 0);
|
||
|
|
inter_incr_out(0)(2)(2)(6)(4-1 downto 0) <= incr_tx_pl_vec022(20-1 downto 16);
|
||
|
|
vc_write_rx_vec022(20-1 downto 16) <= inter_vc_write_in(0)(2)(2)(6)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(0)(2)(2)(6)(4-1 downto 0) <= vc_write_tx_pl_vec022(20-1 downto 16);
|
||
|
|
|
||
|
|
inter_data_in(0)(2)(2)(6) <= inter_data_out(0)(2)(2-1)(5);
|
||
|
|
|
||
|
|
inter_incr_in(0)(2)(2)(6) <= inter_incr_out(0)(2)(2-1)(5);
|
||
|
|
|
||
|
|
inter_vc_write_in(0)(2)(2)(6) <= inter_vc_write_out(0)(2)(2-1)(5);
|
||
|
|
|
||
|
|
inter_data_in(0)(2)(2)(0) <= local_rx(40);
|
||
|
|
local_tx(40) <= inter_data_out(0)(2)(2)(0);
|
||
|
|
|
||
|
|
inter_incr_in(0)(2)(2)(0)(4-1 downto 0) <= local_incr_rx_vec(164-1 downto 160);
|
||
|
|
local_incr_tx_vec(164-1 downto 160) <= inter_incr_out(0)(2)(2)(0)(4-1 downto 0);
|
||
|
|
|
||
|
|
inter_vc_write_in(0)(2)(2)(0)(4-1 downto 0) <= local_vc_write_rx(164-1 downto 160);
|
||
|
|
local_vc_write_tx(164-1 downto 160) <= inter_vc_write_out(0)(2)(2)(0)(4-1 downto 0);
|
||
|
|
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
-- Router at x= 0 y=2 z=2
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
router_022: entity work.router_pl
|
||
|
|
generic map (
|
||
|
|
port_num => 5,
|
||
|
|
Xis => 0,
|
||
|
|
Yis => 2,
|
||
|
|
Zis => 2,
|
||
|
|
header_incl_in_packet_length => true,
|
||
|
|
port_exist => (0,1,2,3,6),
|
||
|
|
vc_num_vec => (4, 4, 4, 4, 4),
|
||
|
|
vc_num_out_vec => (4, 4, 4, 4, 4),
|
||
|
|
vc_depth_array => ((4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4)),
|
||
|
|
vc_depth_out_array => ((4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4)),
|
||
|
|
rout_algo => "DXYU"
|
||
|
|
)
|
||
|
|
port map (
|
||
|
|
clk => clk,
|
||
|
|
rst => rst,
|
||
|
|
data_rx => data_in022,
|
||
|
|
vc_write_rx_vec => vc_write_rx_vec022,
|
||
|
|
incr_rx_vec => incr_rx_vec022,
|
||
|
|
data_tx_pl => data_out022,
|
||
|
|
vc_write_tx_pl_vec => vc_write_tx_pl_vec022,
|
||
|
|
incr_tx_pl_vec => incr_tx_pl_vec022
|
||
|
|
);
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
-- Router port connections to adjacent routers
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
data_in122(0) <= inter_data_in(1)(2)(2)(0);
|
||
|
|
inter_data_out(1)(2)(2)(0) <= data_out122(0);
|
||
|
|
incr_rx_vec122(4-1 downto 0) <= inter_incr_in(1)(2)(2)(0)(4-1 downto 0);
|
||
|
|
inter_incr_out(1)(2)(2)(0)(4-1 downto 0) <= incr_tx_pl_vec122(4-1 downto 0);
|
||
|
|
vc_write_rx_vec122(4-1 downto 0) <= inter_vc_write_in(1)(2)(2)(0)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(1)(2)(2)(0)(4-1 downto 0) <= vc_write_tx_pl_vec122(4-1 downto 0);
|
||
|
|
data_in122(1) <= inter_data_in(1)(2)(2)(1);
|
||
|
|
inter_data_out(1)(2)(2)(1) <= data_out122(1);
|
||
|
|
incr_rx_vec122(8-1 downto 4) <= inter_incr_in(1)(2)(2)(1)(4-1 downto 0);
|
||
|
|
inter_incr_out(1)(2)(2)(1)(4-1 downto 0) <= incr_tx_pl_vec122(8-1 downto 4);
|
||
|
|
vc_write_rx_vec122(8-1 downto 4) <= inter_vc_write_in(1)(2)(2)(1)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(1)(2)(2)(1)(4-1 downto 0) <= vc_write_tx_pl_vec122(8-1 downto 4);
|
||
|
|
|
||
|
|
inter_data_in(1)(2)(2)(1) <= inter_data_out(1)(2+1)(2)(3);
|
||
|
|
|
||
|
|
inter_incr_in(1)(2)(2)(1) <= inter_incr_out(1)(2+1)(2)(3);
|
||
|
|
|
||
|
|
inter_vc_write_in(1)(2)(2)(1) <= inter_vc_write_out(1)(2+1)(2)(3);
|
||
|
|
data_in122(2) <= inter_data_in(1)(2)(2)(2);
|
||
|
|
inter_data_out(1)(2)(2)(2) <= data_out122(2);
|
||
|
|
incr_rx_vec122(12-1 downto 8) <= inter_incr_in(1)(2)(2)(2)(4-1 downto 0);
|
||
|
|
inter_incr_out(1)(2)(2)(2)(4-1 downto 0) <= incr_tx_pl_vec122(12-1 downto 8);
|
||
|
|
vc_write_rx_vec122(12-1 downto 8) <= inter_vc_write_in(1)(2)(2)(2)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(1)(2)(2)(2)(4-1 downto 0) <= vc_write_tx_pl_vec122(12-1 downto 8);
|
||
|
|
|
||
|
|
inter_data_in(1)(2)(2)(2) <= inter_data_out(1+1)(2)(2)(4);
|
||
|
|
|
||
|
|
inter_incr_in(1)(2)(2)(2) <= inter_incr_out(1+1)(2)(2)(4);
|
||
|
|
|
||
|
|
inter_vc_write_in(1)(2)(2)(2) <= inter_vc_write_out(1+1)(2)(2)(4);
|
||
|
|
data_in122(3) <= inter_data_in(1)(2)(2)(3);
|
||
|
|
inter_data_out(1)(2)(2)(3) <= data_out122(3);
|
||
|
|
incr_rx_vec122(16-1 downto 12) <= inter_incr_in(1)(2)(2)(3)(4-1 downto 0);
|
||
|
|
inter_incr_out(1)(2)(2)(3)(4-1 downto 0) <= incr_tx_pl_vec122(16-1 downto 12);
|
||
|
|
vc_write_rx_vec122(16-1 downto 12) <= inter_vc_write_in(1)(2)(2)(3)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(1)(2)(2)(3)(4-1 downto 0) <= vc_write_tx_pl_vec122(16-1 downto 12);
|
||
|
|
|
||
|
|
inter_data_in(1)(2)(2)(3) <= inter_data_out(1)(2-1)(2)(1);
|
||
|
|
|
||
|
|
inter_incr_in(1)(2)(2)(3) <= inter_incr_out(1)(2-1)(2)(1);
|
||
|
|
|
||
|
|
inter_vc_write_in(1)(2)(2)(3) <= inter_vc_write_out(1)(2-1)(2)(1);
|
||
|
|
data_in122(4) <= inter_data_in(1)(2)(2)(4);
|
||
|
|
inter_data_out(1)(2)(2)(4) <= data_out122(4);
|
||
|
|
incr_rx_vec122(20-1 downto 16) <= inter_incr_in(1)(2)(2)(4)(4-1 downto 0);
|
||
|
|
inter_incr_out(1)(2)(2)(4)(4-1 downto 0) <= incr_tx_pl_vec122(20-1 downto 16);
|
||
|
|
vc_write_rx_vec122(20-1 downto 16) <= inter_vc_write_in(1)(2)(2)(4)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(1)(2)(2)(4)(4-1 downto 0) <= vc_write_tx_pl_vec122(20-1 downto 16);
|
||
|
|
|
||
|
|
inter_data_in(1)(2)(2)(4) <= inter_data_out(1-1)(2)(2)(2);
|
||
|
|
|
||
|
|
inter_incr_in(1)(2)(2)(4) <= inter_incr_out(1-1)(2)(2)(2);
|
||
|
|
|
||
|
|
inter_vc_write_in(1)(2)(2)(4) <= inter_vc_write_out(1-1)(2)(2)(2);
|
||
|
|
data_in122(5) <= inter_data_in(1)(2)(2)(6);
|
||
|
|
inter_data_out(1)(2)(2)(6) <= data_out122(5);
|
||
|
|
incr_rx_vec122(24-1 downto 20) <= inter_incr_in(1)(2)(2)(6)(4-1 downto 0);
|
||
|
|
inter_incr_out(1)(2)(2)(6)(4-1 downto 0) <= incr_tx_pl_vec122(24-1 downto 20);
|
||
|
|
vc_write_rx_vec122(24-1 downto 20) <= inter_vc_write_in(1)(2)(2)(6)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(1)(2)(2)(6)(4-1 downto 0) <= vc_write_tx_pl_vec122(24-1 downto 20);
|
||
|
|
|
||
|
|
inter_data_in(1)(2)(2)(6) <= inter_data_out(1)(2)(2-1)(5);
|
||
|
|
|
||
|
|
inter_incr_in(1)(2)(2)(6) <= inter_incr_out(1)(2)(2-1)(5);
|
||
|
|
|
||
|
|
inter_vc_write_in(1)(2)(2)(6) <= inter_vc_write_out(1)(2)(2-1)(5);
|
||
|
|
|
||
|
|
inter_data_in(1)(2)(2)(0) <= local_rx(41);
|
||
|
|
local_tx(41) <= inter_data_out(1)(2)(2)(0);
|
||
|
|
|
||
|
|
inter_incr_in(1)(2)(2)(0)(4-1 downto 0) <= local_incr_rx_vec(168-1 downto 164);
|
||
|
|
local_incr_tx_vec(168-1 downto 164) <= inter_incr_out(1)(2)(2)(0)(4-1 downto 0);
|
||
|
|
|
||
|
|
inter_vc_write_in(1)(2)(2)(0)(4-1 downto 0) <= local_vc_write_rx(168-1 downto 164);
|
||
|
|
local_vc_write_tx(168-1 downto 164) <= inter_vc_write_out(1)(2)(2)(0)(4-1 downto 0);
|
||
|
|
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
-- Router at x= 1 y=2 z=2
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
router_122: entity work.router_pl
|
||
|
|
generic map (
|
||
|
|
port_num => 6,
|
||
|
|
Xis => 1,
|
||
|
|
Yis => 2,
|
||
|
|
Zis => 2,
|
||
|
|
header_incl_in_packet_length => true,
|
||
|
|
port_exist => (0,1,2,3,4,6),
|
||
|
|
vc_num_vec => (4, 4, 4, 4, 4, 4),
|
||
|
|
vc_num_out_vec => (4, 4, 4, 4, 4, 4),
|
||
|
|
vc_depth_array => ((4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4)),
|
||
|
|
vc_depth_out_array => ((4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4)),
|
||
|
|
rout_algo => "DXYU"
|
||
|
|
)
|
||
|
|
port map (
|
||
|
|
clk => clk,
|
||
|
|
rst => rst,
|
||
|
|
data_rx => data_in122,
|
||
|
|
vc_write_rx_vec => vc_write_rx_vec122,
|
||
|
|
incr_rx_vec => incr_rx_vec122,
|
||
|
|
data_tx_pl => data_out122,
|
||
|
|
vc_write_tx_pl_vec => vc_write_tx_pl_vec122,
|
||
|
|
incr_tx_pl_vec => incr_tx_pl_vec122
|
||
|
|
);
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
-- Router port connections to adjacent routers
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
data_in222(0) <= inter_data_in(2)(2)(2)(0);
|
||
|
|
inter_data_out(2)(2)(2)(0) <= data_out222(0);
|
||
|
|
incr_rx_vec222(4-1 downto 0) <= inter_incr_in(2)(2)(2)(0)(4-1 downto 0);
|
||
|
|
inter_incr_out(2)(2)(2)(0)(4-1 downto 0) <= incr_tx_pl_vec222(4-1 downto 0);
|
||
|
|
vc_write_rx_vec222(4-1 downto 0) <= inter_vc_write_in(2)(2)(2)(0)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(2)(2)(2)(0)(4-1 downto 0) <= vc_write_tx_pl_vec222(4-1 downto 0);
|
||
|
|
data_in222(1) <= inter_data_in(2)(2)(2)(1);
|
||
|
|
inter_data_out(2)(2)(2)(1) <= data_out222(1);
|
||
|
|
incr_rx_vec222(8-1 downto 4) <= inter_incr_in(2)(2)(2)(1)(4-1 downto 0);
|
||
|
|
inter_incr_out(2)(2)(2)(1)(4-1 downto 0) <= incr_tx_pl_vec222(8-1 downto 4);
|
||
|
|
vc_write_rx_vec222(8-1 downto 4) <= inter_vc_write_in(2)(2)(2)(1)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(2)(2)(2)(1)(4-1 downto 0) <= vc_write_tx_pl_vec222(8-1 downto 4);
|
||
|
|
|
||
|
|
inter_data_in(2)(2)(2)(1) <= inter_data_out(2)(2+1)(2)(3);
|
||
|
|
|
||
|
|
inter_incr_in(2)(2)(2)(1) <= inter_incr_out(2)(2+1)(2)(3);
|
||
|
|
|
||
|
|
inter_vc_write_in(2)(2)(2)(1) <= inter_vc_write_out(2)(2+1)(2)(3);
|
||
|
|
data_in222(2) <= inter_data_in(2)(2)(2)(2);
|
||
|
|
inter_data_out(2)(2)(2)(2) <= data_out222(2);
|
||
|
|
incr_rx_vec222(12-1 downto 8) <= inter_incr_in(2)(2)(2)(2)(4-1 downto 0);
|
||
|
|
inter_incr_out(2)(2)(2)(2)(4-1 downto 0) <= incr_tx_pl_vec222(12-1 downto 8);
|
||
|
|
vc_write_rx_vec222(12-1 downto 8) <= inter_vc_write_in(2)(2)(2)(2)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(2)(2)(2)(2)(4-1 downto 0) <= vc_write_tx_pl_vec222(12-1 downto 8);
|
||
|
|
|
||
|
|
inter_data_in(2)(2)(2)(2) <= inter_data_out(2+1)(2)(2)(4);
|
||
|
|
|
||
|
|
inter_incr_in(2)(2)(2)(2) <= inter_incr_out(2+1)(2)(2)(4);
|
||
|
|
|
||
|
|
inter_vc_write_in(2)(2)(2)(2) <= inter_vc_write_out(2+1)(2)(2)(4);
|
||
|
|
data_in222(3) <= inter_data_in(2)(2)(2)(3);
|
||
|
|
inter_data_out(2)(2)(2)(3) <= data_out222(3);
|
||
|
|
incr_rx_vec222(16-1 downto 12) <= inter_incr_in(2)(2)(2)(3)(4-1 downto 0);
|
||
|
|
inter_incr_out(2)(2)(2)(3)(4-1 downto 0) <= incr_tx_pl_vec222(16-1 downto 12);
|
||
|
|
vc_write_rx_vec222(16-1 downto 12) <= inter_vc_write_in(2)(2)(2)(3)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(2)(2)(2)(3)(4-1 downto 0) <= vc_write_tx_pl_vec222(16-1 downto 12);
|
||
|
|
|
||
|
|
inter_data_in(2)(2)(2)(3) <= inter_data_out(2)(2-1)(2)(1);
|
||
|
|
|
||
|
|
inter_incr_in(2)(2)(2)(3) <= inter_incr_out(2)(2-1)(2)(1);
|
||
|
|
|
||
|
|
inter_vc_write_in(2)(2)(2)(3) <= inter_vc_write_out(2)(2-1)(2)(1);
|
||
|
|
data_in222(4) <= inter_data_in(2)(2)(2)(4);
|
||
|
|
inter_data_out(2)(2)(2)(4) <= data_out222(4);
|
||
|
|
incr_rx_vec222(20-1 downto 16) <= inter_incr_in(2)(2)(2)(4)(4-1 downto 0);
|
||
|
|
inter_incr_out(2)(2)(2)(4)(4-1 downto 0) <= incr_tx_pl_vec222(20-1 downto 16);
|
||
|
|
vc_write_rx_vec222(20-1 downto 16) <= inter_vc_write_in(2)(2)(2)(4)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(2)(2)(2)(4)(4-1 downto 0) <= vc_write_tx_pl_vec222(20-1 downto 16);
|
||
|
|
|
||
|
|
inter_data_in(2)(2)(2)(4) <= inter_data_out(2-1)(2)(2)(2);
|
||
|
|
|
||
|
|
inter_incr_in(2)(2)(2)(4) <= inter_incr_out(2-1)(2)(2)(2);
|
||
|
|
|
||
|
|
inter_vc_write_in(2)(2)(2)(4) <= inter_vc_write_out(2-1)(2)(2)(2);
|
||
|
|
data_in222(5) <= inter_data_in(2)(2)(2)(6);
|
||
|
|
inter_data_out(2)(2)(2)(6) <= data_out222(5);
|
||
|
|
incr_rx_vec222(24-1 downto 20) <= inter_incr_in(2)(2)(2)(6)(4-1 downto 0);
|
||
|
|
inter_incr_out(2)(2)(2)(6)(4-1 downto 0) <= incr_tx_pl_vec222(24-1 downto 20);
|
||
|
|
vc_write_rx_vec222(24-1 downto 20) <= inter_vc_write_in(2)(2)(2)(6)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(2)(2)(2)(6)(4-1 downto 0) <= vc_write_tx_pl_vec222(24-1 downto 20);
|
||
|
|
|
||
|
|
inter_data_in(2)(2)(2)(6) <= inter_data_out(2)(2)(2-1)(5);
|
||
|
|
|
||
|
|
inter_incr_in(2)(2)(2)(6) <= inter_incr_out(2)(2)(2-1)(5);
|
||
|
|
|
||
|
|
inter_vc_write_in(2)(2)(2)(6) <= inter_vc_write_out(2)(2)(2-1)(5);
|
||
|
|
|
||
|
|
inter_data_in(2)(2)(2)(0) <= local_rx(42);
|
||
|
|
local_tx(42) <= inter_data_out(2)(2)(2)(0);
|
||
|
|
|
||
|
|
inter_incr_in(2)(2)(2)(0)(4-1 downto 0) <= local_incr_rx_vec(172-1 downto 168);
|
||
|
|
local_incr_tx_vec(172-1 downto 168) <= inter_incr_out(2)(2)(2)(0)(4-1 downto 0);
|
||
|
|
|
||
|
|
inter_vc_write_in(2)(2)(2)(0)(4-1 downto 0) <= local_vc_write_rx(172-1 downto 168);
|
||
|
|
local_vc_write_tx(172-1 downto 168) <= inter_vc_write_out(2)(2)(2)(0)(4-1 downto 0);
|
||
|
|
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
-- Router at x= 2 y=2 z=2
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
router_222: entity work.router_pl
|
||
|
|
generic map (
|
||
|
|
port_num => 6,
|
||
|
|
Xis => 2,
|
||
|
|
Yis => 2,
|
||
|
|
Zis => 2,
|
||
|
|
header_incl_in_packet_length => true,
|
||
|
|
port_exist => (0,1,2,3,4,6),
|
||
|
|
vc_num_vec => (4, 4, 4, 4, 4, 4),
|
||
|
|
vc_num_out_vec => (4, 4, 4, 4, 4, 4),
|
||
|
|
vc_depth_array => ((4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4)),
|
||
|
|
vc_depth_out_array => ((4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4)),
|
||
|
|
rout_algo => "DXYU"
|
||
|
|
)
|
||
|
|
port map (
|
||
|
|
clk => clk,
|
||
|
|
rst => rst,
|
||
|
|
data_rx => data_in222,
|
||
|
|
vc_write_rx_vec => vc_write_rx_vec222,
|
||
|
|
incr_rx_vec => incr_rx_vec222,
|
||
|
|
data_tx_pl => data_out222,
|
||
|
|
vc_write_tx_pl_vec => vc_write_tx_pl_vec222,
|
||
|
|
incr_tx_pl_vec => incr_tx_pl_vec222
|
||
|
|
);
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
-- Router port connections to adjacent routers
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
data_in322(0) <= inter_data_in(3)(2)(2)(0);
|
||
|
|
inter_data_out(3)(2)(2)(0) <= data_out322(0);
|
||
|
|
incr_rx_vec322(4-1 downto 0) <= inter_incr_in(3)(2)(2)(0)(4-1 downto 0);
|
||
|
|
inter_incr_out(3)(2)(2)(0)(4-1 downto 0) <= incr_tx_pl_vec322(4-1 downto 0);
|
||
|
|
vc_write_rx_vec322(4-1 downto 0) <= inter_vc_write_in(3)(2)(2)(0)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(3)(2)(2)(0)(4-1 downto 0) <= vc_write_tx_pl_vec322(4-1 downto 0);
|
||
|
|
data_in322(1) <= inter_data_in(3)(2)(2)(1);
|
||
|
|
inter_data_out(3)(2)(2)(1) <= data_out322(1);
|
||
|
|
incr_rx_vec322(8-1 downto 4) <= inter_incr_in(3)(2)(2)(1)(4-1 downto 0);
|
||
|
|
inter_incr_out(3)(2)(2)(1)(4-1 downto 0) <= incr_tx_pl_vec322(8-1 downto 4);
|
||
|
|
vc_write_rx_vec322(8-1 downto 4) <= inter_vc_write_in(3)(2)(2)(1)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(3)(2)(2)(1)(4-1 downto 0) <= vc_write_tx_pl_vec322(8-1 downto 4);
|
||
|
|
|
||
|
|
inter_data_in(3)(2)(2)(1) <= inter_data_out(3)(2+1)(2)(3);
|
||
|
|
|
||
|
|
inter_incr_in(3)(2)(2)(1) <= inter_incr_out(3)(2+1)(2)(3);
|
||
|
|
|
||
|
|
inter_vc_write_in(3)(2)(2)(1) <= inter_vc_write_out(3)(2+1)(2)(3);
|
||
|
|
data_in322(2) <= inter_data_in(3)(2)(2)(3);
|
||
|
|
inter_data_out(3)(2)(2)(3) <= data_out322(2);
|
||
|
|
incr_rx_vec322(12-1 downto 8) <= inter_incr_in(3)(2)(2)(3)(4-1 downto 0);
|
||
|
|
inter_incr_out(3)(2)(2)(3)(4-1 downto 0) <= incr_tx_pl_vec322(12-1 downto 8);
|
||
|
|
vc_write_rx_vec322(12-1 downto 8) <= inter_vc_write_in(3)(2)(2)(3)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(3)(2)(2)(3)(4-1 downto 0) <= vc_write_tx_pl_vec322(12-1 downto 8);
|
||
|
|
|
||
|
|
inter_data_in(3)(2)(2)(3) <= inter_data_out(3)(2-1)(2)(1);
|
||
|
|
|
||
|
|
inter_incr_in(3)(2)(2)(3) <= inter_incr_out(3)(2-1)(2)(1);
|
||
|
|
|
||
|
|
inter_vc_write_in(3)(2)(2)(3) <= inter_vc_write_out(3)(2-1)(2)(1);
|
||
|
|
data_in322(3) <= inter_data_in(3)(2)(2)(4);
|
||
|
|
inter_data_out(3)(2)(2)(4) <= data_out322(3);
|
||
|
|
incr_rx_vec322(16-1 downto 12) <= inter_incr_in(3)(2)(2)(4)(4-1 downto 0);
|
||
|
|
inter_incr_out(3)(2)(2)(4)(4-1 downto 0) <= incr_tx_pl_vec322(16-1 downto 12);
|
||
|
|
vc_write_rx_vec322(16-1 downto 12) <= inter_vc_write_in(3)(2)(2)(4)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(3)(2)(2)(4)(4-1 downto 0) <= vc_write_tx_pl_vec322(16-1 downto 12);
|
||
|
|
|
||
|
|
inter_data_in(3)(2)(2)(4) <= inter_data_out(3-1)(2)(2)(2);
|
||
|
|
|
||
|
|
inter_incr_in(3)(2)(2)(4) <= inter_incr_out(3-1)(2)(2)(2);
|
||
|
|
|
||
|
|
inter_vc_write_in(3)(2)(2)(4) <= inter_vc_write_out(3-1)(2)(2)(2);
|
||
|
|
data_in322(4) <= inter_data_in(3)(2)(2)(6);
|
||
|
|
inter_data_out(3)(2)(2)(6) <= data_out322(4);
|
||
|
|
incr_rx_vec322(20-1 downto 16) <= inter_incr_in(3)(2)(2)(6)(4-1 downto 0);
|
||
|
|
inter_incr_out(3)(2)(2)(6)(4-1 downto 0) <= incr_tx_pl_vec322(20-1 downto 16);
|
||
|
|
vc_write_rx_vec322(20-1 downto 16) <= inter_vc_write_in(3)(2)(2)(6)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(3)(2)(2)(6)(4-1 downto 0) <= vc_write_tx_pl_vec322(20-1 downto 16);
|
||
|
|
|
||
|
|
inter_data_in(3)(2)(2)(6) <= inter_data_out(3)(2)(2-1)(5);
|
||
|
|
|
||
|
|
inter_incr_in(3)(2)(2)(6) <= inter_incr_out(3)(2)(2-1)(5);
|
||
|
|
|
||
|
|
inter_vc_write_in(3)(2)(2)(6) <= inter_vc_write_out(3)(2)(2-1)(5);
|
||
|
|
|
||
|
|
inter_data_in(3)(2)(2)(0) <= local_rx(43);
|
||
|
|
local_tx(43) <= inter_data_out(3)(2)(2)(0);
|
||
|
|
|
||
|
|
inter_incr_in(3)(2)(2)(0)(4-1 downto 0) <= local_incr_rx_vec(176-1 downto 172);
|
||
|
|
local_incr_tx_vec(176-1 downto 172) <= inter_incr_out(3)(2)(2)(0)(4-1 downto 0);
|
||
|
|
|
||
|
|
inter_vc_write_in(3)(2)(2)(0)(4-1 downto 0) <= local_vc_write_rx(176-1 downto 172);
|
||
|
|
local_vc_write_tx(176-1 downto 172) <= inter_vc_write_out(3)(2)(2)(0)(4-1 downto 0);
|
||
|
|
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
-- Router at x= 3 y=2 z=2
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
router_322: entity work.router_pl
|
||
|
|
generic map (
|
||
|
|
port_num => 5,
|
||
|
|
Xis => 3,
|
||
|
|
Yis => 2,
|
||
|
|
Zis => 2,
|
||
|
|
header_incl_in_packet_length => true,
|
||
|
|
port_exist => (0,1,3,4,6),
|
||
|
|
vc_num_vec => (4, 4, 4, 4, 4),
|
||
|
|
vc_num_out_vec => (4, 4, 4, 4, 4),
|
||
|
|
vc_depth_array => ((4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4)),
|
||
|
|
vc_depth_out_array => ((4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4)),
|
||
|
|
rout_algo => "DXYU"
|
||
|
|
)
|
||
|
|
port map (
|
||
|
|
clk => clk,
|
||
|
|
rst => rst,
|
||
|
|
data_rx => data_in322,
|
||
|
|
vc_write_rx_vec => vc_write_rx_vec322,
|
||
|
|
incr_rx_vec => incr_rx_vec322,
|
||
|
|
data_tx_pl => data_out322,
|
||
|
|
vc_write_tx_pl_vec => vc_write_tx_pl_vec322,
|
||
|
|
incr_tx_pl_vec => incr_tx_pl_vec322
|
||
|
|
);
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
-- Router port connections to adjacent routers
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
data_in032(0) <= inter_data_in(0)(3)(2)(0);
|
||
|
|
inter_data_out(0)(3)(2)(0) <= data_out032(0);
|
||
|
|
incr_rx_vec032(4-1 downto 0) <= inter_incr_in(0)(3)(2)(0)(4-1 downto 0);
|
||
|
|
inter_incr_out(0)(3)(2)(0)(4-1 downto 0) <= incr_tx_pl_vec032(4-1 downto 0);
|
||
|
|
vc_write_rx_vec032(4-1 downto 0) <= inter_vc_write_in(0)(3)(2)(0)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(0)(3)(2)(0)(4-1 downto 0) <= vc_write_tx_pl_vec032(4-1 downto 0);
|
||
|
|
data_in032(1) <= inter_data_in(0)(3)(2)(2);
|
||
|
|
inter_data_out(0)(3)(2)(2) <= data_out032(1);
|
||
|
|
incr_rx_vec032(8-1 downto 4) <= inter_incr_in(0)(3)(2)(2)(4-1 downto 0);
|
||
|
|
inter_incr_out(0)(3)(2)(2)(4-1 downto 0) <= incr_tx_pl_vec032(8-1 downto 4);
|
||
|
|
vc_write_rx_vec032(8-1 downto 4) <= inter_vc_write_in(0)(3)(2)(2)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(0)(3)(2)(2)(4-1 downto 0) <= vc_write_tx_pl_vec032(8-1 downto 4);
|
||
|
|
|
||
|
|
inter_data_in(0)(3)(2)(2) <= inter_data_out(0+1)(3)(2)(4);
|
||
|
|
|
||
|
|
inter_incr_in(0)(3)(2)(2) <= inter_incr_out(0+1)(3)(2)(4);
|
||
|
|
|
||
|
|
inter_vc_write_in(0)(3)(2)(2) <= inter_vc_write_out(0+1)(3)(2)(4);
|
||
|
|
data_in032(2) <= inter_data_in(0)(3)(2)(3);
|
||
|
|
inter_data_out(0)(3)(2)(3) <= data_out032(2);
|
||
|
|
incr_rx_vec032(12-1 downto 8) <= inter_incr_in(0)(3)(2)(3)(4-1 downto 0);
|
||
|
|
inter_incr_out(0)(3)(2)(3)(4-1 downto 0) <= incr_tx_pl_vec032(12-1 downto 8);
|
||
|
|
vc_write_rx_vec032(12-1 downto 8) <= inter_vc_write_in(0)(3)(2)(3)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(0)(3)(2)(3)(4-1 downto 0) <= vc_write_tx_pl_vec032(12-1 downto 8);
|
||
|
|
|
||
|
|
inter_data_in(0)(3)(2)(3) <= inter_data_out(0)(3-1)(2)(1);
|
||
|
|
|
||
|
|
inter_incr_in(0)(3)(2)(3) <= inter_incr_out(0)(3-1)(2)(1);
|
||
|
|
|
||
|
|
inter_vc_write_in(0)(3)(2)(3) <= inter_vc_write_out(0)(3-1)(2)(1);
|
||
|
|
data_in032(3) <= inter_data_in(0)(3)(2)(6);
|
||
|
|
inter_data_out(0)(3)(2)(6) <= data_out032(3);
|
||
|
|
incr_rx_vec032(16-1 downto 12) <= inter_incr_in(0)(3)(2)(6)(4-1 downto 0);
|
||
|
|
inter_incr_out(0)(3)(2)(6)(4-1 downto 0) <= incr_tx_pl_vec032(16-1 downto 12);
|
||
|
|
vc_write_rx_vec032(16-1 downto 12) <= inter_vc_write_in(0)(3)(2)(6)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(0)(3)(2)(6)(4-1 downto 0) <= vc_write_tx_pl_vec032(16-1 downto 12);
|
||
|
|
|
||
|
|
inter_data_in(0)(3)(2)(6) <= inter_data_out(0)(3)(2-1)(5);
|
||
|
|
|
||
|
|
inter_incr_in(0)(3)(2)(6) <= inter_incr_out(0)(3)(2-1)(5);
|
||
|
|
|
||
|
|
inter_vc_write_in(0)(3)(2)(6) <= inter_vc_write_out(0)(3)(2-1)(5);
|
||
|
|
|
||
|
|
inter_data_in(0)(3)(2)(0) <= local_rx(44);
|
||
|
|
local_tx(44) <= inter_data_out(0)(3)(2)(0);
|
||
|
|
|
||
|
|
inter_incr_in(0)(3)(2)(0)(4-1 downto 0) <= local_incr_rx_vec(180-1 downto 176);
|
||
|
|
local_incr_tx_vec(180-1 downto 176) <= inter_incr_out(0)(3)(2)(0)(4-1 downto 0);
|
||
|
|
|
||
|
|
inter_vc_write_in(0)(3)(2)(0)(4-1 downto 0) <= local_vc_write_rx(180-1 downto 176);
|
||
|
|
local_vc_write_tx(180-1 downto 176) <= inter_vc_write_out(0)(3)(2)(0)(4-1 downto 0);
|
||
|
|
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
-- Router at x= 0 y=3 z=2
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
router_032: entity work.router_pl
|
||
|
|
generic map (
|
||
|
|
port_num => 4,
|
||
|
|
Xis => 0,
|
||
|
|
Yis => 3,
|
||
|
|
Zis => 2,
|
||
|
|
header_incl_in_packet_length => true,
|
||
|
|
port_exist => (0,2,3,6),
|
||
|
|
vc_num_vec => (4, 4, 4, 4),
|
||
|
|
vc_num_out_vec => (4, 4, 4, 4),
|
||
|
|
vc_depth_array => ((4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4)),
|
||
|
|
vc_depth_out_array => ((4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4)),
|
||
|
|
rout_algo => "DXYU"
|
||
|
|
)
|
||
|
|
port map (
|
||
|
|
clk => clk,
|
||
|
|
rst => rst,
|
||
|
|
data_rx => data_in032,
|
||
|
|
vc_write_rx_vec => vc_write_rx_vec032,
|
||
|
|
incr_rx_vec => incr_rx_vec032,
|
||
|
|
data_tx_pl => data_out032,
|
||
|
|
vc_write_tx_pl_vec => vc_write_tx_pl_vec032,
|
||
|
|
incr_tx_pl_vec => incr_tx_pl_vec032
|
||
|
|
);
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
-- Router port connections to adjacent routers
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
data_in132(0) <= inter_data_in(1)(3)(2)(0);
|
||
|
|
inter_data_out(1)(3)(2)(0) <= data_out132(0);
|
||
|
|
incr_rx_vec132(4-1 downto 0) <= inter_incr_in(1)(3)(2)(0)(4-1 downto 0);
|
||
|
|
inter_incr_out(1)(3)(2)(0)(4-1 downto 0) <= incr_tx_pl_vec132(4-1 downto 0);
|
||
|
|
vc_write_rx_vec132(4-1 downto 0) <= inter_vc_write_in(1)(3)(2)(0)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(1)(3)(2)(0)(4-1 downto 0) <= vc_write_tx_pl_vec132(4-1 downto 0);
|
||
|
|
data_in132(1) <= inter_data_in(1)(3)(2)(2);
|
||
|
|
inter_data_out(1)(3)(2)(2) <= data_out132(1);
|
||
|
|
incr_rx_vec132(8-1 downto 4) <= inter_incr_in(1)(3)(2)(2)(4-1 downto 0);
|
||
|
|
inter_incr_out(1)(3)(2)(2)(4-1 downto 0) <= incr_tx_pl_vec132(8-1 downto 4);
|
||
|
|
vc_write_rx_vec132(8-1 downto 4) <= inter_vc_write_in(1)(3)(2)(2)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(1)(3)(2)(2)(4-1 downto 0) <= vc_write_tx_pl_vec132(8-1 downto 4);
|
||
|
|
|
||
|
|
inter_data_in(1)(3)(2)(2) <= inter_data_out(1+1)(3)(2)(4);
|
||
|
|
|
||
|
|
inter_incr_in(1)(3)(2)(2) <= inter_incr_out(1+1)(3)(2)(4);
|
||
|
|
|
||
|
|
inter_vc_write_in(1)(3)(2)(2) <= inter_vc_write_out(1+1)(3)(2)(4);
|
||
|
|
data_in132(2) <= inter_data_in(1)(3)(2)(3);
|
||
|
|
inter_data_out(1)(3)(2)(3) <= data_out132(2);
|
||
|
|
incr_rx_vec132(12-1 downto 8) <= inter_incr_in(1)(3)(2)(3)(4-1 downto 0);
|
||
|
|
inter_incr_out(1)(3)(2)(3)(4-1 downto 0) <= incr_tx_pl_vec132(12-1 downto 8);
|
||
|
|
vc_write_rx_vec132(12-1 downto 8) <= inter_vc_write_in(1)(3)(2)(3)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(1)(3)(2)(3)(4-1 downto 0) <= vc_write_tx_pl_vec132(12-1 downto 8);
|
||
|
|
|
||
|
|
inter_data_in(1)(3)(2)(3) <= inter_data_out(1)(3-1)(2)(1);
|
||
|
|
|
||
|
|
inter_incr_in(1)(3)(2)(3) <= inter_incr_out(1)(3-1)(2)(1);
|
||
|
|
|
||
|
|
inter_vc_write_in(1)(3)(2)(3) <= inter_vc_write_out(1)(3-1)(2)(1);
|
||
|
|
data_in132(3) <= inter_data_in(1)(3)(2)(4);
|
||
|
|
inter_data_out(1)(3)(2)(4) <= data_out132(3);
|
||
|
|
incr_rx_vec132(16-1 downto 12) <= inter_incr_in(1)(3)(2)(4)(4-1 downto 0);
|
||
|
|
inter_incr_out(1)(3)(2)(4)(4-1 downto 0) <= incr_tx_pl_vec132(16-1 downto 12);
|
||
|
|
vc_write_rx_vec132(16-1 downto 12) <= inter_vc_write_in(1)(3)(2)(4)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(1)(3)(2)(4)(4-1 downto 0) <= vc_write_tx_pl_vec132(16-1 downto 12);
|
||
|
|
|
||
|
|
inter_data_in(1)(3)(2)(4) <= inter_data_out(1-1)(3)(2)(2);
|
||
|
|
|
||
|
|
inter_incr_in(1)(3)(2)(4) <= inter_incr_out(1-1)(3)(2)(2);
|
||
|
|
|
||
|
|
inter_vc_write_in(1)(3)(2)(4) <= inter_vc_write_out(1-1)(3)(2)(2);
|
||
|
|
data_in132(4) <= inter_data_in(1)(3)(2)(6);
|
||
|
|
inter_data_out(1)(3)(2)(6) <= data_out132(4);
|
||
|
|
incr_rx_vec132(20-1 downto 16) <= inter_incr_in(1)(3)(2)(6)(4-1 downto 0);
|
||
|
|
inter_incr_out(1)(3)(2)(6)(4-1 downto 0) <= incr_tx_pl_vec132(20-1 downto 16);
|
||
|
|
vc_write_rx_vec132(20-1 downto 16) <= inter_vc_write_in(1)(3)(2)(6)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(1)(3)(2)(6)(4-1 downto 0) <= vc_write_tx_pl_vec132(20-1 downto 16);
|
||
|
|
|
||
|
|
inter_data_in(1)(3)(2)(6) <= inter_data_out(1)(3)(2-1)(5);
|
||
|
|
|
||
|
|
inter_incr_in(1)(3)(2)(6) <= inter_incr_out(1)(3)(2-1)(5);
|
||
|
|
|
||
|
|
inter_vc_write_in(1)(3)(2)(6) <= inter_vc_write_out(1)(3)(2-1)(5);
|
||
|
|
|
||
|
|
inter_data_in(1)(3)(2)(0) <= local_rx(45);
|
||
|
|
local_tx(45) <= inter_data_out(1)(3)(2)(0);
|
||
|
|
|
||
|
|
inter_incr_in(1)(3)(2)(0)(4-1 downto 0) <= local_incr_rx_vec(184-1 downto 180);
|
||
|
|
local_incr_tx_vec(184-1 downto 180) <= inter_incr_out(1)(3)(2)(0)(4-1 downto 0);
|
||
|
|
|
||
|
|
inter_vc_write_in(1)(3)(2)(0)(4-1 downto 0) <= local_vc_write_rx(184-1 downto 180);
|
||
|
|
local_vc_write_tx(184-1 downto 180) <= inter_vc_write_out(1)(3)(2)(0)(4-1 downto 0);
|
||
|
|
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
-- Router at x= 1 y=3 z=2
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
router_132: entity work.router_pl
|
||
|
|
generic map (
|
||
|
|
port_num => 5,
|
||
|
|
Xis => 1,
|
||
|
|
Yis => 3,
|
||
|
|
Zis => 2,
|
||
|
|
header_incl_in_packet_length => true,
|
||
|
|
port_exist => (0,2,3,4,6),
|
||
|
|
vc_num_vec => (4, 4, 4, 4, 4),
|
||
|
|
vc_num_out_vec => (4, 4, 4, 4, 4),
|
||
|
|
vc_depth_array => ((4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4)),
|
||
|
|
vc_depth_out_array => ((4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4)),
|
||
|
|
rout_algo => "DXYU"
|
||
|
|
)
|
||
|
|
port map (
|
||
|
|
clk => clk,
|
||
|
|
rst => rst,
|
||
|
|
data_rx => data_in132,
|
||
|
|
vc_write_rx_vec => vc_write_rx_vec132,
|
||
|
|
incr_rx_vec => incr_rx_vec132,
|
||
|
|
data_tx_pl => data_out132,
|
||
|
|
vc_write_tx_pl_vec => vc_write_tx_pl_vec132,
|
||
|
|
incr_tx_pl_vec => incr_tx_pl_vec132
|
||
|
|
);
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
-- Router port connections to adjacent routers
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
data_in232(0) <= inter_data_in(2)(3)(2)(0);
|
||
|
|
inter_data_out(2)(3)(2)(0) <= data_out232(0);
|
||
|
|
incr_rx_vec232(4-1 downto 0) <= inter_incr_in(2)(3)(2)(0)(4-1 downto 0);
|
||
|
|
inter_incr_out(2)(3)(2)(0)(4-1 downto 0) <= incr_tx_pl_vec232(4-1 downto 0);
|
||
|
|
vc_write_rx_vec232(4-1 downto 0) <= inter_vc_write_in(2)(3)(2)(0)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(2)(3)(2)(0)(4-1 downto 0) <= vc_write_tx_pl_vec232(4-1 downto 0);
|
||
|
|
data_in232(1) <= inter_data_in(2)(3)(2)(2);
|
||
|
|
inter_data_out(2)(3)(2)(2) <= data_out232(1);
|
||
|
|
incr_rx_vec232(8-1 downto 4) <= inter_incr_in(2)(3)(2)(2)(4-1 downto 0);
|
||
|
|
inter_incr_out(2)(3)(2)(2)(4-1 downto 0) <= incr_tx_pl_vec232(8-1 downto 4);
|
||
|
|
vc_write_rx_vec232(8-1 downto 4) <= inter_vc_write_in(2)(3)(2)(2)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(2)(3)(2)(2)(4-1 downto 0) <= vc_write_tx_pl_vec232(8-1 downto 4);
|
||
|
|
|
||
|
|
inter_data_in(2)(3)(2)(2) <= inter_data_out(2+1)(3)(2)(4);
|
||
|
|
|
||
|
|
inter_incr_in(2)(3)(2)(2) <= inter_incr_out(2+1)(3)(2)(4);
|
||
|
|
|
||
|
|
inter_vc_write_in(2)(3)(2)(2) <= inter_vc_write_out(2+1)(3)(2)(4);
|
||
|
|
data_in232(2) <= inter_data_in(2)(3)(2)(3);
|
||
|
|
inter_data_out(2)(3)(2)(3) <= data_out232(2);
|
||
|
|
incr_rx_vec232(12-1 downto 8) <= inter_incr_in(2)(3)(2)(3)(4-1 downto 0);
|
||
|
|
inter_incr_out(2)(3)(2)(3)(4-1 downto 0) <= incr_tx_pl_vec232(12-1 downto 8);
|
||
|
|
vc_write_rx_vec232(12-1 downto 8) <= inter_vc_write_in(2)(3)(2)(3)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(2)(3)(2)(3)(4-1 downto 0) <= vc_write_tx_pl_vec232(12-1 downto 8);
|
||
|
|
|
||
|
|
inter_data_in(2)(3)(2)(3) <= inter_data_out(2)(3-1)(2)(1);
|
||
|
|
|
||
|
|
inter_incr_in(2)(3)(2)(3) <= inter_incr_out(2)(3-1)(2)(1);
|
||
|
|
|
||
|
|
inter_vc_write_in(2)(3)(2)(3) <= inter_vc_write_out(2)(3-1)(2)(1);
|
||
|
|
data_in232(3) <= inter_data_in(2)(3)(2)(4);
|
||
|
|
inter_data_out(2)(3)(2)(4) <= data_out232(3);
|
||
|
|
incr_rx_vec232(16-1 downto 12) <= inter_incr_in(2)(3)(2)(4)(4-1 downto 0);
|
||
|
|
inter_incr_out(2)(3)(2)(4)(4-1 downto 0) <= incr_tx_pl_vec232(16-1 downto 12);
|
||
|
|
vc_write_rx_vec232(16-1 downto 12) <= inter_vc_write_in(2)(3)(2)(4)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(2)(3)(2)(4)(4-1 downto 0) <= vc_write_tx_pl_vec232(16-1 downto 12);
|
||
|
|
|
||
|
|
inter_data_in(2)(3)(2)(4) <= inter_data_out(2-1)(3)(2)(2);
|
||
|
|
|
||
|
|
inter_incr_in(2)(3)(2)(4) <= inter_incr_out(2-1)(3)(2)(2);
|
||
|
|
|
||
|
|
inter_vc_write_in(2)(3)(2)(4) <= inter_vc_write_out(2-1)(3)(2)(2);
|
||
|
|
data_in232(4) <= inter_data_in(2)(3)(2)(6);
|
||
|
|
inter_data_out(2)(3)(2)(6) <= data_out232(4);
|
||
|
|
incr_rx_vec232(20-1 downto 16) <= inter_incr_in(2)(3)(2)(6)(4-1 downto 0);
|
||
|
|
inter_incr_out(2)(3)(2)(6)(4-1 downto 0) <= incr_tx_pl_vec232(20-1 downto 16);
|
||
|
|
vc_write_rx_vec232(20-1 downto 16) <= inter_vc_write_in(2)(3)(2)(6)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(2)(3)(2)(6)(4-1 downto 0) <= vc_write_tx_pl_vec232(20-1 downto 16);
|
||
|
|
|
||
|
|
inter_data_in(2)(3)(2)(6) <= inter_data_out(2)(3)(2-1)(5);
|
||
|
|
|
||
|
|
inter_incr_in(2)(3)(2)(6) <= inter_incr_out(2)(3)(2-1)(5);
|
||
|
|
|
||
|
|
inter_vc_write_in(2)(3)(2)(6) <= inter_vc_write_out(2)(3)(2-1)(5);
|
||
|
|
|
||
|
|
inter_data_in(2)(3)(2)(0) <= local_rx(46);
|
||
|
|
local_tx(46) <= inter_data_out(2)(3)(2)(0);
|
||
|
|
|
||
|
|
inter_incr_in(2)(3)(2)(0)(4-1 downto 0) <= local_incr_rx_vec(188-1 downto 184);
|
||
|
|
local_incr_tx_vec(188-1 downto 184) <= inter_incr_out(2)(3)(2)(0)(4-1 downto 0);
|
||
|
|
|
||
|
|
inter_vc_write_in(2)(3)(2)(0)(4-1 downto 0) <= local_vc_write_rx(188-1 downto 184);
|
||
|
|
local_vc_write_tx(188-1 downto 184) <= inter_vc_write_out(2)(3)(2)(0)(4-1 downto 0);
|
||
|
|
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
-- Router at x= 2 y=3 z=2
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
router_232: entity work.router_pl
|
||
|
|
generic map (
|
||
|
|
port_num => 5,
|
||
|
|
Xis => 2,
|
||
|
|
Yis => 3,
|
||
|
|
Zis => 2,
|
||
|
|
header_incl_in_packet_length => true,
|
||
|
|
port_exist => (0,2,3,4,6),
|
||
|
|
vc_num_vec => (4, 4, 4, 4, 4),
|
||
|
|
vc_num_out_vec => (4, 4, 4, 4, 4),
|
||
|
|
vc_depth_array => ((4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4)),
|
||
|
|
vc_depth_out_array => ((4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4)),
|
||
|
|
rout_algo => "DXYU"
|
||
|
|
)
|
||
|
|
port map (
|
||
|
|
clk => clk,
|
||
|
|
rst => rst,
|
||
|
|
data_rx => data_in232,
|
||
|
|
vc_write_rx_vec => vc_write_rx_vec232,
|
||
|
|
incr_rx_vec => incr_rx_vec232,
|
||
|
|
data_tx_pl => data_out232,
|
||
|
|
vc_write_tx_pl_vec => vc_write_tx_pl_vec232,
|
||
|
|
incr_tx_pl_vec => incr_tx_pl_vec232
|
||
|
|
);
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
-- Router port connections to adjacent routers
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
data_in332(0) <= inter_data_in(3)(3)(2)(0);
|
||
|
|
inter_data_out(3)(3)(2)(0) <= data_out332(0);
|
||
|
|
incr_rx_vec332(4-1 downto 0) <= inter_incr_in(3)(3)(2)(0)(4-1 downto 0);
|
||
|
|
inter_incr_out(3)(3)(2)(0)(4-1 downto 0) <= incr_tx_pl_vec332(4-1 downto 0);
|
||
|
|
vc_write_rx_vec332(4-1 downto 0) <= inter_vc_write_in(3)(3)(2)(0)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(3)(3)(2)(0)(4-1 downto 0) <= vc_write_tx_pl_vec332(4-1 downto 0);
|
||
|
|
data_in332(1) <= inter_data_in(3)(3)(2)(3);
|
||
|
|
inter_data_out(3)(3)(2)(3) <= data_out332(1);
|
||
|
|
incr_rx_vec332(8-1 downto 4) <= inter_incr_in(3)(3)(2)(3)(4-1 downto 0);
|
||
|
|
inter_incr_out(3)(3)(2)(3)(4-1 downto 0) <= incr_tx_pl_vec332(8-1 downto 4);
|
||
|
|
vc_write_rx_vec332(8-1 downto 4) <= inter_vc_write_in(3)(3)(2)(3)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(3)(3)(2)(3)(4-1 downto 0) <= vc_write_tx_pl_vec332(8-1 downto 4);
|
||
|
|
|
||
|
|
inter_data_in(3)(3)(2)(3) <= inter_data_out(3)(3-1)(2)(1);
|
||
|
|
|
||
|
|
inter_incr_in(3)(3)(2)(3) <= inter_incr_out(3)(3-1)(2)(1);
|
||
|
|
|
||
|
|
inter_vc_write_in(3)(3)(2)(3) <= inter_vc_write_out(3)(3-1)(2)(1);
|
||
|
|
data_in332(2) <= inter_data_in(3)(3)(2)(4);
|
||
|
|
inter_data_out(3)(3)(2)(4) <= data_out332(2);
|
||
|
|
incr_rx_vec332(12-1 downto 8) <= inter_incr_in(3)(3)(2)(4)(4-1 downto 0);
|
||
|
|
inter_incr_out(3)(3)(2)(4)(4-1 downto 0) <= incr_tx_pl_vec332(12-1 downto 8);
|
||
|
|
vc_write_rx_vec332(12-1 downto 8) <= inter_vc_write_in(3)(3)(2)(4)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(3)(3)(2)(4)(4-1 downto 0) <= vc_write_tx_pl_vec332(12-1 downto 8);
|
||
|
|
|
||
|
|
inter_data_in(3)(3)(2)(4) <= inter_data_out(3-1)(3)(2)(2);
|
||
|
|
|
||
|
|
inter_incr_in(3)(3)(2)(4) <= inter_incr_out(3-1)(3)(2)(2);
|
||
|
|
|
||
|
|
inter_vc_write_in(3)(3)(2)(4) <= inter_vc_write_out(3-1)(3)(2)(2);
|
||
|
|
data_in332(3) <= inter_data_in(3)(3)(2)(6);
|
||
|
|
inter_data_out(3)(3)(2)(6) <= data_out332(3);
|
||
|
|
incr_rx_vec332(16-1 downto 12) <= inter_incr_in(3)(3)(2)(6)(4-1 downto 0);
|
||
|
|
inter_incr_out(3)(3)(2)(6)(4-1 downto 0) <= incr_tx_pl_vec332(16-1 downto 12);
|
||
|
|
vc_write_rx_vec332(16-1 downto 12) <= inter_vc_write_in(3)(3)(2)(6)(4-1 downto 0);
|
||
|
|
inter_vc_write_out(3)(3)(2)(6)(4-1 downto 0) <= vc_write_tx_pl_vec332(16-1 downto 12);
|
||
|
|
|
||
|
|
inter_data_in(3)(3)(2)(6) <= inter_data_out(3)(3)(2-1)(5);
|
||
|
|
|
||
|
|
inter_incr_in(3)(3)(2)(6) <= inter_incr_out(3)(3)(2-1)(5);
|
||
|
|
|
||
|
|
inter_vc_write_in(3)(3)(2)(6) <= inter_vc_write_out(3)(3)(2-1)(5);
|
||
|
|
|
||
|
|
inter_data_in(3)(3)(2)(0) <= local_rx(47);
|
||
|
|
local_tx(47) <= inter_data_out(3)(3)(2)(0);
|
||
|
|
|
||
|
|
inter_incr_in(3)(3)(2)(0)(4-1 downto 0) <= local_incr_rx_vec(192-1 downto 188);
|
||
|
|
local_incr_tx_vec(192-1 downto 188) <= inter_incr_out(3)(3)(2)(0)(4-1 downto 0);
|
||
|
|
|
||
|
|
inter_vc_write_in(3)(3)(2)(0)(4-1 downto 0) <= local_vc_write_rx(192-1 downto 188);
|
||
|
|
local_vc_write_tx(192-1 downto 188) <= inter_vc_write_out(3)(3)(2)(0)(4-1 downto 0);
|
||
|
|
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
-- Router at x= 3 y=3 z=2
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
router_332: entity work.router_pl
|
||
|
|
generic map (
|
||
|
|
port_num => 4,
|
||
|
|
Xis => 3,
|
||
|
|
Yis => 3,
|
||
|
|
Zis => 2,
|
||
|
|
header_incl_in_packet_length => true,
|
||
|
|
port_exist => (0,3,4,6),
|
||
|
|
vc_num_vec => (4, 4, 4, 4),
|
||
|
|
vc_num_out_vec => (4, 4, 4, 4),
|
||
|
|
vc_depth_array => ((4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4)),
|
||
|
|
vc_depth_out_array => ((4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4), (4, 4, 4, 4)),
|
||
|
|
rout_algo => "DXYU"
|
||
|
|
)
|
||
|
|
port map (
|
||
|
|
clk => clk,
|
||
|
|
rst => rst,
|
||
|
|
data_rx => data_in332,
|
||
|
|
vc_write_rx_vec => vc_write_rx_vec332,
|
||
|
|
incr_rx_vec => incr_rx_vec332,
|
||
|
|
data_tx_pl => data_out332,
|
||
|
|
vc_write_tx_pl_vec => vc_write_tx_pl_vec332,
|
||
|
|
incr_tx_pl_vec => incr_tx_pl_vec332
|
||
|
|
);
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
-- Router port connections to adjacent routers
|
||
|
|
--------------------------------------------------------------------------
|
||
|
|
end architecture structural;
|
||
|
|
|