166 lines
7.3 KiB
VHDL
166 lines
7.3 KiB
VHDL
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-------------------------------------------------------------------------------
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-- Title : Header arbiter and decoder
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-- Project : Modular, heterogenous 3D NoC
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-------------------------------------------------------------------------------
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-- File : header_arbiter_and_decoder.vhd
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-- Author : Lennart Bamberg <lennart@x230>
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-- Company :
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-- Created : 2018-11-05
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-- Last update: 2018-11-28
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-- Platform :
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-- Standard : VHDL'93/02
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-------------------------------------------------------------------------------
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-- Description: Arbitrate next VC in the input to be assigned to an output VC.
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-- For the granted input the routing is calculated, and the request
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-- to the output is made. Also a counter with the packet length is
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-- set. Via enable-read (enr_vc) the end of the packet is trackes,
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-- which indicated that the next valid flit in the input vc will be
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-- teh head-flit of a new package (new arbitration).
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-- COMMENTS:
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-- We have a 'strong' fifo fairness. Thus, if one packet
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-- is blocked and it waits in the only virtual channel that wasn't
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-- recently served, we wait for the blocking to be solved!
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-- For a week fairness (with potentially a higher throughput) set
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-- "ack" of the RR-arbiter to constant '1'.
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-------------------------------------------------------------------------------
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-- Copyright (c) 2018
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-------------------------------------------------------------------------------
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-- Revisions :
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-- Date Version Author Description
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-- 2018-11-05 1.0 lennart Created
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.std_logic_misc.all;
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use work.NOC_3D_PACKAGE.all;
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use work.TURNS_3D_NOC.all;
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entity header_arbiter_and_decoder is
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generic (Xis : natural := 1;
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Yis : natural := 1;
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Zis : natural := 1;
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port_num : integer := 7;
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port_exist : integer_vec := (0, 1, 2, 3, 4, 5, 6);
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port_is : integer := 1; -- current port
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vc_num : positive := 4;
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header_incl_in_packet_length : boolean := true;
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rout_algo : string := "DXYU");
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port (
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clk, rst : in std_logic;
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header : in header_inf_vector(vc_num-1 downto 0);
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valid_data_vc : in std_logic_vector(vc_num-1 downto 0);
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enr_vc : in std_logic_vector(vc_num-1 downto 0); -- ONE-HOT
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ack_vc : in std_logic; -- acknowledge of vc allocation
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granted_rq : out std_logic_vector(port_num-1 downto 0);
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input_vc_in_use : out std_logic_vector(vc_num-1 downto 0);
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-- indicate if a vc is free again in the next cc
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packet_end : out std_logic_vector(vc_num-1 downto 0);
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granted_vc : out std_logic_vector(vc_num-1 downto 0)
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);
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end header_arbiter_and_decoder;
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architecture rtl of header_arbiter_and_decoder is
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constant poss_routes : turn_table_3D := routes_3D(rout_algo);
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signal new_package_vc, grant : std_logic_vector(vc_num-1 downto 0);
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signal flit_count_0, flit_count_1 : std_logic_vector(vc_num-1 downto 0);
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type flit_counter_vector is array(vc_num-1 downto 0) of
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unsigned(packet_len_width-1 downto 0);
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signal flit_count_values : flit_counter_vector;
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signal header_nxt : header_inf; -- current analyzed header
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signal address_nxt : address_inf; -- current analyzed header
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signal routing_en : std_logic;
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signal granted_rq_cmplt : std_logic_vector(6 downto 0);
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signal allocated : std_logic_vector(vc_num-1 downto 0);
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signal packet_length_nxt : std_logic_vector(packet_len_width-1 downto 0);
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begin
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-----------------------------------------------------------------------------
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-- Check if in any VC a new package has to be en encoded and also if in the
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-- next clock cycle any VV becomes free again--------------------------------
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-----------------------------------------------------------------------------
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GEN_COUNT_EQ_ZERO : for i in 0 to vc_num-1 generate
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flit_count_0(i) <= '1' when (flit_count_values(i) = to_unsigned(0, packet_len_width))
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else '0';
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flit_count_1(i) <= '1' when (flit_count_values(i) = to_unsigned(1, packet_len_width))
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else '0'; -- Only req 1 extra gate to flit_count_0
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end generate;
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input_vc_in_use <= not(flit_count_0);
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packet_end <= flit_count_1 and enr_vc;
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new_package_vc <= flit_count_0 and valid_data_vc;
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-----------------------------------------------------------------------------
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-- Round robin arbitration between all new packages -------------------------
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-----------------------------------------------------------------------------
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GEN_RR : if vc_num > 1 generate
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-- to add an extra pipeline stage for the rout_algo just intanciate
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-- "rr_arbiter" instead of "rr_arbiter_no_delay" ??
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rr_arbiter_no_delay_1 : entity work.rr_arbiter_no_delay
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generic map (
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CNT => vc_num)
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port map (
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clk => clk,
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rst => rst,
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req => new_package_vc,
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ack => ack_vc,
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grant => grant);
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header_nxt <= header(one_hot2int(grant)); -- next header to be decoded
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end generate;
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GEN_PASS_NO_VC : if vc_num = 1 generate
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grant <= new_package_vc;
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header_nxt <= header(0);
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end generate;
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address_nxt <= extract_address_inf(header_nxt);
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packet_length_nxt <= header_nxt.packet_length;
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routing_en <= or_reduce(grant);
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granted_vc <= grant;
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-----------------------------------------------------------------------------
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---------------------------- Routing computation ----------------------------
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-----------------------------------------------------------------------------
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routing_calc_1 : entity work.routing_calc
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generic map (
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Xis => Xis,
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Yis => Yis,
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Zis => Zis,
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rout_algo => rout_algo)
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port map (
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address => address_nxt,
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enable => routing_en,
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routing => granted_rq_cmplt);
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--check which routes are actually possible. Set non-possible 0
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process(granted_rq_cmplt)
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begin
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granted_rq <= (others => '0');
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for i in 0 to port_num-1 loop
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if poss_routes(port_is)(port_exist(i)) then
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granted_rq(i) <= granted_rq_cmplt(port_exist(i));
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end if;
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end loop;
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end process;
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allocated <= (others => '0') when ack_vc = '0' else grant;
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-----------------------------------------------------------------------------
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-- Generate the storage Elements, including the flit counter ----------------
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-----------------------------------------------------------------------------
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STOR_GEN : for i in 0 to vc_num-1 generate
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seq_packet_counter_i : entity work.seq_packet_counter
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generic map (
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header_incl_in_packet_length => header_incl_in_packet_length)
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port map (
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clk => clk,
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rst => rst,
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allocated => allocated(i),
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packet_len => header_nxt.packet_length,
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enr_vc => enr_vc(i),
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flit_count => flit_count_values(i));
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end generate;
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end rtl;
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