68 lines
2 KiB
VHDL
68 lines
2 KiB
VHDL
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-------------------------------------------------------------------------------
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-- Title : Test pattern receiver
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-- Project : NoC testbench generator
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-------------------------------------------------------------------------------
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-- File : traffic_rec.vhd
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-- Author : Seyed Nima Omidsajedi <nima@omidsajedi.com>
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-- Company : University of Bremen
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-------------------------------------------------------------------------------
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-- Copyright (c) 2019
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-------------------------------------------------------------------------------
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-- Vesion : 1.9.0
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.std_logic_textio.all;
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use std.textio.all;
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use work.NOC_3D_PACKAGE.all;
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entity traffic_rec is
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generic(
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flit_width : positive := flit_size;
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rec_time_text : string := "receive_time_noc.txt";
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rec_data_text : string := "receive_data_noc.txt"
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);
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port(
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clk, rst : in std_logic := '0';
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valid : in std_logic := '0';
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incr : out std_logic := '0';
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data_in : in flit := (others => '0')
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);
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end entity;
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architecture behave of traffic_rec is
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-- Used text files
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file rec_time : text open write_mode is rec_time_text;
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file rec_data : text open write_mode is rec_data_text;
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begin
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-- Set increment
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incr <= valid;
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-------------------------------------------------------------------
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--------------------------- write Process -------------------------
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write_data: process(clk, rst)
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variable rowOut: line;
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variable data_time: time := 0 ns;
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begin
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if clk = '1' and clk'event and rst = not(RST_LVL) then
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if (valid = '1') then
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write(rowOut, data_in);
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writeline(rec_data, rowOut);
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data_time := now - clk_period;
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write(rowOut, data_time);
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writeline(rec_time, rowOut);
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end if;
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end if;
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end process;
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--------------------------------------------------------------------
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-------------------------------------------------------------------
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end architecture;
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