100 lines
4.1 KiB
VHDL
100 lines
4.1 KiB
VHDL
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-------------------------------------------------------------------------------
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-- Title : Input buffer when virtual channels are used
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-- (for credit based flow-control)
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-- Project : Modular, heterogenous 3D NoC
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-------------------------------------------------------------------------------
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-- File : vc_input_buffer.vhd
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-- Author : Lennart Bamberg <bamberg@office.item.uni-bremen.de>
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-- Company :
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-- Created : 2018-05-24
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-- Last update: 2018-11-28
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-- Platform :
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-- Standard : VHDL'93/02
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-------------------------------------------------------------------------------
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-- Description: An input buffer consists of vc_num (number of virtual channels)
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-- paralell input buffers, whose depth is defined via "vc_depth".
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-- The one hot encoded signal vc_write_rx determines in which VC
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-- data is written (max. 1). vc_transfer determines from which VC
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-- data is transfered to the next router (max. 1).
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-- The LSBs of the next flit are forwarded to the the centralized
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-- arbiter, as they containing the information req. to route the
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-- package of the network if the flit is a head-flit. Also the
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-- information which VC contains valid data is provided for the
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-- centralized arbiter.
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-------------------------------------------------------------------------------
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-- Copyright (c) 2018
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-------------------------------------------------------------------------------
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-- Revisions :
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-- Date Version Author Description
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-- 2018-05-24 1.0 bamberg Created
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.math_real.all;
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use ieee.numeric_std.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_misc.all;
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use work.NOC_3D_PACKAGE.all;
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entity vc_input_buffer is
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generic(vc_num : positive := 4; -- Virtual channels (VC)
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vc_depth : integer_vec := (4 ,4 ,4 ,4 )); -- Buff depth of each VC
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port(clk : in std_logic;
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rst : in std_logic;
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data_rx : in flit;
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vc_write_rx : in std_logic_vector(vc_num-1 downto 0); -- Write EN VC
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vc_transfer : in std_logic_vector(vc_num-1 downto 0); -- Read EN VC
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valid_data_vc : out std_logic_vector(vc_num-1 downto 0); --
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data_transfer : out flit; --
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-- Information from the header that are required for path-finding
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-- and channel allocation (Destination Address & Packet-Length)
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header : out header_inf_vector(vc_num-1 downto 0)
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);
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end entity vc_input_buffer;
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architecture rtl of vc_input_buffer is
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signal buffer_out_vector : flit_vector(vc_num-1 downto 0);
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begin
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-----------------------------------------------------------------------------
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------------- Structural Part - Generate FIFOs for each VC ------------------
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-----------------------------------------------------------------------------
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buffer_gen : for i in 0 to vc_num-1 generate
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fifo_i : entity work.fifo generic map(buff_depth => vc_depth(vc_depth'left+i))
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port map (data_in => data_rx,
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write_en => vc_write_rx(i),
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read_en => vc_transfer(i),
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clk => clk,
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rst => rst,
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data_out => buffer_out_vector(i),
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valid_data => valid_data_vc(i)
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);
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end generate buffer_gen;
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-----------------------------------------------------------------------------
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------------- Logic Part - Calculate outputs --------------------------------
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-----------------------------------------------------------------------------
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OUTPUT_MUX : if vc_num > 1 generate
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process(buffer_out_vector, vc_transfer)
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begin
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data_transfer <= (others => '-');
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if or_reduce(vc_transfer) = '1' then
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data_transfer <= buffer_out_vector(one_hot2int(vc_transfer));
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end if;
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end process;
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end generate;
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OUTPUT_PASS : if vc_num = 1 generate
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data_transfer <= buffer_out_vector(0);
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end generate;
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HEADER_GEN : for i in 0 to vc_num-1 generate
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header(i) <= get_header_inf(buffer_out_vector(i));
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end generate;
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end rtl;
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