96 lines
2.6 KiB
VHDL
96 lines
2.6 KiB
VHDL
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-------------------------------------------------------------------------------
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-- Title : Routing calc at position (Xis,Yis,Zis) in a
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-- A-3D NOC
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-- Project : modular, heterogenous 3D NoC
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-------------------------------------------------------------------------------
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-- File : routing_calc.vhd
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-- Author : Lennart Bamberg <bamberg@office.item.uni-bremen.de>
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-- Company : ITEM.ids, University of Bremen
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-- Created : 2018-04-03
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-- Last update: 2018-11-14
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-- Platform : Linux Debian 8
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-- Standard : VHDL'93/02
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-------------------------------------------------------------------------------
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-- Description:
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-------------------------------------------------------------------------------
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-- Copyright (c) 2018
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-------------------------------------------------------------------------------
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-- Revisions :
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-- Date Version Author Description
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-- 2018-04-03 1.0 bamberg Created
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.math_real.all;
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use ieee.numeric_std.all;
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use work.NOC_3D_PACKAGE.all;
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entity routing_calc is
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generic(
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Xis : natural := 1;
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Yis : natural := 1;
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Zis : natural := 1;
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rout_algo : string := "DXYU");
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port(
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address : in address_inf;
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enable : in std_logic;
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routing : out std_logic_vector(6 downto 0));
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end routing_calc;
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architecture rtl of routing_calc is
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begin
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ROUTING_DXYU : if rout_algo = "DXYU" generate
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dxyu_routing_1 : entity work.dxyu_routing
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generic map (
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Xis => Xis,
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Yis => Yis,
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Zis => Zis)
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port map (
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address => address,
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enable => enable,
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routing => routing);
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end generate;
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ROUTING_UXYD : if rout_algo = "UXYD" generate
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dxyu_routing_1 : entity work.uxyd_routing
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generic map (
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Xis => Xis,
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Yis => Yis,
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Zis => Zis)
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port map (
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address => address,
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enable => enable,
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routing => routing);
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end generate;
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ROUTING_XYZ : if rout_algo = "XYZ" or rout_algo = "XYZ_ref"
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or rout_algo = "XYZ_REF" generate
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dxyu_routing_1 : entity work.xyz_routing
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generic map (
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Xis => Xis,
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Yis => Yis,
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Zis => Zis)
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port map (
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address => address,
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enable => enable,
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routing => routing);
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end generate;
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ROUTING_ZXY : if rout_algo = "ZXY" generate
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dxyu_routing_1 : entity work.zxy_routing
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generic map (
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Xis => Xis,
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Yis => Yis,
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Zis => Zis)
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port map (
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address => address,
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enable => enable,
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routing => routing);
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end generate;
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end architecture;
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