262 lines
13 KiB
VHDL
262 lines
13 KiB
VHDL
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-------------------------------------------------------------------------------
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-- Title : Switch allocator
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-- Project : Modular, heterogenous 3D NoC
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-------------------------------------------------------------------------------
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-- File : switch_allocator.vhd
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-- Author : Lennart Bamberg <bamberg@office.item.uni-bremen.de>
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-- Company :
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-- Created : 2018-11-15
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-- Last update: 2018-11-28
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-- Platform :
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-- Standard : VHDL'93/02
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-------------------------------------------------------------------------------
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-- Description: Switch allocator witch sets the input to output connections
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-- between assigned input VCs (with valid data) and the according
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-- outputs VCs (when credit is available).
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-------------------------------------------------------------------------------
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--Desginer comments: With an encoded vc_transfer and a valid signal the
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-- input VC select signal could be determined in advance.
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-- Since this is part of the crit. path, it has a potential
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-- to enhance timing if we slightly mod. the design (-power).
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-- Second possiblity to improve speed would be to pre-calcu-
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-- late the next switch allocation. This is realized by
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-- simply swapping the regular RR-arbiters by delayed RR-
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-- arbiters (see DESIGNER-HINT l. 181). The drawback would be
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-- a one clock-cycle bigger initial latency for the first flit
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-- of a new package.
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-------------------------------------------------------------------------------
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-- Copyright (c) 2018
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-------------------------------------------------------------------------------
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-- Revisions :
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-- Date Version Author Description
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-- 2018-11-15 1.0 bamberg Created
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_misc.all;
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use work.NOC_3D_PACKAGE.all;
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use work.TURNS_3D_NOC.all;
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entity switch_allocator is
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generic (
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port_num : integer := 7;
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-- integer vector of range "0 to port_num-1"
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port_exist : integer_vec := (0, 1, 2, 3, 4, 5, 6);
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vc_num_vec : integer_vec := (4 ,4 ,4 ,4 ,4 ,4 ,4 );
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vc_num_out_vec : integer_vec := (4 ,4 ,4 ,4 ,4 ,4 ,4 );
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-- integer vector of range "0 to port_num-1, 0 to max_vc_num-1"
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vc_depth_array : vc_prop_int_array := ((4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) );
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vc_depth_out_array : vc_prop_int_array := ((4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) );
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rout_algo : string := "DXYU"
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);
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port(
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clk, rst : in std_logic;
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-- Inputs from VC allocator
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input_vc_in_use : in std_logic_vector(int_vec_sum(vc_num_vec)-1 downto 0);
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output_vc_in_use : in std_logic_vector(int_vec_sum(vc_num_out_vec)-1 downto 0);
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crossbar_ctrl_vec : in std_logic_vector(int_vec_sum(vc_num_out_vec)*
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bit_width(port_num-1)-1 downto 0);
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vc_sel_enc_vec : in vc_status_array_enc(int_vec_sum(vc_num_out_vec)-1 downto 0);
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-- Inputs from Input buffer
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valid_data_vc_vec : in std_logic_vector(int_vec_sum(vc_num_vec)-1 downto 0); --
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-- Inputs from Link
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incr_rx_vec : in std_logic_vector(int_vec_sum(vc_num_out_vec)-1 downto 0);
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-- Output to crossbar
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crossbar_ctrl : out std_logic_vector(port_num*bit_width(port_num-1)-1 downto 0);
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-- output to Inbut Buffer (vc_transfer) and output-buffer (incr_tx)
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vc_transfer_vec : out std_logic_vector(int_vec_sum(vc_num_vec)-1 downto 0);
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vc_write_tx_vec : out std_logic_vector(int_vec_sum(vc_num_out_vec)-1 downto 0)
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);
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end entity switch_allocator;
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architecture rtl of switch_allocator is
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constant poss_routes : turn_table_3D := routes_3D(rout_algo);
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constant sel_width : positive := bit_width(port_num-1);
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signal switch_rq : std_logic_vector(int_vec_sum(vc_num_vec)-1 downto 0);
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signal switch_rq_grant : vc_status_array(port_num-1 downto 0);
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signal vc_transfer_vec_int : std_logic_vector(int_vec_sum(vc_num_vec)-1 downto 0);
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type switch_ack_array is array(port_num-1 downto 0) of std_logic_vector(port_num-1 downto 0);
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signal switch_acks : switch_ack_array;
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signal switch_ack : std_logic_vector(port_num-1 downto 0);
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type crossbar_ctrl_array_type is array(int_vec_sum(vc_num_out_vec)-1 downto 0) of std_logic_vector(sel_width-1 downto 0);
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signal crossbar_ctrl_vc_out : crossbar_ctrl_array_type;
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type rq_array is array (port_num-1 downto 0) of vc_status_array(port_num-2 downto 0);
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signal poss_channel_rq : rq_array;
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signal channel_rq, channel_grant : std_logic_vector(int_vec_sum(vc_num_out_vec)-1 downto 0);
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signal credit_avail : std_logic_vector(int_vec_sum(vc_num_out_vec)-1 downto 0);
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begin -- architecture rtl
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-------------------------------------------------------------------------------
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-- Transform the crossbar ctrls into an array for better readability ----------
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-------------------------------------------------------------------------------
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XBAR_CTRL : for i in 0 to int_vec_sum(vc_num_out_vec)-1 generate
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crossbar_ctrl_vc_out(i) <= crossbar_ctrl_vec((i+1)*sel_width-1 downto i*sel_width);
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end generate;
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-------------------------------------------------------------------------------
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-- When an input VC is assigned and contains data: a switch request is made ---
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-------------------------------------------------------------------------------
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switch_rq <= input_vc_in_use and valid_data_vc_vec;
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-------------------------------------------------------------------------------
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-- For each input VC arbitrate grant one switch request in a RR manner --------
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-------------------------------------------------------------------------------
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INPUT_ARB_GEN : for i in 0 to port_num-1 generate
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constant ur_vc : natural := upper_range(vc_num_vec, i);
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constant lr_vc : natural := lower_range(vc_num_vec, i);
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begin
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PASS_NO_VC : if vc_num_vec(i) = 1 generate -- single vc --> no arb. required
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switch_rq_grant(i)(0) <= switch_rq(lr_vc);
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end generate;
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GEN_RR : if vc_num_vec(i) > 1 generate
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rr_arbiter : entity work.rr_arbiter_no_delay
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generic map (
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CNT => vc_num_vec(i))
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port map (
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clk => clk,
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rst => rst,
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req => switch_rq(ur_vc downto lr_vc),
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ack => switch_ack(i),
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grant => switch_rq_grant(i)(vc_num_vec(i)-1 downto 0));
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end generate;
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end generate;
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-------------------------------------------------------------------------------
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-- Wiring of granted switch request to the according outputs in the order the
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-- crossbar select is defined (clock-wise / modulo). Thereby we exploits that
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-- some request are not possible, since a routing forbids it for dead and live-
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-- lock avoidance (don't care to reduce the circuit complexity after synthesis)
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-------------------------------------------------------------------------------
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WIRING : process(switch_rq_grant)
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variable var_in : natural;
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begin
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poss_channel_rq <= (others => (others => (others => '-')));
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for y in 0 to port_num-1 loop -- For the phy channel at output y,
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for x in 0 to port_num-2 loop -- the x^th possible input is
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if y+x < port_num-1 then
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var_in := y+x+1; -- clock wise
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else
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var_in := y+x-port_num+1; -- modulo
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end if;
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if poss_routes(port_exist(var_in))(port_exist(y)) then
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poss_channel_rq(y)(x) <= switch_rq_grant(var_in);
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end if;
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end loop;
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end loop;
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end process;
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-------------------------------------------------------------------------------
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-- Choose (multiplex) the "channel_rq" out of the "poss_channel_rq" in depend.
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-- of VC allocation ("crossbar_ctrl_vec" & "vc_sel_enc_vec") ------------------
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-------------------------------------------------------------------------------
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MUX_CHANNEL_RQ_GEN : process(credit_avail, crossbar_ctrl_vc_out, output_vc_in_use,
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poss_channel_rq, vc_sel_enc_vec)
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variable assigned_input : std_logic_vector(sel_width-1 downto 0);
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variable assigned_vc : vc_status_vec_enc;
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variable lr_vc_out, ur_vc_out : natural range 0 to int_vec_sum(vc_num_out_vec)-1;
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begin
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for port_i in 0 to port_num-1 loop
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lr_vc_out := lower_range(vc_num_out_vec, port_i);
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ur_vc_out := upper_range(vc_num_out_vec, port_i);
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for vc_i in lr_vc_out to ur_vc_out loop
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assigned_input := crossbar_ctrl_vc_out(vc_i);
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assigned_vc := vc_sel_enc_vec(vc_i);
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channel_rq(vc_i) <=
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poss_channel_rq(port_i)(slv2int(assigned_input))(slv2int(assigned_vc))
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and output_vc_in_use(vc_i) and credit_avail(vc_i);
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end loop;
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end loop;
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end process;
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-------------------------------------------------------------------------------
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-- Generate the physical channel (output) arbiters ----------------------------
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-------------------------------------------------------------------------------
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OUTPUT_ARB_GEN : for i in 0 to port_num-1 generate
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constant ur_vc_out : natural := upper_range(vc_num_out_vec, i);
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constant lr_vc_out : natural := lower_range(vc_num_out_vec, i);
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begin
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PASS_NO_VC : if vc_num_out_vec(i) = 1 generate -- single vc --> no arb. required
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channel_grant(lr_vc_out) <= channel_rq(lr_vc_out);
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end generate;
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-- DESIGNER_HINT maybe use a delayed rr_arbitter (allows speed improvement)
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GEN_RR : if vc_num_out_vec(i) > 1 generate
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rr_arbiter : entity work.rr_arbiter_no_delay
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generic map (
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CNT => vc_num_out_vec(i))
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port map (
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clk => clk,
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rst => rst,
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req => channel_rq(ur_vc_out downto lr_vc_out),
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ack => '1',
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grant => channel_grant(ur_vc_out downto lr_vc_out));
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end generate;
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CREDIT_COUNT_GENERATE : for vc_i in lr_vc_out to ur_vc_out generate
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credit_count_i : entity work.credit_count_single
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generic map (
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vc_depth_out => vc_depth_out_array(i)(vc_i-lr_vc_out))
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port map (
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clk => clk,
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rst => rst,
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incr_rx => incr_rx_vec(vc_i),
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vc_write_tx => channel_grant(vc_i), -- EQUAL: vc_write_tx_vec
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credit_avail => credit_avail(vc_i));
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end generate;
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end generate;
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vc_write_tx_vec <= channel_grant;
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-----------------------------------------------------------------------------
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-- Crossbar ctrl, input acknowledge out of winner----------------------------
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-----------------------------------------------------------------------------
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DECODE_INPUT_ACK : for i in 0 to port_num-1 generate
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constant ur : natural := upper_range(vc_num_out_vec, i);
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constant lr : natural := lower_range(vc_num_out_vec, i);
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begin
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process(channel_grant(ur downto lr), crossbar_ctrl_vc_out)
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variable winner : natural range 0 to int_vec_sum(vc_num_out_vec)-1;
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variable input_winner : natural range 0 to port_num-1;
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begin
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crossbar_ctrl((i+1)*sel_width-1 downto i*sel_width) <= (others => '-');
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switch_acks(i) <= (others => '0');
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if vc_num_out_vec(i) = 1 then
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winner := lr;
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else
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winner := lr + one_hot2int(channel_grant(ur downto lr));
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end if;
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crossbar_ctrl((i+1)*sel_width-1 downto i*sel_width) <= crossbar_ctrl_vc_out(winner);
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if or_reduce(channel_grant(ur downto lr)) = '1' then
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input_winner := (slv2int(crossbar_ctrl_vc_out(winner))+ i + 1) mod port_num;
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switch_acks(i)(input_winner) <= '1';
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end if;
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end process;
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end generate;
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INP_ACK : process(switch_acks)
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variable switch_ack_var : std_logic_vector(port_num-1 downto 0);
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begin
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switch_ack_var := (others => '0');
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for i in 0 to port_num-1 loop
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switch_ack_var := switch_ack_var or switch_acks(i);
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end loop;
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switch_ack <= switch_ack_var;
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end process;
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process(switch_ack, switch_rq_grant)
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variable ur, lr : natural range 0 to int_vec_sum(vc_num_vec)-1;
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begin
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vc_transfer_vec_int <= (others => '0');
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for i in 0 to port_num-1 loop
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if switch_ack(i) = '1' then
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ur := upper_range(vc_num_vec, i);
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lr := lower_range(vc_num_vec, i);
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vc_transfer_vec_int(ur downto lr) <= switch_rq_grant(i)(vc_num_vec(i)-1 downto 0);
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end if;
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end loop;
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end process;
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vc_transfer_vec <= vc_transfer_vec_int;
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end architecture;
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