68 lines
2.4 KiB
VHDL
68 lines
2.4 KiB
VHDL
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-------------------------------------------------------------------------------
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-- Title : Up-X-Y-Down routing for a router at position (Xis,Yis,Zis) in a
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-- A-3D NOC
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-- Project : modular, heterogenous 3D NoC
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-------------------------------------------------------------------------------
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-- File : uxyd_routing.vhd
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-- Author : Lennart Bamberg <bamberg@office.item.uni-bremen.de>
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-- Company : ITEM.ids, University of Bremen
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-- Created : 2018-04-03
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-- Last update: 2018-11-13
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-- Platform : Linux Debian 8
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-- Standard : VHDL'93/02
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-------------------------------------------------------------------------------
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-- Description:
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-------------------------------------------------------------------------------
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-- Copyright (c) 2018
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-------------------------------------------------------------------------------
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-- Revisions :
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-- Date Version Author Description
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-- 2018-04-03 1.0 bamberg Created
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.math_real.all;
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use ieee.numeric_std.all;
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use work.NOC_3D_PACKAGE.all;
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entity uxyd_routing is
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generic(
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Xis : natural := 1;
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Yis : natural := 1;
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Zis : natural := 1);
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--port_num : positive := 7;)
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port(
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address : in address_inf;
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enable : in std_logic;
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-- in dependence of the possible routes not all bit of "routing" are used
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routing : out std_logic_vector(6 downto 0));
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end uxyd_routing;
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architecture rtl of uxyd_routing is
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begin
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process(address, enable)
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begin
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routing <= (others => '0');
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if enable = '1' then
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if (to_integer(unsigned(address.z_dest)) > Zis) then
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routing(int_down) <= '1'; -- Route pos. Z
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elsif (to_integer(unsigned(address.x_dest)) < Xis) then
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routing(int_west) <= '1'; -- Route neg. X
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elsif (to_integer(unsigned(address.x_dest)) > Xis) then
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routing(int_east) <= '1'; -- Route pos. X
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elsif (to_integer(unsigned(address.y_dest)) < Yis) then
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routing(int_south) <= '1'; -- Route neg. Y
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elsif (to_integer(unsigned(address.y_dest)) > Yis) then
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routing(int_north) <= '1'; -- Route pos. Y
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elsif (to_integer(unsigned(address.z_dest)) < Zis) then
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routing(int_up) <= '1'; -- Route neg. Z
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else
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routing(int_local) <= '1'; -- Route local
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end if;
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end if;
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end process;
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end architecture;
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